nand/raw/gpio.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Updated, and converted to generic GPIO based driver by Russell King.
0004  *
0005  * Written by Ben Dooks <ben@simtec.co.uk>
0006  *   Based on 2.4 version by Mark Whittaker
0007  *
0008  * © 2004 Simtec Electronics
0009  *
0010  * Device driver for NAND flash that uses a memory mapped interface to
0011  * read/write the NAND commands and data, and GPIO pins for control signals
0012  * (the DT binding refers to this as "GPIO assisted NAND flash")
0013  */
0014
0015 #include <linux/kernel.h>
0016 #include <linux/err.h>
0017 #include <linux/slab.h>
0018 #include <linux/module.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/gpio/consumer.h>
0021 #include <linux/io.h>
0022 #include <linux/mtd/mtd.h>
0023 #include <linux/mtd/rawnand.h>
0024 #include <linux/mtd/partitions.h>
0025 #include <linux/mtd/nand-gpio.h>
0026 #include <linux/of.h>
0027 #include <linux/of_address.h>
0028 #include <linux/delay.h>
0029
0030 struct gpiomtd {
0031     struct nand_controller  base;
0032     void __iomem        *io;
0033     void __iomem        *io_sync;
0034     struct nand_chip    nand_chip;
0035     struct gpio_nand_platdata plat;
0036     struct gpio_desc *nce; /* Optional chip enable */
0037     struct gpio_desc *cle;
0038     struct gpio_desc *ale;
0039     struct gpio_desc *rdy;
0040     struct gpio_desc *nwp; /* Optional write protection */
0041 };
0042
0043 static inline struct gpiomtd *gpio_nand_getpriv(struct mtd_info *mtd)
0044 {
0045     return container_of(mtd_to_nand(mtd), struct gpiomtd, nand_chip);
0046 }
0047
0048
0049 #ifdef CONFIG_ARM
0050 /* gpio_nand_dosync()
0051  *
0052  * Make sure the GPIO state changes occur in-order with writes to NAND
0053  * memory region.
0054  * Needed on PXA due to bus-reordering within the SoC itself (see section on
0055  * I/O ordering in PXA manual (section 2.3, p35)
0056  */
0057 static void gpio_nand_dosync(struct gpiomtd *gpiomtd)
0058 {
0059     unsigned long tmp;
0060
0061     if (gpiomtd->io_sync) {
0062         /*
0063          * Linux memory barriers don't cater for what's required here.
0064          * What's required is what's here - a read from a separate
0065          * region with a dependency on that read.
0066          */
0067         tmp = readl(gpiomtd->io_sync);
0068         asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp));
0069     }
0070 }
0071 #else
0072 static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {}
0073 #endif
0074
0075 static int gpio_nand_exec_instr(struct nand_chip *chip,
0076                 const struct nand_op_instr *instr)
0077 {
0078     struct gpiomtd *gpiomtd = gpio_nand_getpriv(nand_to_mtd(chip));
0079     unsigned int i;
0080
0081     switch (instr->type) {
0082     case NAND_OP_CMD_INSTR:
0083         gpio_nand_dosync(gpiomtd);
0084         gpiod_set_value(gpiomtd->cle, 1);
0085         gpio_nand_dosync(gpiomtd);
0086         writeb(instr->ctx.cmd.opcode, gpiomtd->io);
0087         gpio_nand_dosync(gpiomtd);
0088         gpiod_set_value(gpiomtd->cle, 0);
0089         return 0;
0090
0091     case NAND_OP_ADDR_INSTR:
0092         gpio_nand_dosync(gpiomtd);
0093         gpiod_set_value(gpiomtd->ale, 1);
0094         gpio_nand_dosync(gpiomtd);
0095         for (i = 0; i < instr->ctx.addr.naddrs; i++)
0096             writeb(instr->ctx.addr.addrs[i], gpiomtd->io);
0097         gpio_nand_dosync(gpiomtd);
0098         gpiod_set_value(gpiomtd->ale, 0);
0099         return 0;
0100
0101     case NAND_OP_DATA_IN_INSTR:
0102         gpio_nand_dosync(gpiomtd);
0103         if ((chip->options & NAND_BUSWIDTH_16) &&
0104             !instr->ctx.data.force_8bit)
0105             ioread16_rep(gpiomtd->io, instr->ctx.data.buf.in,
0106                      instr->ctx.data.len / 2);
0107         else
0108             ioread8_rep(gpiomtd->io, instr->ctx.data.buf.in,
0109                     instr->ctx.data.len);
0110         return 0;
0111
0112     case NAND_OP_DATA_OUT_INSTR:
0113         gpio_nand_dosync(gpiomtd);
0114         if ((chip->options & NAND_BUSWIDTH_16) &&
0115             !instr->ctx.data.force_8bit)
0116             iowrite16_rep(gpiomtd->io, instr->ctx.data.buf.out,
0117                       instr->ctx.data.len / 2);
0118         else
0119             iowrite8_rep(gpiomtd->io, instr->ctx.data.buf.out,
0120                      instr->ctx.data.len);
0121         return 0;
0122
0123     case NAND_OP_WAITRDY_INSTR:
0124         if (!gpiomtd->rdy)
0125             return nand_soft_waitrdy(chip, instr->ctx.waitrdy.timeout_ms);
0126
0127         return nand_gpio_waitrdy(chip, gpiomtd->rdy,
0128                      instr->ctx.waitrdy.timeout_ms);
0129
0130     default:
0131         return -EINVAL;
0132     }
0133
0134     return 0;
0135 }
0136
0137 static int gpio_nand_exec_op(struct nand_chip *chip,
0138                  const struct nand_operation *op,
0139                  bool check_only)
0140 {
0141     struct gpiomtd *gpiomtd = gpio_nand_getpriv(nand_to_mtd(chip));
0142     unsigned int i;
0143     int ret = 0;
0144
0145     if (check_only)
0146         return 0;
0147
0148     gpio_nand_dosync(gpiomtd);
0149     gpiod_set_value(gpiomtd->nce, 0);
0150     for (i = 0; i < op->ninstrs; i++) {
0151         ret = gpio_nand_exec_instr(chip, &op->instrs[i]);
0152         if (ret)
0153             break;
0154
0155         if (op->instrs[i].delay_ns)
0156             ndelay(op->instrs[i].delay_ns);
0157     }
0158     gpio_nand_dosync(gpiomtd);
0159     gpiod_set_value(gpiomtd->nce, 1);
0160
0161     return ret;
0162 }
0163
0164 static int gpio_nand_attach_chip(struct nand_chip *chip)
0165 {
0166     if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
0167         chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
0168         chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
0169
0170     return 0;
0171 }
0172
0173 static const struct nand_controller_ops gpio_nand_ops = {
0174     .exec_op = gpio_nand_exec_op,
0175     .attach_chip = gpio_nand_attach_chip,
0176 };
0177
0178 #ifdef CONFIG_OF
0179 static const struct of_device_id gpio_nand_id_table[] = {
0180     { .compatible = "gpio-control-nand" },
0181     {}
0182 };
0183 MODULE_DEVICE_TABLE(of, gpio_nand_id_table);
0184
0185 static int gpio_nand_get_config_of(const struct device *dev,
0186                    struct gpio_nand_platdata *plat)
0187 {
0188     u32 val;
0189
0190     if (!dev->of_node)
0191         return -ENODEV;
0192
0193     if (!of_property_read_u32(dev->of_node, "bank-width", &val)) {
0194         if (val == 2) {
0195             plat->options |= NAND_BUSWIDTH_16;
0196         } else if (val != 1) {
0197             dev_err(dev, "invalid bank-width %u\n", val);
0198             return -EINVAL;
0199         }
0200     }
0201
0202     if (!of_property_read_u32(dev->of_node, "chip-delay", &val))
0203         plat->chip_delay = val;
0204
0205     return 0;
0206 }
0207
0208 static struct resource *gpio_nand_get_io_sync_of(struct platform_device *pdev)
0209 {
0210     struct resource *r;
0211     u64 addr;
0212
0213     if (of_property_read_u64(pdev->dev.of_node,
0214                        "gpio-control-nand,io-sync-reg", &addr))
0215         return NULL;
0216
0217     r = devm_kzalloc(&pdev->dev, sizeof(*r), GFP_KERNEL);
0218     if (!r)
0219         return NULL;
0220
0221     r->start = addr;
0222     r->end = r->start + 0x3;
0223     r->flags = IORESOURCE_MEM;
0224
0225     return r;
0226 }
0227 #else /* CONFIG_OF */
0228 static inline int gpio_nand_get_config_of(const struct device *dev,
0229                       struct gpio_nand_platdata *plat)
0230 {
0231     return -ENOSYS;
0232 }
0233
0234 static inline struct resource *
0235 gpio_nand_get_io_sync_of(struct platform_device *pdev)
0236 {
0237     return NULL;
0238 }
0239 #endif /* CONFIG_OF */
0240
0241 static inline int gpio_nand_get_config(const struct device *dev,
0242                        struct gpio_nand_platdata *plat)
0243 {
0244     int ret = gpio_nand_get_config_of(dev, plat);
0245
0246     if (!ret)
0247         return ret;
0248
0249     if (dev_get_platdata(dev)) {
0250         memcpy(plat, dev_get_platdata(dev), sizeof(*plat));
0251         return 0;
0252     }
0253
0254     return -EINVAL;
0255 }
0256
0257 static inline struct resource *
0258 gpio_nand_get_io_sync(struct platform_device *pdev)
0259 {
0260     struct resource *r = gpio_nand_get_io_sync_of(pdev);
0261
0262     if (r)
0263         return r;
0264
0265     return platform_get_resource(pdev, IORESOURCE_MEM, 1);
0266 }
0267
0268 static int gpio_nand_remove(struct platform_device *pdev)
0269 {
0270     struct gpiomtd *gpiomtd = platform_get_drvdata(pdev);
0271     struct nand_chip *chip = &gpiomtd->nand_chip;
0272     int ret;
0273
0274     ret = mtd_device_unregister(nand_to_mtd(chip));
0275     WARN_ON(ret);
0276     nand_cleanup(chip);
0277
0278     /* Enable write protection and disable the chip */
0279     if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp))
0280         gpiod_set_value(gpiomtd->nwp, 0);
0281     if (gpiomtd->nce && !IS_ERR(gpiomtd->nce))
0282         gpiod_set_value(gpiomtd->nce, 0);
0283
0284     return 0;
0285 }
0286
0287 static int gpio_nand_probe(struct platform_device *pdev)
0288 {
0289     struct gpiomtd *gpiomtd;
0290     struct nand_chip *chip;
0291     struct mtd_info *mtd;
0292     struct resource *res;
0293     struct device *dev = &pdev->dev;
0294     int ret = 0;
0295
0296     if (!dev->of_node && !dev_get_platdata(dev))
0297         return -EINVAL;
0298
0299     gpiomtd = devm_kzalloc(dev, sizeof(*gpiomtd), GFP_KERNEL);
0300     if (!gpiomtd)
0301         return -ENOMEM;
0302
0303     chip = &gpiomtd->nand_chip;
0304
0305     gpiomtd->io = devm_platform_ioremap_resource(pdev, 0);
0306     if (IS_ERR(gpiomtd->io))
0307         return PTR_ERR(gpiomtd->io);
0308
0309     res = gpio_nand_get_io_sync(pdev);
0310     if (res) {
0311         gpiomtd->io_sync = devm_ioremap_resource(dev, res);
0312         if (IS_ERR(gpiomtd->io_sync))
0313             return PTR_ERR(gpiomtd->io_sync);
0314     }
0315
0316     ret = gpio_nand_get_config(dev, &gpiomtd->plat);
0317     if (ret)
0318         return ret;
0319
0320     /* Just enable the chip */
0321     gpiomtd->nce = devm_gpiod_get_optional(dev, "nce", GPIOD_OUT_HIGH);
0322     if (IS_ERR(gpiomtd->nce))
0323         return PTR_ERR(gpiomtd->nce);
0324
0325     /* We disable write protection once we know probe() will succeed */
0326     gpiomtd->nwp = devm_gpiod_get_optional(dev, "nwp", GPIOD_OUT_LOW);
0327     if (IS_ERR(gpiomtd->nwp)) {
0328         ret = PTR_ERR(gpiomtd->nwp);
0329         goto out_ce;
0330     }
0331
0332     gpiomtd->ale = devm_gpiod_get(dev, "ale", GPIOD_OUT_LOW);
0333     if (IS_ERR(gpiomtd->ale)) {
0334         ret = PTR_ERR(gpiomtd->ale);
0335         goto out_ce;
0336     }
0337
0338     gpiomtd->cle = devm_gpiod_get(dev, "cle", GPIOD_OUT_LOW);
0339     if (IS_ERR(gpiomtd->cle)) {
0340         ret = PTR_ERR(gpiomtd->cle);
0341         goto out_ce;
0342     }
0343
0344     gpiomtd->rdy = devm_gpiod_get_optional(dev, "rdy", GPIOD_IN);
0345     if (IS_ERR(gpiomtd->rdy)) {
0346         ret = PTR_ERR(gpiomtd->rdy);
0347         goto out_ce;
0348     }
0349
0350     nand_controller_init(&gpiomtd->base);
0351     gpiomtd->base.ops = &gpio_nand_ops;
0352
0353     nand_set_flash_node(chip, pdev->dev.of_node);
0354     chip->options       = gpiomtd->plat.options;
0355     chip->controller    = &gpiomtd->base;
0356
0357     mtd         = nand_to_mtd(chip);
0358     mtd->dev.parent     = dev;
0359
0360     platform_set_drvdata(pdev, gpiomtd);
0361
0362     /* Disable write protection, if wired up */
0363     if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp))
0364         gpiod_direction_output(gpiomtd->nwp, 1);
0365
0366     /*
0367      * This driver assumes that the default ECC engine should be TYPE_SOFT.
0368      * Set ->engine_type before registering the NAND devices in order to
0369      * provide a driver specific default value.
0370      */
0371     chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
0372
0373     ret = nand_scan(chip, 1);
0374     if (ret)
0375         goto err_wp;
0376
0377     if (gpiomtd->plat.adjust_parts)
0378         gpiomtd->plat.adjust_parts(&gpiomtd->plat, mtd->size);
0379
0380     ret = mtd_device_register(mtd, gpiomtd->plat.parts,
0381                   gpiomtd->plat.num_parts);
0382     if (!ret)
0383         return 0;
0384
0385 err_wp:
0386     if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp))
0387         gpiod_set_value(gpiomtd->nwp, 0);
0388 out_ce:
0389     if (gpiomtd->nce && !IS_ERR(gpiomtd->nce))
0390         gpiod_set_value(gpiomtd->nce, 0);
0391
0392     return ret;
0393 }
0394
0395 static struct platform_driver gpio_nand_driver = {
0396     .probe      = gpio_nand_probe,
0397     .remove     = gpio_nand_remove,
0398     .driver     = {
0399         .name   = "gpio-nand",
0400         .of_match_table = of_match_ptr(gpio_nand_id_table),
0401     },
0402 };
0403
0404 module_platform_driver(gpio_nand_driver);
0405
0406 MODULE_LICENSE("GPL");
0407 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
0408 MODULE_DESCRIPTION("GPIO NAND Driver");