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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * ST Microelectronics
0004  * Flexible Static Memory Controller (FSMC)
0005  * Driver for NAND portions
0006  *
0007  * Copyright © 2010 ST Microelectronics
0008  * Vipin Kumar <vipin.kumar@st.com>
0009  * Ashish Priyadarshi
0010  *
0011  * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
0012  *  Copyright © 2007 STMicroelectronics Pvt. Ltd.
0013  *  Copyright © 2009 Alessandro Rubini
0014  */
0015 
0016 #include <linux/clk.h>
0017 #include <linux/completion.h>
0018 #include <linux/delay.h>
0019 #include <linux/dmaengine.h>
0020 #include <linux/dma-direction.h>
0021 #include <linux/dma-mapping.h>
0022 #include <linux/err.h>
0023 #include <linux/init.h>
0024 #include <linux/module.h>
0025 #include <linux/resource.h>
0026 #include <linux/sched.h>
0027 #include <linux/types.h>
0028 #include <linux/mtd/mtd.h>
0029 #include <linux/mtd/nand-ecc-sw-hamming.h>
0030 #include <linux/mtd/rawnand.h>
0031 #include <linux/platform_device.h>
0032 #include <linux/of.h>
0033 #include <linux/mtd/partitions.h>
0034 #include <linux/io.h>
0035 #include <linux/slab.h>
0036 #include <linux/amba/bus.h>
0037 #include <mtd/mtd-abi.h>
0038 
0039 /* fsmc controller registers for NOR flash */
0040 #define CTRL            0x0
0041     /* ctrl register definitions */
0042     #define BANK_ENABLE     BIT(0)
0043     #define MUXED           BIT(1)
0044     #define NOR_DEV         (2 << 2)
0045     #define WIDTH_16        BIT(4)
0046     #define RSTPWRDWN       BIT(6)
0047     #define WPROT           BIT(7)
0048     #define WRT_ENABLE      BIT(12)
0049     #define WAIT_ENB        BIT(13)
0050 
0051 #define CTRL_TIM        0x4
0052     /* ctrl_tim register definitions */
0053 
0054 #define FSMC_NOR_BANK_SZ    0x8
0055 #define FSMC_NOR_REG_SIZE   0x40
0056 
0057 #define FSMC_NOR_REG(base, bank, reg)   ((base) +           \
0058                      (FSMC_NOR_BANK_SZ * (bank)) +  \
0059                      (reg))
0060 
0061 /* fsmc controller registers for NAND flash */
0062 #define FSMC_PC         0x00
0063     /* pc register definitions */
0064     #define FSMC_RESET      BIT(0)
0065     #define FSMC_WAITON     BIT(1)
0066     #define FSMC_ENABLE     BIT(2)
0067     #define FSMC_DEVTYPE_NAND   BIT(3)
0068     #define FSMC_DEVWID_16      BIT(4)
0069     #define FSMC_ECCEN      BIT(6)
0070     #define FSMC_ECCPLEN_256    BIT(7)
0071     #define FSMC_TCLR_SHIFT     (9)
0072     #define FSMC_TCLR_MASK      (0xF)
0073     #define FSMC_TAR_SHIFT      (13)
0074     #define FSMC_TAR_MASK       (0xF)
0075 #define STS         0x04
0076     /* sts register definitions */
0077     #define FSMC_CODE_RDY       BIT(15)
0078 #define COMM            0x08
0079     /* comm register definitions */
0080     #define FSMC_TSET_SHIFT     0
0081     #define FSMC_TSET_MASK      0xFF
0082     #define FSMC_TWAIT_SHIFT    8
0083     #define FSMC_TWAIT_MASK     0xFF
0084     #define FSMC_THOLD_SHIFT    16
0085     #define FSMC_THOLD_MASK     0xFF
0086     #define FSMC_THIZ_SHIFT     24
0087     #define FSMC_THIZ_MASK      0xFF
0088 #define ATTRIB          0x0C
0089 #define IOATA           0x10
0090 #define ECC1            0x14
0091 #define ECC2            0x18
0092 #define ECC3            0x1C
0093 #define FSMC_NAND_BANK_SZ   0x20
0094 
0095 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
0096 
0097 /*
0098  * According to SPEAr300 Reference Manual (RM0082)
0099  *  TOUDEL = 7ns (Output delay from the flip-flops to the board)
0100  *  TINDEL = 5ns (Input delay from the board to the flipflop)
0101  */
0102 #define TOUTDEL 7000
0103 #define TINDEL  5000
0104 
0105 struct fsmc_nand_timings {
0106     u8 tclr;
0107     u8 tar;
0108     u8 thiz;
0109     u8 thold;
0110     u8 twait;
0111     u8 tset;
0112 };
0113 
0114 enum access_mode {
0115     USE_DMA_ACCESS = 1,
0116     USE_WORD_ACCESS,
0117 };
0118 
0119 /**
0120  * struct fsmc_nand_data - structure for FSMC NAND device state
0121  *
0122  * @base:       Inherit from the nand_controller struct
0123  * @pid:        Part ID on the AMBA PrimeCell format
0124  * @nand:       Chip related info for a NAND flash.
0125  *
0126  * @bank:       Bank number for probed device.
0127  * @dev:        Parent device
0128  * @mode:       Access mode
0129  * @clk:        Clock structure for FSMC.
0130  *
0131  * @read_dma_chan:  DMA channel for read access
0132  * @write_dma_chan: DMA channel for write access to NAND
0133  * @dma_access_complete: Completion structure
0134  *
0135  * @dev_timings:    NAND timings
0136  *
0137  * @data_pa:        NAND Physical port for Data.
0138  * @data_va:        NAND port for Data.
0139  * @cmd_va:     NAND port for Command.
0140  * @addr_va:        NAND port for Address.
0141  * @regs_va:        Registers base address for a given bank.
0142  */
0143 struct fsmc_nand_data {
0144     struct nand_controller  base;
0145     u32         pid;
0146     struct nand_chip    nand;
0147 
0148     unsigned int        bank;
0149     struct device       *dev;
0150     enum access_mode    mode;
0151     struct clk      *clk;
0152 
0153     /* DMA related objects */
0154     struct dma_chan     *read_dma_chan;
0155     struct dma_chan     *write_dma_chan;
0156     struct completion   dma_access_complete;
0157 
0158     struct fsmc_nand_timings *dev_timings;
0159 
0160     dma_addr_t      data_pa;
0161     void __iomem        *data_va;
0162     void __iomem        *cmd_va;
0163     void __iomem        *addr_va;
0164     void __iomem        *regs_va;
0165 };
0166 
0167 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
0168                    struct mtd_oob_region *oobregion)
0169 {
0170     struct nand_chip *chip = mtd_to_nand(mtd);
0171 
0172     if (section >= chip->ecc.steps)
0173         return -ERANGE;
0174 
0175     oobregion->offset = (section * 16) + 2;
0176     oobregion->length = 3;
0177 
0178     return 0;
0179 }
0180 
0181 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
0182                     struct mtd_oob_region *oobregion)
0183 {
0184     struct nand_chip *chip = mtd_to_nand(mtd);
0185 
0186     if (section >= chip->ecc.steps)
0187         return -ERANGE;
0188 
0189     oobregion->offset = (section * 16) + 8;
0190 
0191     if (section < chip->ecc.steps - 1)
0192         oobregion->length = 8;
0193     else
0194         oobregion->length = mtd->oobsize - oobregion->offset;
0195 
0196     return 0;
0197 }
0198 
0199 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
0200     .ecc = fsmc_ecc1_ooblayout_ecc,
0201     .free = fsmc_ecc1_ooblayout_free,
0202 };
0203 
0204 /*
0205  * ECC placement definitions in oobfree type format.
0206  * There are 13 bytes of ecc for every 512 byte block and it has to be read
0207  * consecutively and immediately after the 512 byte data block for hardware to
0208  * generate the error bit offsets in 512 byte data.
0209  */
0210 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
0211                    struct mtd_oob_region *oobregion)
0212 {
0213     struct nand_chip *chip = mtd_to_nand(mtd);
0214 
0215     if (section >= chip->ecc.steps)
0216         return -ERANGE;
0217 
0218     oobregion->length = chip->ecc.bytes;
0219 
0220     if (!section && mtd->writesize <= 512)
0221         oobregion->offset = 0;
0222     else
0223         oobregion->offset = (section * 16) + 2;
0224 
0225     return 0;
0226 }
0227 
0228 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
0229                     struct mtd_oob_region *oobregion)
0230 {
0231     struct nand_chip *chip = mtd_to_nand(mtd);
0232 
0233     if (section >= chip->ecc.steps)
0234         return -ERANGE;
0235 
0236     oobregion->offset = (section * 16) + 15;
0237 
0238     if (section < chip->ecc.steps - 1)
0239         oobregion->length = 3;
0240     else
0241         oobregion->length = mtd->oobsize - oobregion->offset;
0242 
0243     return 0;
0244 }
0245 
0246 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
0247     .ecc = fsmc_ecc4_ooblayout_ecc,
0248     .free = fsmc_ecc4_ooblayout_free,
0249 };
0250 
0251 static inline struct fsmc_nand_data *nand_to_fsmc(struct nand_chip *chip)
0252 {
0253     return container_of(chip, struct fsmc_nand_data, nand);
0254 }
0255 
0256 /*
0257  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
0258  *
0259  * This routine initializes timing parameters related to NAND memory access in
0260  * FSMC registers
0261  */
0262 static void fsmc_nand_setup(struct fsmc_nand_data *host,
0263                 struct fsmc_nand_timings *tims)
0264 {
0265     u32 value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
0266     u32 tclr, tar, thiz, thold, twait, tset;
0267 
0268     tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
0269     tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
0270     thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
0271     thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
0272     twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
0273     tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
0274 
0275     if (host->nand.options & NAND_BUSWIDTH_16)
0276         value |= FSMC_DEVWID_16;
0277 
0278     writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC);
0279     writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM);
0280     writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB);
0281 }
0282 
0283 static int fsmc_calc_timings(struct fsmc_nand_data *host,
0284                  const struct nand_sdr_timings *sdrt,
0285                  struct fsmc_nand_timings *tims)
0286 {
0287     unsigned long hclk = clk_get_rate(host->clk);
0288     unsigned long hclkn = NSEC_PER_SEC / hclk;
0289     u32 thiz, thold, twait, tset, twait_min;
0290 
0291     if (sdrt->tRC_min < 30000)
0292         return -EOPNOTSUPP;
0293 
0294     tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1;
0295     if (tims->tar > FSMC_TAR_MASK)
0296         tims->tar = FSMC_TAR_MASK;
0297     tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1;
0298     if (tims->tclr > FSMC_TCLR_MASK)
0299         tims->tclr = FSMC_TCLR_MASK;
0300 
0301     thiz = sdrt->tCS_min - sdrt->tWP_min;
0302     tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn);
0303 
0304     thold = sdrt->tDH_min;
0305     if (thold < sdrt->tCH_min)
0306         thold = sdrt->tCH_min;
0307     if (thold < sdrt->tCLH_min)
0308         thold = sdrt->tCLH_min;
0309     if (thold < sdrt->tWH_min)
0310         thold = sdrt->tWH_min;
0311     if (thold < sdrt->tALH_min)
0312         thold = sdrt->tALH_min;
0313     if (thold < sdrt->tREH_min)
0314         thold = sdrt->tREH_min;
0315     tims->thold = DIV_ROUND_UP(thold / 1000, hclkn);
0316     if (tims->thold == 0)
0317         tims->thold = 1;
0318     else if (tims->thold > FSMC_THOLD_MASK)
0319         tims->thold = FSMC_THOLD_MASK;
0320 
0321     tset = max(sdrt->tCS_min - sdrt->tWP_min,
0322            sdrt->tCEA_max - sdrt->tREA_max);
0323     tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1;
0324     if (tims->tset == 0)
0325         tims->tset = 1;
0326     else if (tims->tset > FSMC_TSET_MASK)
0327         tims->tset = FSMC_TSET_MASK;
0328 
0329     /*
0330      * According to SPEAr300 Reference Manual (RM0082) which gives more
0331      * information related to FSMSC timings than the SPEAr600 one (RM0305),
0332      *   twait >= tCEA - (tset * TCLK) + TOUTDEL + TINDEL
0333      */
0334     twait_min = sdrt->tCEA_max - ((tims->tset + 1) * hclkn * 1000)
0335             + TOUTDEL + TINDEL;
0336     twait = max3(sdrt->tRP_min, sdrt->tWP_min, twait_min);
0337 
0338     tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1;
0339     if (tims->twait == 0)
0340         tims->twait = 1;
0341     else if (tims->twait > FSMC_TWAIT_MASK)
0342         tims->twait = FSMC_TWAIT_MASK;
0343 
0344     return 0;
0345 }
0346 
0347 static int fsmc_setup_interface(struct nand_chip *nand, int csline,
0348                 const struct nand_interface_config *conf)
0349 {
0350     struct fsmc_nand_data *host = nand_to_fsmc(nand);
0351     struct fsmc_nand_timings tims;
0352     const struct nand_sdr_timings *sdrt;
0353     int ret;
0354 
0355     sdrt = nand_get_sdr_timings(conf);
0356     if (IS_ERR(sdrt))
0357         return PTR_ERR(sdrt);
0358 
0359     ret = fsmc_calc_timings(host, sdrt, &tims);
0360     if (ret)
0361         return ret;
0362 
0363     if (csline == NAND_DATA_IFACE_CHECK_ONLY)
0364         return 0;
0365 
0366     fsmc_nand_setup(host, &tims);
0367 
0368     return 0;
0369 }
0370 
0371 /*
0372  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
0373  */
0374 static void fsmc_enable_hwecc(struct nand_chip *chip, int mode)
0375 {
0376     struct fsmc_nand_data *host = nand_to_fsmc(chip);
0377 
0378     writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256,
0379                host->regs_va + FSMC_PC);
0380     writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCEN,
0381                host->regs_va + FSMC_PC);
0382     writel_relaxed(readl(host->regs_va + FSMC_PC) | FSMC_ECCEN,
0383                host->regs_va + FSMC_PC);
0384 }
0385 
0386 /*
0387  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
0388  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
0389  * max of 8-bits)
0390  */
0391 static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const u8 *data,
0392                 u8 *ecc)
0393 {
0394     struct fsmc_nand_data *host = nand_to_fsmc(chip);
0395     u32 ecc_tmp;
0396     unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
0397 
0398     do {
0399         if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY)
0400             break;
0401 
0402         cond_resched();
0403     } while (!time_after_eq(jiffies, deadline));
0404 
0405     if (time_after_eq(jiffies, deadline)) {
0406         dev_err(host->dev, "calculate ecc timed out\n");
0407         return -ETIMEDOUT;
0408     }
0409 
0410     ecc_tmp = readl_relaxed(host->regs_va + ECC1);
0411     ecc[0] = ecc_tmp;
0412     ecc[1] = ecc_tmp >> 8;
0413     ecc[2] = ecc_tmp >> 16;
0414     ecc[3] = ecc_tmp >> 24;
0415 
0416     ecc_tmp = readl_relaxed(host->regs_va + ECC2);
0417     ecc[4] = ecc_tmp;
0418     ecc[5] = ecc_tmp >> 8;
0419     ecc[6] = ecc_tmp >> 16;
0420     ecc[7] = ecc_tmp >> 24;
0421 
0422     ecc_tmp = readl_relaxed(host->regs_va + ECC3);
0423     ecc[8] = ecc_tmp;
0424     ecc[9] = ecc_tmp >> 8;
0425     ecc[10] = ecc_tmp >> 16;
0426     ecc[11] = ecc_tmp >> 24;
0427 
0428     ecc_tmp = readl_relaxed(host->regs_va + STS);
0429     ecc[12] = ecc_tmp >> 16;
0430 
0431     return 0;
0432 }
0433 
0434 /*
0435  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
0436  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
0437  * max of 1-bit)
0438  */
0439 static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const u8 *data,
0440                 u8 *ecc)
0441 {
0442     struct fsmc_nand_data *host = nand_to_fsmc(chip);
0443     u32 ecc_tmp;
0444 
0445     ecc_tmp = readl_relaxed(host->regs_va + ECC1);
0446     ecc[0] = ecc_tmp;
0447     ecc[1] = ecc_tmp >> 8;
0448     ecc[2] = ecc_tmp >> 16;
0449 
0450     return 0;
0451 }
0452 
0453 static int fsmc_correct_ecc1(struct nand_chip *chip,
0454                  unsigned char *buf,
0455                  unsigned char *read_ecc,
0456                  unsigned char *calc_ecc)
0457 {
0458     bool sm_order = chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER;
0459 
0460     return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
0461                       chip->ecc.size, sm_order);
0462 }
0463 
0464 /* Count the number of 0's in buff upto a max of max_bits */
0465 static int count_written_bits(u8 *buff, int size, int max_bits)
0466 {
0467     int k, written_bits = 0;
0468 
0469     for (k = 0; k < size; k++) {
0470         written_bits += hweight8(~buff[k]);
0471         if (written_bits > max_bits)
0472             break;
0473     }
0474 
0475     return written_bits;
0476 }
0477 
0478 static void dma_complete(void *param)
0479 {
0480     struct fsmc_nand_data *host = param;
0481 
0482     complete(&host->dma_access_complete);
0483 }
0484 
0485 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
0486             enum dma_data_direction direction)
0487 {
0488     struct dma_chan *chan;
0489     struct dma_device *dma_dev;
0490     struct dma_async_tx_descriptor *tx;
0491     dma_addr_t dma_dst, dma_src, dma_addr;
0492     dma_cookie_t cookie;
0493     unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
0494     int ret;
0495     unsigned long time_left;
0496 
0497     if (direction == DMA_TO_DEVICE)
0498         chan = host->write_dma_chan;
0499     else if (direction == DMA_FROM_DEVICE)
0500         chan = host->read_dma_chan;
0501     else
0502         return -EINVAL;
0503 
0504     dma_dev = chan->device;
0505     dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
0506 
0507     if (direction == DMA_TO_DEVICE) {
0508         dma_src = dma_addr;
0509         dma_dst = host->data_pa;
0510     } else {
0511         dma_src = host->data_pa;
0512         dma_dst = dma_addr;
0513     }
0514 
0515     tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
0516             len, flags);
0517     if (!tx) {
0518         dev_err(host->dev, "device_prep_dma_memcpy error\n");
0519         ret = -EIO;
0520         goto unmap_dma;
0521     }
0522 
0523     tx->callback = dma_complete;
0524     tx->callback_param = host;
0525     cookie = tx->tx_submit(tx);
0526 
0527     ret = dma_submit_error(cookie);
0528     if (ret) {
0529         dev_err(host->dev, "dma_submit_error %d\n", cookie);
0530         goto unmap_dma;
0531     }
0532 
0533     dma_async_issue_pending(chan);
0534 
0535     time_left =
0536     wait_for_completion_timeout(&host->dma_access_complete,
0537                     msecs_to_jiffies(3000));
0538     if (time_left == 0) {
0539         dmaengine_terminate_all(chan);
0540         dev_err(host->dev, "wait_for_completion_timeout\n");
0541         ret = -ETIMEDOUT;
0542         goto unmap_dma;
0543     }
0544 
0545     ret = 0;
0546 
0547 unmap_dma:
0548     dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
0549 
0550     return ret;
0551 }
0552 
0553 /*
0554  * fsmc_write_buf - write buffer to chip
0555  * @host:   FSMC NAND controller
0556  * @buf:    data buffer
0557  * @len:    number of bytes to write
0558  */
0559 static void fsmc_write_buf(struct fsmc_nand_data *host, const u8 *buf,
0560                int len)
0561 {
0562     int i;
0563 
0564     if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
0565         IS_ALIGNED(len, sizeof(u32))) {
0566         u32 *p = (u32 *)buf;
0567 
0568         len = len >> 2;
0569         for (i = 0; i < len; i++)
0570             writel_relaxed(p[i], host->data_va);
0571     } else {
0572         for (i = 0; i < len; i++)
0573             writeb_relaxed(buf[i], host->data_va);
0574     }
0575 }
0576 
0577 /*
0578  * fsmc_read_buf - read chip data into buffer
0579  * @host:   FSMC NAND controller
0580  * @buf:    buffer to store date
0581  * @len:    number of bytes to read
0582  */
0583 static void fsmc_read_buf(struct fsmc_nand_data *host, u8 *buf, int len)
0584 {
0585     int i;
0586 
0587     if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
0588         IS_ALIGNED(len, sizeof(u32))) {
0589         u32 *p = (u32 *)buf;
0590 
0591         len = len >> 2;
0592         for (i = 0; i < len; i++)
0593             p[i] = readl_relaxed(host->data_va);
0594     } else {
0595         for (i = 0; i < len; i++)
0596             buf[i] = readb_relaxed(host->data_va);
0597     }
0598 }
0599 
0600 /*
0601  * fsmc_read_buf_dma - read chip data into buffer
0602  * @host:   FSMC NAND controller
0603  * @buf:    buffer to store date
0604  * @len:    number of bytes to read
0605  */
0606 static void fsmc_read_buf_dma(struct fsmc_nand_data *host, u8 *buf,
0607                   int len)
0608 {
0609     dma_xfer(host, buf, len, DMA_FROM_DEVICE);
0610 }
0611 
0612 /*
0613  * fsmc_write_buf_dma - write buffer to chip
0614  * @host:   FSMC NAND controller
0615  * @buf:    data buffer
0616  * @len:    number of bytes to write
0617  */
0618 static void fsmc_write_buf_dma(struct fsmc_nand_data *host, const u8 *buf,
0619                    int len)
0620 {
0621     dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
0622 }
0623 
0624 /*
0625  * fsmc_exec_op - hook called by the core to execute NAND operations
0626  *
0627  * This controller is simple enough and thus does not need to use the parser
0628  * provided by the core, instead, handle every situation here.
0629  */
0630 static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op,
0631             bool check_only)
0632 {
0633     struct fsmc_nand_data *host = nand_to_fsmc(chip);
0634     const struct nand_op_instr *instr = NULL;
0635     int ret = 0;
0636     unsigned int op_id;
0637     int i;
0638 
0639     if (check_only)
0640         return 0;
0641 
0642     pr_debug("Executing operation [%d instructions]:\n", op->ninstrs);
0643 
0644     for (op_id = 0; op_id < op->ninstrs; op_id++) {
0645         instr = &op->instrs[op_id];
0646 
0647         nand_op_trace("  ", instr);
0648 
0649         switch (instr->type) {
0650         case NAND_OP_CMD_INSTR:
0651             writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va);
0652             break;
0653 
0654         case NAND_OP_ADDR_INSTR:
0655             for (i = 0; i < instr->ctx.addr.naddrs; i++)
0656                 writeb_relaxed(instr->ctx.addr.addrs[i],
0657                            host->addr_va);
0658             break;
0659 
0660         case NAND_OP_DATA_IN_INSTR:
0661             if (host->mode == USE_DMA_ACCESS)
0662                 fsmc_read_buf_dma(host, instr->ctx.data.buf.in,
0663                           instr->ctx.data.len);
0664             else
0665                 fsmc_read_buf(host, instr->ctx.data.buf.in,
0666                           instr->ctx.data.len);
0667             break;
0668 
0669         case NAND_OP_DATA_OUT_INSTR:
0670             if (host->mode == USE_DMA_ACCESS)
0671                 fsmc_write_buf_dma(host,
0672                            instr->ctx.data.buf.out,
0673                            instr->ctx.data.len);
0674             else
0675                 fsmc_write_buf(host, instr->ctx.data.buf.out,
0676                            instr->ctx.data.len);
0677             break;
0678 
0679         case NAND_OP_WAITRDY_INSTR:
0680             ret = nand_soft_waitrdy(chip,
0681                         instr->ctx.waitrdy.timeout_ms);
0682             break;
0683         }
0684 
0685         if (instr->delay_ns)
0686             ndelay(instr->delay_ns);
0687     }
0688 
0689     return ret;
0690 }
0691 
0692 /*
0693  * fsmc_read_page_hwecc
0694  * @chip:   nand chip info structure
0695  * @buf:    buffer to store read data
0696  * @oob_required:   caller expects OOB data read to chip->oob_poi
0697  * @page:   page number to read
0698  *
0699  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
0700  * performed in a strict sequence as follows:
0701  * data(512 byte) -> ecc(13 byte)
0702  * After this read, fsmc hardware generates and reports error data bits(up to a
0703  * max of 8 bits)
0704  */
0705 static int fsmc_read_page_hwecc(struct nand_chip *chip, u8 *buf,
0706                 int oob_required, int page)
0707 {
0708     struct mtd_info *mtd = nand_to_mtd(chip);
0709     int i, j, s, stat, eccsize = chip->ecc.size;
0710     int eccbytes = chip->ecc.bytes;
0711     int eccsteps = chip->ecc.steps;
0712     u8 *p = buf;
0713     u8 *ecc_calc = chip->ecc.calc_buf;
0714     u8 *ecc_code = chip->ecc.code_buf;
0715     int off, len, ret, group = 0;
0716     /*
0717      * ecc_oob is intentionally taken as u16. In 16bit devices, we
0718      * end up reading 14 bytes (7 words) from oob. The local array is
0719      * to maintain word alignment
0720      */
0721     u16 ecc_oob[7];
0722     u8 *oob = (u8 *)&ecc_oob[0];
0723     unsigned int max_bitflips = 0;
0724 
0725     for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
0726         nand_read_page_op(chip, page, s * eccsize, NULL, 0);
0727         chip->ecc.hwctl(chip, NAND_ECC_READ);
0728         ret = nand_read_data_op(chip, p, eccsize, false, false);
0729         if (ret)
0730             return ret;
0731 
0732         for (j = 0; j < eccbytes;) {
0733             struct mtd_oob_region oobregion;
0734 
0735             ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
0736             if (ret)
0737                 return ret;
0738 
0739             off = oobregion.offset;
0740             len = oobregion.length;
0741 
0742             /*
0743              * length is intentionally kept a higher multiple of 2
0744              * to read at least 13 bytes even in case of 16 bit NAND
0745              * devices
0746              */
0747             if (chip->options & NAND_BUSWIDTH_16)
0748                 len = roundup(len, 2);
0749 
0750             nand_read_oob_op(chip, page, off, oob + j, len);
0751             j += len;
0752         }
0753 
0754         memcpy(&ecc_code[i], oob, chip->ecc.bytes);
0755         chip->ecc.calculate(chip, p, &ecc_calc[i]);
0756 
0757         stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
0758         if (stat < 0) {
0759             mtd->ecc_stats.failed++;
0760         } else {
0761             mtd->ecc_stats.corrected += stat;
0762             max_bitflips = max_t(unsigned int, max_bitflips, stat);
0763         }
0764     }
0765 
0766     return max_bitflips;
0767 }
0768 
0769 /*
0770  * fsmc_bch8_correct_data
0771  * @mtd:    mtd info structure
0772  * @dat:    buffer of read data
0773  * @read_ecc:   ecc read from device spare area
0774  * @calc_ecc:   ecc calculated from read data
0775  *
0776  * calc_ecc is a 104 bit information containing maximum of 8 error
0777  * offset information of 13 bits each in 512 bytes of read data.
0778  */
0779 static int fsmc_bch8_correct_data(struct nand_chip *chip, u8 *dat,
0780                   u8 *read_ecc, u8 *calc_ecc)
0781 {
0782     struct fsmc_nand_data *host = nand_to_fsmc(chip);
0783     u32 err_idx[8];
0784     u32 num_err, i;
0785     u32 ecc1, ecc2, ecc3, ecc4;
0786 
0787     num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF;
0788 
0789     /* no bit flipping */
0790     if (likely(num_err == 0))
0791         return 0;
0792 
0793     /* too many errors */
0794     if (unlikely(num_err > 8)) {
0795         /*
0796          * This is a temporary erase check. A newly erased page read
0797          * would result in an ecc error because the oob data is also
0798          * erased to FF and the calculated ecc for an FF data is not
0799          * FF..FF.
0800          * This is a workaround to skip performing correction in case
0801          * data is FF..FF
0802          *
0803          * Logic:
0804          * For every page, each bit written as 0 is counted until these
0805          * number of bits are greater than 8 (the maximum correction
0806          * capability of FSMC for each 512 + 13 bytes)
0807          */
0808 
0809         int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
0810         int bits_data = count_written_bits(dat, chip->ecc.size, 8);
0811 
0812         if ((bits_ecc + bits_data) <= 8) {
0813             if (bits_data)
0814                 memset(dat, 0xff, chip->ecc.size);
0815             return bits_data;
0816         }
0817 
0818         return -EBADMSG;
0819     }
0820 
0821     /*
0822      * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
0823      * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
0824      *
0825      * calc_ecc is a 104 bit information containing maximum of 8 error
0826      * offset information of 13 bits each. calc_ecc is copied into a
0827      * u64 array and error offset indexes are populated in err_idx
0828      * array
0829      */
0830     ecc1 = readl_relaxed(host->regs_va + ECC1);
0831     ecc2 = readl_relaxed(host->regs_va + ECC2);
0832     ecc3 = readl_relaxed(host->regs_va + ECC3);
0833     ecc4 = readl_relaxed(host->regs_va + STS);
0834 
0835     err_idx[0] = (ecc1 >> 0) & 0x1FFF;
0836     err_idx[1] = (ecc1 >> 13) & 0x1FFF;
0837     err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
0838     err_idx[3] = (ecc2 >> 7) & 0x1FFF;
0839     err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
0840     err_idx[5] = (ecc3 >> 1) & 0x1FFF;
0841     err_idx[6] = (ecc3 >> 14) & 0x1FFF;
0842     err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
0843 
0844     i = 0;
0845     while (num_err--) {
0846         err_idx[i] ^= 3;
0847 
0848         if (err_idx[i] < chip->ecc.size * 8) {
0849             int err = err_idx[i];
0850 
0851             dat[err >> 3] ^= BIT(err & 7);
0852             i++;
0853         }
0854     }
0855     return i;
0856 }
0857 
0858 static bool filter(struct dma_chan *chan, void *slave)
0859 {
0860     chan->private = slave;
0861     return true;
0862 }
0863 
0864 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
0865                      struct fsmc_nand_data *host,
0866                      struct nand_chip *nand)
0867 {
0868     struct device_node *np = pdev->dev.of_node;
0869     u32 val;
0870     int ret;
0871 
0872     nand->options = 0;
0873 
0874     if (!of_property_read_u32(np, "bank-width", &val)) {
0875         if (val == 2) {
0876             nand->options |= NAND_BUSWIDTH_16;
0877         } else if (val != 1) {
0878             dev_err(&pdev->dev, "invalid bank-width %u\n", val);
0879             return -EINVAL;
0880         }
0881     }
0882 
0883     if (of_get_property(np, "nand-skip-bbtscan", NULL))
0884         nand->options |= NAND_SKIP_BBTSCAN;
0885 
0886     host->dev_timings = devm_kzalloc(&pdev->dev,
0887                      sizeof(*host->dev_timings),
0888                      GFP_KERNEL);
0889     if (!host->dev_timings)
0890         return -ENOMEM;
0891 
0892     ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
0893                     sizeof(*host->dev_timings));
0894     if (ret)
0895         host->dev_timings = NULL;
0896 
0897     /* Set default NAND bank to 0 */
0898     host->bank = 0;
0899     if (!of_property_read_u32(np, "bank", &val)) {
0900         if (val > 3) {
0901             dev_err(&pdev->dev, "invalid bank %u\n", val);
0902             return -EINVAL;
0903         }
0904         host->bank = val;
0905     }
0906     return 0;
0907 }
0908 
0909 static int fsmc_nand_attach_chip(struct nand_chip *nand)
0910 {
0911     struct mtd_info *mtd = nand_to_mtd(nand);
0912     struct fsmc_nand_data *host = nand_to_fsmc(nand);
0913 
0914     if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
0915         nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
0916 
0917     if (!nand->ecc.size)
0918         nand->ecc.size = 512;
0919 
0920     if (AMBA_REV_BITS(host->pid) >= 8) {
0921         nand->ecc.read_page = fsmc_read_page_hwecc;
0922         nand->ecc.calculate = fsmc_read_hwecc_ecc4;
0923         nand->ecc.correct = fsmc_bch8_correct_data;
0924         nand->ecc.bytes = 13;
0925         nand->ecc.strength = 8;
0926     }
0927 
0928     if (AMBA_REV_BITS(host->pid) >= 8) {
0929         switch (mtd->oobsize) {
0930         case 16:
0931         case 64:
0932         case 128:
0933         case 224:
0934         case 256:
0935             break;
0936         default:
0937             dev_warn(host->dev,
0938                  "No oob scheme defined for oobsize %d\n",
0939                  mtd->oobsize);
0940             return -EINVAL;
0941         }
0942 
0943         mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
0944 
0945         return 0;
0946     }
0947 
0948     switch (nand->ecc.engine_type) {
0949     case NAND_ECC_ENGINE_TYPE_ON_HOST:
0950         dev_info(host->dev, "Using 1-bit HW ECC scheme\n");
0951         nand->ecc.calculate = fsmc_read_hwecc_ecc1;
0952         nand->ecc.correct = fsmc_correct_ecc1;
0953         nand->ecc.hwctl = fsmc_enable_hwecc;
0954         nand->ecc.bytes = 3;
0955         nand->ecc.strength = 1;
0956         nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
0957         break;
0958 
0959     case NAND_ECC_ENGINE_TYPE_SOFT:
0960         if (nand->ecc.algo == NAND_ECC_ALGO_BCH) {
0961             dev_info(host->dev,
0962                  "Using 4-bit SW BCH ECC scheme\n");
0963             break;
0964         }
0965         break;
0966 
0967     case NAND_ECC_ENGINE_TYPE_ON_DIE:
0968         break;
0969 
0970     default:
0971         dev_err(host->dev, "Unsupported ECC mode!\n");
0972         return -ENOTSUPP;
0973     }
0974 
0975     /*
0976      * Don't set layout for BCH4 SW ECC. This will be
0977      * generated later during BCH initialization.
0978      */
0979     if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
0980         switch (mtd->oobsize) {
0981         case 16:
0982         case 64:
0983         case 128:
0984             mtd_set_ooblayout(mtd,
0985                       &fsmc_ecc1_ooblayout_ops);
0986             break;
0987         default:
0988             dev_warn(host->dev,
0989                  "No oob scheme defined for oobsize %d\n",
0990                  mtd->oobsize);
0991             return -EINVAL;
0992         }
0993     }
0994 
0995     return 0;
0996 }
0997 
0998 static const struct nand_controller_ops fsmc_nand_controller_ops = {
0999     .attach_chip = fsmc_nand_attach_chip,
1000     .exec_op = fsmc_exec_op,
1001     .setup_interface = fsmc_setup_interface,
1002 };
1003 
1004 /**
1005  * fsmc_nand_disable() - Disables the NAND bank
1006  * @host: The instance to disable
1007  */
1008 static void fsmc_nand_disable(struct fsmc_nand_data *host)
1009 {
1010     u32 val;
1011 
1012     val = readl(host->regs_va + FSMC_PC);
1013     val &= ~FSMC_ENABLE;
1014     writel(val, host->regs_va + FSMC_PC);
1015 }
1016 
1017 /*
1018  * fsmc_nand_probe - Probe function
1019  * @pdev:       platform device structure
1020  */
1021 static int __init fsmc_nand_probe(struct platform_device *pdev)
1022 {
1023     struct fsmc_nand_data *host;
1024     struct mtd_info *mtd;
1025     struct nand_chip *nand;
1026     struct resource *res;
1027     void __iomem *base;
1028     dma_cap_mask_t mask;
1029     int ret = 0;
1030     u32 pid;
1031     int i;
1032 
1033     /* Allocate memory for the device structure (and zero it) */
1034     host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
1035     if (!host)
1036         return -ENOMEM;
1037 
1038     nand = &host->nand;
1039 
1040     ret = fsmc_nand_probe_config_dt(pdev, host, nand);
1041     if (ret)
1042         return ret;
1043 
1044     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
1045     host->data_va = devm_ioremap_resource(&pdev->dev, res);
1046     if (IS_ERR(host->data_va))
1047         return PTR_ERR(host->data_va);
1048 
1049     host->data_pa = (dma_addr_t)res->start;
1050 
1051     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
1052     host->addr_va = devm_ioremap_resource(&pdev->dev, res);
1053     if (IS_ERR(host->addr_va))
1054         return PTR_ERR(host->addr_va);
1055 
1056     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
1057     host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
1058     if (IS_ERR(host->cmd_va))
1059         return PTR_ERR(host->cmd_va);
1060 
1061     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
1062     base = devm_ioremap_resource(&pdev->dev, res);
1063     if (IS_ERR(base))
1064         return PTR_ERR(base);
1065 
1066     host->regs_va = base + FSMC_NOR_REG_SIZE +
1067         (host->bank * FSMC_NAND_BANK_SZ);
1068 
1069     host->clk = devm_clk_get(&pdev->dev, NULL);
1070     if (IS_ERR(host->clk)) {
1071         dev_err(&pdev->dev, "failed to fetch block clock\n");
1072         return PTR_ERR(host->clk);
1073     }
1074 
1075     ret = clk_prepare_enable(host->clk);
1076     if (ret)
1077         return ret;
1078 
1079     /*
1080      * This device ID is actually a common AMBA ID as used on the
1081      * AMBA PrimeCell bus. However it is not a PrimeCell.
1082      */
1083     for (pid = 0, i = 0; i < 4; i++)
1084         pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) &
1085             255) << (i * 8);
1086 
1087     host->pid = pid;
1088 
1089     dev_info(&pdev->dev,
1090          "FSMC device partno %03x, manufacturer %02x, revision %02x, config %02x\n",
1091          AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
1092          AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
1093 
1094     host->dev = &pdev->dev;
1095 
1096     if (host->mode == USE_DMA_ACCESS)
1097         init_completion(&host->dma_access_complete);
1098 
1099     /* Link all private pointers */
1100     mtd = nand_to_mtd(&host->nand);
1101     nand_set_flash_node(nand, pdev->dev.of_node);
1102 
1103     mtd->dev.parent = &pdev->dev;
1104 
1105     nand->badblockbits = 7;
1106 
1107     if (host->mode == USE_DMA_ACCESS) {
1108         dma_cap_zero(mask);
1109         dma_cap_set(DMA_MEMCPY, mask);
1110         host->read_dma_chan = dma_request_channel(mask, filter, NULL);
1111         if (!host->read_dma_chan) {
1112             dev_err(&pdev->dev, "Unable to get read dma channel\n");
1113             ret = -ENODEV;
1114             goto disable_clk;
1115         }
1116         host->write_dma_chan = dma_request_channel(mask, filter, NULL);
1117         if (!host->write_dma_chan) {
1118             dev_err(&pdev->dev, "Unable to get write dma channel\n");
1119             ret = -ENODEV;
1120             goto release_dma_read_chan;
1121         }
1122     }
1123 
1124     if (host->dev_timings) {
1125         fsmc_nand_setup(host, host->dev_timings);
1126         nand->options |= NAND_KEEP_TIMINGS;
1127     }
1128 
1129     nand_controller_init(&host->base);
1130     host->base.ops = &fsmc_nand_controller_ops;
1131     nand->controller = &host->base;
1132 
1133     /*
1134      * Scan to find existence of the device
1135      */
1136     ret = nand_scan(nand, 1);
1137     if (ret)
1138         goto release_dma_write_chan;
1139 
1140     mtd->name = "nand";
1141     ret = mtd_device_register(mtd, NULL, 0);
1142     if (ret)
1143         goto cleanup_nand;
1144 
1145     platform_set_drvdata(pdev, host);
1146     dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1147 
1148     return 0;
1149 
1150 cleanup_nand:
1151     nand_cleanup(nand);
1152 release_dma_write_chan:
1153     if (host->mode == USE_DMA_ACCESS)
1154         dma_release_channel(host->write_dma_chan);
1155 release_dma_read_chan:
1156     if (host->mode == USE_DMA_ACCESS)
1157         dma_release_channel(host->read_dma_chan);
1158 disable_clk:
1159     fsmc_nand_disable(host);
1160     clk_disable_unprepare(host->clk);
1161 
1162     return ret;
1163 }
1164 
1165 /*
1166  * Clean up routine
1167  */
1168 static int fsmc_nand_remove(struct platform_device *pdev)
1169 {
1170     struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1171 
1172     if (host) {
1173         struct nand_chip *chip = &host->nand;
1174         int ret;
1175 
1176         ret = mtd_device_unregister(nand_to_mtd(chip));
1177         WARN_ON(ret);
1178         nand_cleanup(chip);
1179         fsmc_nand_disable(host);
1180 
1181         if (host->mode == USE_DMA_ACCESS) {
1182             dma_release_channel(host->write_dma_chan);
1183             dma_release_channel(host->read_dma_chan);
1184         }
1185         clk_disable_unprepare(host->clk);
1186     }
1187 
1188     return 0;
1189 }
1190 
1191 #ifdef CONFIG_PM_SLEEP
1192 static int fsmc_nand_suspend(struct device *dev)
1193 {
1194     struct fsmc_nand_data *host = dev_get_drvdata(dev);
1195 
1196     if (host)
1197         clk_disable_unprepare(host->clk);
1198 
1199     return 0;
1200 }
1201 
1202 static int fsmc_nand_resume(struct device *dev)
1203 {
1204     struct fsmc_nand_data *host = dev_get_drvdata(dev);
1205 
1206     if (host) {
1207         clk_prepare_enable(host->clk);
1208         if (host->dev_timings)
1209             fsmc_nand_setup(host, host->dev_timings);
1210         nand_reset(&host->nand, 0);
1211     }
1212 
1213     return 0;
1214 }
1215 #endif
1216 
1217 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1218 
1219 static const struct of_device_id fsmc_nand_id_table[] = {
1220     { .compatible = "st,spear600-fsmc-nand" },
1221     { .compatible = "stericsson,fsmc-nand" },
1222     {}
1223 };
1224 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1225 
1226 static struct platform_driver fsmc_nand_driver = {
1227     .remove = fsmc_nand_remove,
1228     .driver = {
1229         .name = "fsmc-nand",
1230         .of_match_table = fsmc_nand_id_table,
1231         .pm = &fsmc_nand_pm_ops,
1232     },
1233 };
1234 
1235 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1236 
1237 MODULE_LICENSE("GPL v2");
1238 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1239 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
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