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0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/delay.h>
0013 #include <linux/mtd/rawnand.h>
0014 #include <linux/mtd/partitions.h>
0015 #include <linux/mtd/mtd.h>
0016 #include <linux/of_platform.h>
0017 #include <linux/io.h>
0018 #include <linux/slab.h>
0019 #include <asm/fsl_lbc.h>
0020
0021 struct fsl_upm_nand {
0022 struct nand_controller base;
0023 struct device *dev;
0024 struct nand_chip chip;
0025 struct fsl_upm upm;
0026 uint8_t upm_addr_offset;
0027 uint8_t upm_cmd_offset;
0028 void __iomem *io_base;
0029 struct gpio_desc *rnb_gpio[NAND_MAX_CHIPS];
0030 uint32_t mchip_offsets[NAND_MAX_CHIPS];
0031 uint32_t mchip_count;
0032 uint32_t mchip_number;
0033 };
0034
0035 static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo)
0036 {
0037 return container_of(mtd_to_nand(mtdinfo), struct fsl_upm_nand,
0038 chip);
0039 }
0040
0041 static int fun_chip_init(struct fsl_upm_nand *fun,
0042 const struct device_node *upm_np,
0043 const struct resource *io_res)
0044 {
0045 struct mtd_info *mtd = nand_to_mtd(&fun->chip);
0046 int ret;
0047 struct device_node *flash_np;
0048
0049 fun->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
0050 fun->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
0051 fun->chip.controller = &fun->base;
0052 mtd->dev.parent = fun->dev;
0053
0054 flash_np = of_get_next_child(upm_np, NULL);
0055 if (!flash_np)
0056 return -ENODEV;
0057
0058 nand_set_flash_node(&fun->chip, flash_np);
0059 mtd->name = devm_kasprintf(fun->dev, GFP_KERNEL, "0x%llx.%pOFn",
0060 (u64)io_res->start,
0061 flash_np);
0062 if (!mtd->name) {
0063 ret = -ENOMEM;
0064 goto err;
0065 }
0066
0067 ret = nand_scan(&fun->chip, fun->mchip_count);
0068 if (ret)
0069 goto err;
0070
0071 ret = mtd_device_register(mtd, NULL, 0);
0072 err:
0073 of_node_put(flash_np);
0074 return ret;
0075 }
0076
0077 static int func_exec_instr(struct nand_chip *chip,
0078 const struct nand_op_instr *instr)
0079 {
0080 struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
0081 u32 mar, reg_offs = fun->mchip_offsets[fun->mchip_number];
0082 unsigned int i;
0083 const u8 *out;
0084 u8 *in;
0085
0086 switch (instr->type) {
0087 case NAND_OP_CMD_INSTR:
0088 fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
0089 mar = (instr->ctx.cmd.opcode << (32 - fun->upm.width)) |
0090 reg_offs;
0091 fsl_upm_run_pattern(&fun->upm, fun->io_base + reg_offs, mar);
0092 fsl_upm_end_pattern(&fun->upm);
0093 return 0;
0094
0095 case NAND_OP_ADDR_INSTR:
0096 fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
0097 for (i = 0; i < instr->ctx.addr.naddrs; i++) {
0098 mar = (instr->ctx.addr.addrs[i] << (32 - fun->upm.width)) |
0099 reg_offs;
0100 fsl_upm_run_pattern(&fun->upm, fun->io_base + reg_offs, mar);
0101 }
0102 fsl_upm_end_pattern(&fun->upm);
0103 return 0;
0104
0105 case NAND_OP_DATA_IN_INSTR:
0106 in = instr->ctx.data.buf.in;
0107 for (i = 0; i < instr->ctx.data.len; i++)
0108 in[i] = in_8(fun->io_base + reg_offs);
0109 return 0;
0110
0111 case NAND_OP_DATA_OUT_INSTR:
0112 out = instr->ctx.data.buf.out;
0113 for (i = 0; i < instr->ctx.data.len; i++)
0114 out_8(fun->io_base + reg_offs, out[i]);
0115 return 0;
0116
0117 case NAND_OP_WAITRDY_INSTR:
0118 if (!fun->rnb_gpio[fun->mchip_number])
0119 return nand_soft_waitrdy(chip, instr->ctx.waitrdy.timeout_ms);
0120
0121 return nand_gpio_waitrdy(chip, fun->rnb_gpio[fun->mchip_number],
0122 instr->ctx.waitrdy.timeout_ms);
0123
0124 default:
0125 return -EINVAL;
0126 }
0127
0128 return 0;
0129 }
0130
0131 static int fun_exec_op(struct nand_chip *chip, const struct nand_operation *op,
0132 bool check_only)
0133 {
0134 struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
0135 unsigned int i;
0136 int ret;
0137
0138 if (op->cs > NAND_MAX_CHIPS)
0139 return -EINVAL;
0140
0141 if (check_only)
0142 return 0;
0143
0144 fun->mchip_number = op->cs;
0145
0146 for (i = 0; i < op->ninstrs; i++) {
0147 ret = func_exec_instr(chip, &op->instrs[i]);
0148 if (ret)
0149 return ret;
0150
0151 if (op->instrs[i].delay_ns)
0152 ndelay(op->instrs[i].delay_ns);
0153 }
0154
0155 return 0;
0156 }
0157
0158 static const struct nand_controller_ops fun_ops = {
0159 .exec_op = fun_exec_op,
0160 };
0161
0162 static int fun_probe(struct platform_device *ofdev)
0163 {
0164 struct fsl_upm_nand *fun;
0165 struct resource *io_res;
0166 const __be32 *prop;
0167 int ret;
0168 int size;
0169 int i;
0170
0171 fun = devm_kzalloc(&ofdev->dev, sizeof(*fun), GFP_KERNEL);
0172 if (!fun)
0173 return -ENOMEM;
0174
0175 io_res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
0176 fun->io_base = devm_ioremap_resource(&ofdev->dev, io_res);
0177 if (IS_ERR(fun->io_base))
0178 return PTR_ERR(fun->io_base);
0179
0180 ret = fsl_upm_find(io_res->start, &fun->upm);
0181 if (ret) {
0182 dev_err(&ofdev->dev, "can't find UPM\n");
0183 return ret;
0184 }
0185
0186 prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset",
0187 &size);
0188 if (!prop || size != sizeof(uint32_t)) {
0189 dev_err(&ofdev->dev, "can't get UPM address offset\n");
0190 return -EINVAL;
0191 }
0192 fun->upm_addr_offset = *prop;
0193
0194 prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size);
0195 if (!prop || size != sizeof(uint32_t)) {
0196 dev_err(&ofdev->dev, "can't get UPM command offset\n");
0197 return -EINVAL;
0198 }
0199 fun->upm_cmd_offset = *prop;
0200
0201 prop = of_get_property(ofdev->dev.of_node,
0202 "fsl,upm-addr-line-cs-offsets", &size);
0203 if (prop && (size / sizeof(uint32_t)) > 0) {
0204 fun->mchip_count = size / sizeof(uint32_t);
0205 if (fun->mchip_count >= NAND_MAX_CHIPS) {
0206 dev_err(&ofdev->dev, "too much multiple chips\n");
0207 return -EINVAL;
0208 }
0209 for (i = 0; i < fun->mchip_count; i++)
0210 fun->mchip_offsets[i] = be32_to_cpu(prop[i]);
0211 } else {
0212 fun->mchip_count = 1;
0213 }
0214
0215 for (i = 0; i < fun->mchip_count; i++) {
0216 fun->rnb_gpio[i] = devm_gpiod_get_index_optional(&ofdev->dev,
0217 NULL, i,
0218 GPIOD_IN);
0219 if (IS_ERR(fun->rnb_gpio[i])) {
0220 dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
0221 return PTR_ERR(fun->rnb_gpio[i]);
0222 }
0223 }
0224
0225 nand_controller_init(&fun->base);
0226 fun->base.ops = &fun_ops;
0227 fun->dev = &ofdev->dev;
0228
0229 ret = fun_chip_init(fun, ofdev->dev.of_node, io_res);
0230 if (ret)
0231 return ret;
0232
0233 dev_set_drvdata(&ofdev->dev, fun);
0234
0235 return 0;
0236 }
0237
0238 static int fun_remove(struct platform_device *ofdev)
0239 {
0240 struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
0241 struct nand_chip *chip = &fun->chip;
0242 struct mtd_info *mtd = nand_to_mtd(chip);
0243 int ret;
0244
0245 ret = mtd_device_unregister(mtd);
0246 WARN_ON(ret);
0247 nand_cleanup(chip);
0248
0249 return 0;
0250 }
0251
0252 static const struct of_device_id of_fun_match[] = {
0253 { .compatible = "fsl,upm-nand" },
0254 {},
0255 };
0256 MODULE_DEVICE_TABLE(of, of_fun_match);
0257
0258 static struct platform_driver of_fun_driver = {
0259 .driver = {
0260 .name = "fsl,upm-nand",
0261 .of_match_table = of_fun_match,
0262 },
0263 .probe = fun_probe,
0264 .remove = fun_remove,
0265 };
0266
0267 module_platform_driver(of_fun_driver);
0268
0269 MODULE_LICENSE("GPL");
0270 MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
0271 MODULE_DESCRIPTION("Driver for NAND chips working through Freescale "
0272 "LocalBus User-Programmable Machine");
