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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Freescale Integrated Flash Controller NAND driver
0004  *
0005  * Copyright 2011-2012 Freescale Semiconductor, Inc
0006  *
0007  * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/types.h>
0012 #include <linux/kernel.h>
0013 #include <linux/of_address.h>
0014 #include <linux/slab.h>
0015 #include <linux/mtd/mtd.h>
0016 #include <linux/mtd/rawnand.h>
0017 #include <linux/mtd/partitions.h>
0018 #include <linux/fsl_ifc.h>
0019 #include <linux/iopoll.h>
0020 
0021 #define ERR_BYTE        0xFF /* Value returned for read
0022                     bytes when read failed  */
0023 #define IFC_TIMEOUT_MSECS   500  /* Maximum number of mSecs to wait
0024                     for IFC NAND Machine    */
0025 
0026 struct fsl_ifc_ctrl;
0027 
0028 /* mtd information per set */
0029 struct fsl_ifc_mtd {
0030     struct nand_chip chip;
0031     struct fsl_ifc_ctrl *ctrl;
0032 
0033     struct device *dev;
0034     int bank;       /* Chip select bank number      */
0035     unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
0036     u8 __iomem *vbase;      /* Chip select base virtual address */
0037 };
0038 
0039 /* overview of the fsl ifc controller */
0040 struct fsl_ifc_nand_ctrl {
0041     struct nand_controller controller;
0042     struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
0043 
0044     void __iomem *addr; /* Address of assigned IFC buffer   */
0045     unsigned int page;  /* Last page written to / read from */
0046     unsigned int read_bytes;/* Number of bytes read during command  */
0047     unsigned int column;    /* Saved column from SEQIN      */
0048     unsigned int index; /* Pointer to next byte to 'read'   */
0049     unsigned int oob;   /* Non zero if operating on OOB data    */
0050     unsigned int eccread;   /* Non zero for a full-page ECC read    */
0051     unsigned int counter;   /* counter for the initializations  */
0052     unsigned int max_bitflips;  /* Saved during READ0 cmd       */
0053 };
0054 
0055 static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
0056 
0057 /*
0058  * Generic flash bbt descriptors
0059  */
0060 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
0061 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
0062 
0063 static struct nand_bbt_descr bbt_main_descr = {
0064     .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
0065            NAND_BBT_2BIT | NAND_BBT_VERSION,
0066     .offs = 2, /* 0 on 8-bit small page */
0067     .len = 4,
0068     .veroffs = 6,
0069     .maxblocks = 4,
0070     .pattern = bbt_pattern,
0071 };
0072 
0073 static struct nand_bbt_descr bbt_mirror_descr = {
0074     .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
0075            NAND_BBT_2BIT | NAND_BBT_VERSION,
0076     .offs = 2, /* 0 on 8-bit small page */
0077     .len = 4,
0078     .veroffs = 6,
0079     .maxblocks = 4,
0080     .pattern = mirror_pattern,
0081 };
0082 
0083 static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section,
0084                  struct mtd_oob_region *oobregion)
0085 {
0086     struct nand_chip *chip = mtd_to_nand(mtd);
0087 
0088     if (section)
0089         return -ERANGE;
0090 
0091     oobregion->offset = 8;
0092     oobregion->length = chip->ecc.total;
0093 
0094     return 0;
0095 }
0096 
0097 static int fsl_ifc_ooblayout_free(struct mtd_info *mtd, int section,
0098                   struct mtd_oob_region *oobregion)
0099 {
0100     struct nand_chip *chip = mtd_to_nand(mtd);
0101 
0102     if (section > 1)
0103         return -ERANGE;
0104 
0105     if (mtd->writesize == 512 &&
0106         !(chip->options & NAND_BUSWIDTH_16)) {
0107         if (!section) {
0108             oobregion->offset = 0;
0109             oobregion->length = 5;
0110         } else {
0111             oobregion->offset = 6;
0112             oobregion->length = 2;
0113         }
0114 
0115         return 0;
0116     }
0117 
0118     if (!section) {
0119         oobregion->offset = 2;
0120         oobregion->length = 6;
0121     } else {
0122         oobregion->offset = chip->ecc.total + 8;
0123         oobregion->length = mtd->oobsize - oobregion->offset;
0124     }
0125 
0126     return 0;
0127 }
0128 
0129 static const struct mtd_ooblayout_ops fsl_ifc_ooblayout_ops = {
0130     .ecc = fsl_ifc_ooblayout_ecc,
0131     .free = fsl_ifc_ooblayout_free,
0132 };
0133 
0134 /*
0135  * Set up the IFC hardware block and page address fields, and the ifc nand
0136  * structure addr field to point to the correct IFC buffer in memory
0137  */
0138 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
0139 {
0140     struct nand_chip *chip = mtd_to_nand(mtd);
0141     struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
0142     struct fsl_ifc_ctrl *ctrl = priv->ctrl;
0143     struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
0144     int buf_num;
0145 
0146     ifc_nand_ctrl->page = page_addr;
0147     /* Program ROW0/COL0 */
0148     ifc_out32(page_addr, &ifc->ifc_nand.row0);
0149     ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
0150 
0151     buf_num = page_addr & priv->bufnum_mask;
0152 
0153     ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
0154     ifc_nand_ctrl->index = column;
0155 
0156     /* for OOB data point to the second half of the buffer */
0157     if (oob)
0158         ifc_nand_ctrl->index += mtd->writesize;
0159 }
0160 
0161 /* returns nonzero if entire page is blank */
0162 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
0163               u32 eccstat, unsigned int bufnum)
0164 {
0165     return  (eccstat >> ((3 - bufnum % 4) * 8)) & 15;
0166 }
0167 
0168 /*
0169  * execute IFC NAND command and wait for it to complete
0170  */
0171 static void fsl_ifc_run_command(struct mtd_info *mtd)
0172 {
0173     struct nand_chip *chip = mtd_to_nand(mtd);
0174     struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
0175     struct fsl_ifc_ctrl *ctrl = priv->ctrl;
0176     struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
0177     struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
0178     u32 eccstat;
0179     int i;
0180 
0181     /* set the chip select for NAND Transaction */
0182     ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT,
0183           &ifc->ifc_nand.nand_csel);
0184 
0185     dev_vdbg(priv->dev,
0186             "%s: fir0=%08x fcr0=%08x\n",
0187             __func__,
0188             ifc_in32(&ifc->ifc_nand.nand_fir0),
0189             ifc_in32(&ifc->ifc_nand.nand_fcr0));
0190 
0191     ctrl->nand_stat = 0;
0192 
0193     /* start read/write seq */
0194     ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
0195 
0196     /* wait for command complete flag or timeout */
0197     wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
0198                msecs_to_jiffies(IFC_TIMEOUT_MSECS));
0199 
0200     /* ctrl->nand_stat will be updated from IRQ context */
0201     if (!ctrl->nand_stat)
0202         dev_err(priv->dev, "Controller is not responding\n");
0203     if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
0204         dev_err(priv->dev, "NAND Flash Timeout Error\n");
0205     if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
0206         dev_err(priv->dev, "NAND Flash Write Protect Error\n");
0207 
0208     nctrl->max_bitflips = 0;
0209 
0210     if (nctrl->eccread) {
0211         int errors;
0212         int bufnum = nctrl->page & priv->bufnum_mask;
0213         int sector_start = bufnum * chip->ecc.steps;
0214         int sector_end = sector_start + chip->ecc.steps - 1;
0215         __be32 __iomem *eccstat_regs;
0216 
0217         eccstat_regs = ifc->ifc_nand.nand_eccstat;
0218         eccstat = ifc_in32(&eccstat_regs[sector_start / 4]);
0219 
0220         for (i = sector_start; i <= sector_end; i++) {
0221             if (i != sector_start && !(i % 4))
0222                 eccstat = ifc_in32(&eccstat_regs[i / 4]);
0223 
0224             errors = check_read_ecc(mtd, ctrl, eccstat, i);
0225 
0226             if (errors == 15) {
0227                 /*
0228                  * Uncorrectable error.
0229                  * We'll check for blank pages later.
0230                  *
0231                  * We disable ECCER reporting due to...
0232                  * erratum IFC-A002770 -- so report it now if we
0233                  * see an uncorrectable error in ECCSTAT.
0234                  */
0235                 ctrl->nand_stat |= IFC_NAND_EVTER_STAT_ECCER;
0236                 continue;
0237             }
0238 
0239             mtd->ecc_stats.corrected += errors;
0240             nctrl->max_bitflips = max_t(unsigned int,
0241                             nctrl->max_bitflips,
0242                             errors);
0243         }
0244 
0245         nctrl->eccread = 0;
0246     }
0247 }
0248 
0249 static void fsl_ifc_do_read(struct nand_chip *chip,
0250                 int oob,
0251                 struct mtd_info *mtd)
0252 {
0253     struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
0254     struct fsl_ifc_ctrl *ctrl = priv->ctrl;
0255     struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
0256 
0257     /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
0258     if (mtd->writesize > 512) {
0259         ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
0260               (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
0261               (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
0262               (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
0263               (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
0264               &ifc->ifc_nand.nand_fir0);
0265         ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
0266 
0267         ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
0268               (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
0269               &ifc->ifc_nand.nand_fcr0);
0270     } else {
0271         ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
0272               (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
0273               (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
0274               (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
0275               &ifc->ifc_nand.nand_fir0);
0276         ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
0277 
0278         if (oob)
0279             ifc_out32(NAND_CMD_READOOB <<
0280                   IFC_NAND_FCR0_CMD0_SHIFT,
0281                   &ifc->ifc_nand.nand_fcr0);
0282         else
0283             ifc_out32(NAND_CMD_READ0 <<
0284                   IFC_NAND_FCR0_CMD0_SHIFT,
0285                   &ifc->ifc_nand.nand_fcr0);
0286     }
0287 }
0288 
0289 /* cmdfunc send commands to the IFC NAND Machine */
0290 static void fsl_ifc_cmdfunc(struct nand_chip *chip, unsigned int command,
0291                 int column, int page_addr) {
0292     struct mtd_info *mtd = nand_to_mtd(chip);
0293     struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
0294     struct fsl_ifc_ctrl *ctrl = priv->ctrl;
0295     struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
0296 
0297     /* clear the read buffer */
0298     ifc_nand_ctrl->read_bytes = 0;
0299     if (command != NAND_CMD_PAGEPROG)
0300         ifc_nand_ctrl->index = 0;
0301 
0302     switch (command) {
0303     /* READ0 read the entire buffer to use hardware ECC. */
0304     case NAND_CMD_READ0:
0305         ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
0306         set_addr(mtd, 0, page_addr, 0);
0307 
0308         ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
0309         ifc_nand_ctrl->index += column;
0310 
0311         if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
0312             ifc_nand_ctrl->eccread = 1;
0313 
0314         fsl_ifc_do_read(chip, 0, mtd);
0315         fsl_ifc_run_command(mtd);
0316         return;
0317 
0318     /* READOOB reads only the OOB because no ECC is performed. */
0319     case NAND_CMD_READOOB:
0320         ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
0321         set_addr(mtd, column, page_addr, 1);
0322 
0323         ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
0324 
0325         fsl_ifc_do_read(chip, 1, mtd);
0326         fsl_ifc_run_command(mtd);
0327 
0328         return;
0329 
0330     case NAND_CMD_READID:
0331     case NAND_CMD_PARAM: {
0332         /*
0333          * For READID, read 8 bytes that are currently used.
0334          * For PARAM, read all 3 copies of 256-bytes pages.
0335          */
0336         int len = 8;
0337         int timing = IFC_FIR_OP_RB;
0338         if (command == NAND_CMD_PARAM) {
0339             timing = IFC_FIR_OP_RBCD;
0340             len = 256 * 3;
0341         }
0342 
0343         ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
0344               (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
0345               (timing << IFC_NAND_FIR0_OP2_SHIFT),
0346               &ifc->ifc_nand.nand_fir0);
0347         ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT,
0348               &ifc->ifc_nand.nand_fcr0);
0349         ifc_out32(column, &ifc->ifc_nand.row3);
0350 
0351         ifc_out32(len, &ifc->ifc_nand.nand_fbcr);
0352         ifc_nand_ctrl->read_bytes = len;
0353 
0354         set_addr(mtd, 0, 0, 0);
0355         fsl_ifc_run_command(mtd);
0356         return;
0357     }
0358 
0359     /* ERASE1 stores the block and page address */
0360     case NAND_CMD_ERASE1:
0361         set_addr(mtd, 0, page_addr, 0);
0362         return;
0363 
0364     /* ERASE2 uses the block and page address from ERASE1 */
0365     case NAND_CMD_ERASE2:
0366         ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
0367               (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
0368               (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
0369               &ifc->ifc_nand.nand_fir0);
0370 
0371         ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
0372               (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
0373               &ifc->ifc_nand.nand_fcr0);
0374 
0375         ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
0376         ifc_nand_ctrl->read_bytes = 0;
0377         fsl_ifc_run_command(mtd);
0378         return;
0379 
0380     /* SEQIN sets up the addr buffer and all registers except the length */
0381     case NAND_CMD_SEQIN: {
0382         u32 nand_fcr0;
0383         ifc_nand_ctrl->column = column;
0384         ifc_nand_ctrl->oob = 0;
0385 
0386         if (mtd->writesize > 512) {
0387             nand_fcr0 =
0388                 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
0389                 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
0390                 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
0391 
0392             ifc_out32(
0393                 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
0394                 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
0395                 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
0396                 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
0397                 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
0398                 &ifc->ifc_nand.nand_fir0);
0399             ifc_out32(
0400                 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
0401                 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) |
0402                 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
0403                 &ifc->ifc_nand.nand_fir1);
0404         } else {
0405             nand_fcr0 = ((NAND_CMD_PAGEPROG <<
0406                     IFC_NAND_FCR0_CMD1_SHIFT) |
0407                     (NAND_CMD_SEQIN <<
0408                     IFC_NAND_FCR0_CMD2_SHIFT) |
0409                     (NAND_CMD_STATUS <<
0410                     IFC_NAND_FCR0_CMD3_SHIFT));
0411 
0412             ifc_out32(
0413                 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
0414                 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
0415                 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
0416                 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
0417                 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
0418                 &ifc->ifc_nand.nand_fir0);
0419             ifc_out32(
0420                 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
0421                 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
0422                 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) |
0423                 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
0424                 &ifc->ifc_nand.nand_fir1);
0425 
0426             if (column >= mtd->writesize)
0427                 nand_fcr0 |=
0428                 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
0429             else
0430                 nand_fcr0 |=
0431                 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
0432         }
0433 
0434         if (column >= mtd->writesize) {
0435             /* OOB area --> READOOB */
0436             column -= mtd->writesize;
0437             ifc_nand_ctrl->oob = 1;
0438         }
0439         ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
0440         set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
0441         return;
0442     }
0443 
0444     /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
0445     case NAND_CMD_PAGEPROG: {
0446         if (ifc_nand_ctrl->oob) {
0447             ifc_out32(ifc_nand_ctrl->index -
0448                   ifc_nand_ctrl->column,
0449                   &ifc->ifc_nand.nand_fbcr);
0450         } else {
0451             ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
0452         }
0453 
0454         fsl_ifc_run_command(mtd);
0455         return;
0456     }
0457 
0458     case NAND_CMD_STATUS: {
0459         void __iomem *addr;
0460 
0461         ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
0462               (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
0463               &ifc->ifc_nand.nand_fir0);
0464         ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
0465               &ifc->ifc_nand.nand_fcr0);
0466         ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
0467         set_addr(mtd, 0, 0, 0);
0468         ifc_nand_ctrl->read_bytes = 1;
0469 
0470         fsl_ifc_run_command(mtd);
0471 
0472         /*
0473          * The chip always seems to report that it is
0474          * write-protected, even when it is not.
0475          */
0476         addr = ifc_nand_ctrl->addr;
0477         if (chip->options & NAND_BUSWIDTH_16)
0478             ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr);
0479         else
0480             ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr);
0481         return;
0482     }
0483 
0484     case NAND_CMD_RESET:
0485         ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
0486               &ifc->ifc_nand.nand_fir0);
0487         ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
0488               &ifc->ifc_nand.nand_fcr0);
0489         fsl_ifc_run_command(mtd);
0490         return;
0491 
0492     default:
0493         dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
0494                     __func__, command);
0495     }
0496 }
0497 
0498 static void fsl_ifc_select_chip(struct nand_chip *chip, int cs)
0499 {
0500     /* The hardware does not seem to support multiple
0501      * chips per bank.
0502      */
0503 }
0504 
0505 /*
0506  * Write buf to the IFC NAND Controller Data Buffer
0507  */
0508 static void fsl_ifc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
0509 {
0510     struct mtd_info *mtd = nand_to_mtd(chip);
0511     struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
0512     unsigned int bufsize = mtd->writesize + mtd->oobsize;
0513 
0514     if (len <= 0) {
0515         dev_err(priv->dev, "%s: len %d bytes", __func__, len);
0516         return;
0517     }
0518 
0519     if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
0520         dev_err(priv->dev,
0521             "%s: beyond end of buffer (%d requested, %u available)\n",
0522             __func__, len, bufsize - ifc_nand_ctrl->index);
0523         len = bufsize - ifc_nand_ctrl->index;
0524     }
0525 
0526     memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len);
0527     ifc_nand_ctrl->index += len;
0528 }
0529 
0530 /*
0531  * Read a byte from either the IFC hardware buffer
0532  * read function for 8-bit buswidth
0533  */
0534 static uint8_t fsl_ifc_read_byte(struct nand_chip *chip)
0535 {
0536     struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
0537     unsigned int offset;
0538 
0539     /*
0540      * If there are still bytes in the IFC buffer, then use the
0541      * next byte.
0542      */
0543     if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
0544         offset = ifc_nand_ctrl->index++;
0545         return ifc_in8(ifc_nand_ctrl->addr + offset);
0546     }
0547 
0548     dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
0549     return ERR_BYTE;
0550 }
0551 
0552 /*
0553  * Read two bytes from the IFC hardware buffer
0554  * read function for 16-bit buswith
0555  */
0556 static uint8_t fsl_ifc_read_byte16(struct nand_chip *chip)
0557 {
0558     struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
0559     uint16_t data;
0560 
0561     /*
0562      * If there are still bytes in the IFC buffer, then use the
0563      * next byte.
0564      */
0565     if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
0566         data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
0567         ifc_nand_ctrl->index += 2;
0568         return (uint8_t) data;
0569     }
0570 
0571     dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
0572     return ERR_BYTE;
0573 }
0574 
0575 /*
0576  * Read from the IFC Controller Data Buffer
0577  */
0578 static void fsl_ifc_read_buf(struct nand_chip *chip, u8 *buf, int len)
0579 {
0580     struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
0581     int avail;
0582 
0583     if (len < 0) {
0584         dev_err(priv->dev, "%s: len %d bytes", __func__, len);
0585         return;
0586     }
0587 
0588     avail = min((unsigned int)len,
0589             ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
0590     memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail);
0591     ifc_nand_ctrl->index += avail;
0592 
0593     if (len > avail)
0594         dev_err(priv->dev,
0595             "%s: beyond end of buffer (%d requested, %d available)\n",
0596             __func__, len, avail);
0597 }
0598 
0599 /*
0600  * This function is called after Program and Erase Operations to
0601  * check for success or failure.
0602  */
0603 static int fsl_ifc_wait(struct nand_chip *chip)
0604 {
0605     struct mtd_info *mtd = nand_to_mtd(chip);
0606     struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
0607     struct fsl_ifc_ctrl *ctrl = priv->ctrl;
0608     struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
0609     u32 nand_fsr;
0610     int status;
0611 
0612     /* Use READ_STATUS command, but wait for the device to be ready */
0613     ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
0614           (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
0615           &ifc->ifc_nand.nand_fir0);
0616     ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
0617           &ifc->ifc_nand.nand_fcr0);
0618     ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
0619     set_addr(mtd, 0, 0, 0);
0620     ifc_nand_ctrl->read_bytes = 1;
0621 
0622     fsl_ifc_run_command(mtd);
0623 
0624     nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
0625     status = nand_fsr >> 24;
0626     /*
0627      * The chip always seems to report that it is
0628      * write-protected, even when it is not.
0629      */
0630     return status | NAND_STATUS_WP;
0631 }
0632 
0633 /*
0634  * The controller does not check for bitflips in erased pages,
0635  * therefore software must check instead.
0636  */
0637 static int check_erased_page(struct nand_chip *chip, u8 *buf)
0638 {
0639     struct mtd_info *mtd = nand_to_mtd(chip);
0640     u8 *ecc = chip->oob_poi;
0641     const int ecc_size = chip->ecc.bytes;
0642     const int pkt_size = chip->ecc.size;
0643     int i, res, bitflips = 0;
0644     struct mtd_oob_region oobregion = { };
0645 
0646     mtd_ooblayout_ecc(mtd, 0, &oobregion);
0647     ecc += oobregion.offset;
0648 
0649     for (i = 0; i < chip->ecc.steps; ++i) {
0650         res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
0651                           NULL, 0,
0652                           chip->ecc.strength);
0653         if (res < 0)
0654             mtd->ecc_stats.failed++;
0655         else
0656             mtd->ecc_stats.corrected += res;
0657 
0658         bitflips = max(res, bitflips);
0659         buf += pkt_size;
0660         ecc += ecc_size;
0661     }
0662 
0663     return bitflips;
0664 }
0665 
0666 static int fsl_ifc_read_page(struct nand_chip *chip, uint8_t *buf,
0667                  int oob_required, int page)
0668 {
0669     struct mtd_info *mtd = nand_to_mtd(chip);
0670     struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
0671     struct fsl_ifc_ctrl *ctrl = priv->ctrl;
0672     struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
0673 
0674     nand_read_page_op(chip, page, 0, buf, mtd->writesize);
0675     if (oob_required)
0676         fsl_ifc_read_buf(chip, chip->oob_poi, mtd->oobsize);
0677 
0678     if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER) {
0679         if (!oob_required)
0680             fsl_ifc_read_buf(chip, chip->oob_poi, mtd->oobsize);
0681 
0682         return check_erased_page(chip, buf);
0683     }
0684 
0685     if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
0686         mtd->ecc_stats.failed++;
0687 
0688     return nctrl->max_bitflips;
0689 }
0690 
0691 /* ECC will be calculated automatically, and errors will be detected in
0692  * waitfunc.
0693  */
0694 static int fsl_ifc_write_page(struct nand_chip *chip, const uint8_t *buf,
0695                   int oob_required, int page)
0696 {
0697     struct mtd_info *mtd = nand_to_mtd(chip);
0698 
0699     nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
0700     fsl_ifc_write_buf(chip, chip->oob_poi, mtd->oobsize);
0701 
0702     return nand_prog_page_end_op(chip);
0703 }
0704 
0705 static int fsl_ifc_attach_chip(struct nand_chip *chip)
0706 {
0707     struct mtd_info *mtd = nand_to_mtd(chip);
0708     struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
0709     struct fsl_ifc_ctrl *ctrl = priv->ctrl;
0710     struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
0711     u32 csor;
0712 
0713     csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
0714 
0715     /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
0716     if (csor & CSOR_NAND_ECC_DEC_EN) {
0717         chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
0718         mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
0719 
0720         /* Hardware generates ECC per 512 Bytes */
0721         chip->ecc.size = 512;
0722         if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
0723             chip->ecc.bytes = 8;
0724             chip->ecc.strength = 4;
0725         } else {
0726             chip->ecc.bytes = 16;
0727             chip->ecc.strength = 8;
0728         }
0729     } else {
0730         chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
0731         chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
0732     }
0733 
0734     dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
0735         nanddev_ntargets(&chip->base));
0736     dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
0737             nanddev_target_size(&chip->base));
0738     dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
0739                             chip->pagemask);
0740     dev_dbg(priv->dev, "%s: nand->legacy.chip_delay = %d\n", __func__,
0741         chip->legacy.chip_delay);
0742     dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
0743                             chip->badblockpos);
0744     dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
0745                             chip->chip_shift);
0746     dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
0747                             chip->page_shift);
0748     dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
0749                             chip->phys_erase_shift);
0750     dev_dbg(priv->dev, "%s: nand->ecc.engine_type = %d\n", __func__,
0751                             chip->ecc.engine_type);
0752     dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
0753                             chip->ecc.steps);
0754     dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
0755                             chip->ecc.bytes);
0756     dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
0757                             chip->ecc.total);
0758     dev_dbg(priv->dev, "%s: mtd->ooblayout = %p\n", __func__,
0759                             mtd->ooblayout);
0760     dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
0761     dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
0762     dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
0763                             mtd->erasesize);
0764     dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
0765                             mtd->writesize);
0766     dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
0767                             mtd->oobsize);
0768 
0769     return 0;
0770 }
0771 
0772 static const struct nand_controller_ops fsl_ifc_controller_ops = {
0773     .attach_chip = fsl_ifc_attach_chip,
0774 };
0775 
0776 static int fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
0777 {
0778     struct fsl_ifc_ctrl *ctrl = priv->ctrl;
0779     struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
0780     struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
0781     uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
0782     uint32_t cs = priv->bank;
0783 
0784     if (ctrl->version < FSL_IFC_VERSION_1_1_0)
0785         return 0;
0786 
0787     if (ctrl->version > FSL_IFC_VERSION_1_1_0) {
0788         u32 ncfgr, status;
0789         int ret;
0790 
0791         /* Trigger auto initialization */
0792         ncfgr = ifc_in32(&ifc_runtime->ifc_nand.ncfgr);
0793         ifc_out32(ncfgr | IFC_NAND_NCFGR_SRAM_INIT_EN, &ifc_runtime->ifc_nand.ncfgr);
0794 
0795         /* Wait until done */
0796         ret = readx_poll_timeout(ifc_in32, &ifc_runtime->ifc_nand.ncfgr,
0797                      status, !(status & IFC_NAND_NCFGR_SRAM_INIT_EN),
0798                      10, IFC_TIMEOUT_MSECS * 1000);
0799         if (ret)
0800             dev_err(priv->dev, "Failed to initialize SRAM!\n");
0801 
0802         return ret;
0803     }
0804 
0805     /* Save CSOR and CSOR_ext */
0806     csor = ifc_in32(&ifc_global->csor_cs[cs].csor);
0807     csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext);
0808 
0809     /* chage PageSize 8K and SpareSize 1K*/
0810     csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
0811     ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor);
0812     ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext);
0813 
0814     /* READID */
0815     ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
0816             (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
0817             (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
0818             &ifc_runtime->ifc_nand.nand_fir0);
0819     ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
0820             &ifc_runtime->ifc_nand.nand_fcr0);
0821     ifc_out32(0x0, &ifc_runtime->ifc_nand.row3);
0822 
0823     ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr);
0824 
0825     /* Program ROW0/COL0 */
0826     ifc_out32(0x0, &ifc_runtime->ifc_nand.row0);
0827     ifc_out32(0x0, &ifc_runtime->ifc_nand.col0);
0828 
0829     /* set the chip select for NAND Transaction */
0830     ifc_out32(cs << IFC_NAND_CSEL_SHIFT,
0831         &ifc_runtime->ifc_nand.nand_csel);
0832 
0833     /* start read seq */
0834     ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT,
0835         &ifc_runtime->ifc_nand.nandseq_strt);
0836 
0837     /* wait for command complete flag or timeout */
0838     wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
0839                msecs_to_jiffies(IFC_TIMEOUT_MSECS));
0840 
0841     if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) {
0842         pr_err("fsl-ifc: Failed to Initialise SRAM\n");
0843         return -ETIMEDOUT;
0844     }
0845 
0846     /* Restore CSOR and CSOR_ext */
0847     ifc_out32(csor, &ifc_global->csor_cs[cs].csor);
0848     ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext);
0849 
0850     return 0;
0851 }
0852 
0853 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
0854 {
0855     struct fsl_ifc_ctrl *ctrl = priv->ctrl;
0856     struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
0857     struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
0858     struct nand_chip *chip = &priv->chip;
0859     struct mtd_info *mtd = nand_to_mtd(&priv->chip);
0860     u32 csor;
0861     int ret;
0862 
0863     /* Fill in fsl_ifc_mtd structure */
0864     mtd->dev.parent = priv->dev;
0865     nand_set_flash_node(chip, priv->dev->of_node);
0866 
0867     /* fill in nand_chip structure */
0868     /* set up function call table */
0869     if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))
0870         & CSPR_PORT_SIZE_16)
0871         chip->legacy.read_byte = fsl_ifc_read_byte16;
0872     else
0873         chip->legacy.read_byte = fsl_ifc_read_byte;
0874 
0875     chip->legacy.write_buf = fsl_ifc_write_buf;
0876     chip->legacy.read_buf = fsl_ifc_read_buf;
0877     chip->legacy.select_chip = fsl_ifc_select_chip;
0878     chip->legacy.cmdfunc = fsl_ifc_cmdfunc;
0879     chip->legacy.waitfunc = fsl_ifc_wait;
0880     chip->legacy.set_features = nand_get_set_features_notsupp;
0881     chip->legacy.get_features = nand_get_set_features_notsupp;
0882 
0883     chip->bbt_td = &bbt_main_descr;
0884     chip->bbt_md = &bbt_mirror_descr;
0885 
0886     ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr);
0887 
0888     /* set up nand options */
0889     chip->bbt_options = NAND_BBT_USE_FLASH;
0890     chip->options = NAND_NO_SUBPAGE_WRITE;
0891 
0892     if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)
0893         & CSPR_PORT_SIZE_16) {
0894         chip->legacy.read_byte = fsl_ifc_read_byte16;
0895         chip->options |= NAND_BUSWIDTH_16;
0896     } else {
0897         chip->legacy.read_byte = fsl_ifc_read_byte;
0898     }
0899 
0900     chip->controller = &ifc_nand_ctrl->controller;
0901     nand_set_controller_data(chip, priv);
0902 
0903     chip->ecc.read_page = fsl_ifc_read_page;
0904     chip->ecc.write_page = fsl_ifc_write_page;
0905 
0906     csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
0907 
0908     switch (csor & CSOR_NAND_PGS_MASK) {
0909     case CSOR_NAND_PGS_512:
0910         if (!(chip->options & NAND_BUSWIDTH_16)) {
0911             /* Avoid conflict with bad block marker */
0912             bbt_main_descr.offs = 0;
0913             bbt_mirror_descr.offs = 0;
0914         }
0915 
0916         priv->bufnum_mask = 15;
0917         break;
0918 
0919     case CSOR_NAND_PGS_2K:
0920         priv->bufnum_mask = 3;
0921         break;
0922 
0923     case CSOR_NAND_PGS_4K:
0924         priv->bufnum_mask = 1;
0925         break;
0926 
0927     case CSOR_NAND_PGS_8K:
0928         priv->bufnum_mask = 0;
0929         break;
0930 
0931     default:
0932         dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
0933         return -ENODEV;
0934     }
0935 
0936     ret = fsl_ifc_sram_init(priv);
0937     if (ret)
0938         return ret;
0939 
0940     /*
0941      * As IFC version 2.0.0 has 16KB of internal SRAM as compared to older
0942      * versions which had 8KB. Hence bufnum mask needs to be updated.
0943      */
0944     if (ctrl->version >= FSL_IFC_VERSION_2_0_0)
0945         priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
0946 
0947     return 0;
0948 }
0949 
0950 static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
0951 {
0952     struct mtd_info *mtd = nand_to_mtd(&priv->chip);
0953 
0954     kfree(mtd->name);
0955 
0956     if (priv->vbase)
0957         iounmap(priv->vbase);
0958 
0959     ifc_nand_ctrl->chips[priv->bank] = NULL;
0960 
0961     return 0;
0962 }
0963 
0964 static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank,
0965               phys_addr_t addr)
0966 {
0967     u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr);
0968 
0969     if (!(cspr & CSPR_V))
0970         return 0;
0971     if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
0972         return 0;
0973 
0974     return (cspr & CSPR_BA) == convert_ifc_address(addr);
0975 }
0976 
0977 static DEFINE_MUTEX(fsl_ifc_nand_mutex);
0978 
0979 static int fsl_ifc_nand_probe(struct platform_device *dev)
0980 {
0981     struct fsl_ifc_runtime __iomem *ifc;
0982     struct fsl_ifc_mtd *priv;
0983     struct resource res;
0984     static const char *part_probe_types[]
0985         = { "cmdlinepart", "RedBoot", "ofpart", NULL };
0986     int ret;
0987     int bank;
0988     struct device_node *node = dev->dev.of_node;
0989     struct mtd_info *mtd;
0990 
0991     if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs)
0992         return -ENODEV;
0993     ifc = fsl_ifc_ctrl_dev->rregs;
0994 
0995     /* get, allocate and map the memory resource */
0996     ret = of_address_to_resource(node, 0, &res);
0997     if (ret) {
0998         dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
0999         return ret;
1000     }
1001 
1002     /* find which chip select it is connected to */
1003     for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
1004         if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start))
1005             break;
1006     }
1007 
1008     if (bank >= fsl_ifc_ctrl_dev->banks) {
1009         dev_err(&dev->dev, "%s: address did not match any chip selects\n",
1010             __func__);
1011         return -ENODEV;
1012     }
1013 
1014     priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1015     if (!priv)
1016         return -ENOMEM;
1017 
1018     mutex_lock(&fsl_ifc_nand_mutex);
1019     if (!fsl_ifc_ctrl_dev->nand) {
1020         ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
1021         if (!ifc_nand_ctrl) {
1022             mutex_unlock(&fsl_ifc_nand_mutex);
1023             return -ENOMEM;
1024         }
1025 
1026         ifc_nand_ctrl->read_bytes = 0;
1027         ifc_nand_ctrl->index = 0;
1028         ifc_nand_ctrl->addr = NULL;
1029         fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
1030 
1031         nand_controller_init(&ifc_nand_ctrl->controller);
1032     } else {
1033         ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
1034     }
1035     mutex_unlock(&fsl_ifc_nand_mutex);
1036 
1037     ifc_nand_ctrl->chips[bank] = priv;
1038     priv->bank = bank;
1039     priv->ctrl = fsl_ifc_ctrl_dev;
1040     priv->dev = &dev->dev;
1041 
1042     priv->vbase = ioremap(res.start, resource_size(&res));
1043     if (!priv->vbase) {
1044         dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
1045         ret = -ENOMEM;
1046         goto err;
1047     }
1048 
1049     dev_set_drvdata(priv->dev, priv);
1050 
1051     ifc_out32(IFC_NAND_EVTER_EN_OPC_EN |
1052           IFC_NAND_EVTER_EN_FTOER_EN |
1053           IFC_NAND_EVTER_EN_WPER_EN,
1054           &ifc->ifc_nand.nand_evter_en);
1055 
1056     /* enable NAND Machine Interrupts */
1057     ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN |
1058           IFC_NAND_EVTER_INTR_FTOERIR_EN |
1059           IFC_NAND_EVTER_INTR_WPERIR_EN,
1060           &ifc->ifc_nand.nand_evter_intr_en);
1061 
1062     mtd = nand_to_mtd(&priv->chip);
1063     mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
1064     if (!mtd->name) {
1065         ret = -ENOMEM;
1066         goto err;
1067     }
1068 
1069     ret = fsl_ifc_chip_init(priv);
1070     if (ret)
1071         goto err;
1072 
1073     priv->chip.controller->ops = &fsl_ifc_controller_ops;
1074     ret = nand_scan(&priv->chip, 1);
1075     if (ret)
1076         goto err;
1077 
1078     /* First look for RedBoot table or partitions on the command
1079      * line, these take precedence over device tree information */
1080     ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
1081     if (ret)
1082         goto cleanup_nand;
1083 
1084     dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1085          (unsigned long long)res.start, priv->bank);
1086 
1087     return 0;
1088 
1089 cleanup_nand:
1090     nand_cleanup(&priv->chip);
1091 err:
1092     fsl_ifc_chip_remove(priv);
1093 
1094     return ret;
1095 }
1096 
1097 static int fsl_ifc_nand_remove(struct platform_device *dev)
1098 {
1099     struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1100     struct nand_chip *chip = &priv->chip;
1101     int ret;
1102 
1103     ret = mtd_device_unregister(nand_to_mtd(chip));
1104     WARN_ON(ret);
1105     nand_cleanup(chip);
1106 
1107     fsl_ifc_chip_remove(priv);
1108 
1109     mutex_lock(&fsl_ifc_nand_mutex);
1110     ifc_nand_ctrl->counter--;
1111     if (!ifc_nand_ctrl->counter) {
1112         fsl_ifc_ctrl_dev->nand = NULL;
1113         kfree(ifc_nand_ctrl);
1114     }
1115     mutex_unlock(&fsl_ifc_nand_mutex);
1116 
1117     return 0;
1118 }
1119 
1120 static const struct of_device_id fsl_ifc_nand_match[] = {
1121     {
1122         .compatible = "fsl,ifc-nand",
1123     },
1124     {}
1125 };
1126 MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match);
1127 
1128 static struct platform_driver fsl_ifc_nand_driver = {
1129     .driver = {
1130         .name   = "fsl,ifc-nand",
1131         .of_match_table = fsl_ifc_nand_match,
1132     },
1133     .probe       = fsl_ifc_nand_probe,
1134     .remove      = fsl_ifc_nand_remove,
1135 };
1136 
1137 module_platform_driver(fsl_ifc_nand_driver);
1138 
1139 MODULE_LICENSE("GPL");
1140 MODULE_AUTHOR("Freescale");
1141 MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");
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