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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* Freescale Enhanced Local Bus Controller NAND driver
0003  *
0004  * Copyright © 2006-2007, 2010 Freescale Semiconductor
0005  *
0006  * Authors: Nick Spence <nick.spence@freescale.com>,
0007  *          Scott Wood <scottwood@freescale.com>
0008  *          Jack Lan <jack.lan@freescale.com>
0009  *          Roy Zang <tie-fei.zang@freescale.com>
0010  */
0011 
0012 #include <linux/module.h>
0013 #include <linux/types.h>
0014 #include <linux/kernel.h>
0015 #include <linux/string.h>
0016 #include <linux/ioport.h>
0017 #include <linux/of_address.h>
0018 #include <linux/of_platform.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/slab.h>
0021 #include <linux/interrupt.h>
0022 
0023 #include <linux/mtd/mtd.h>
0024 #include <linux/mtd/rawnand.h>
0025 #include <linux/mtd/partitions.h>
0026 
0027 #include <asm/io.h>
0028 #include <asm/fsl_lbc.h>
0029 
0030 #define MAX_BANKS 8
0031 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
0032 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
0033 
0034 /* mtd information per set */
0035 
0036 struct fsl_elbc_mtd {
0037     struct nand_chip chip;
0038     struct fsl_lbc_ctrl *ctrl;
0039 
0040     struct device *dev;
0041     int bank;               /* Chip select bank number           */
0042     u8 __iomem *vbase;      /* Chip select base virtual address  */
0043     int page_size;          /* NAND page size (0=512, 1=2048)    */
0044     unsigned int fmr;       /* FCM Flash Mode Register value     */
0045 };
0046 
0047 /* Freescale eLBC FCM controller information */
0048 
0049 struct fsl_elbc_fcm_ctrl {
0050     struct nand_controller controller;
0051     struct fsl_elbc_mtd *chips[MAX_BANKS];
0052 
0053     u8 __iomem *addr;        /* Address of assigned FCM buffer        */
0054     unsigned int page;       /* Last page written to / read from      */
0055     unsigned int read_bytes; /* Number of bytes read during command   */
0056     unsigned int column;     /* Saved column from SEQIN               */
0057     unsigned int index;      /* Pointer to next byte to 'read'        */
0058     unsigned int status;     /* status read from LTESR after last op  */
0059     unsigned int mdr;        /* UPM/FCM Data Register value           */
0060     unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
0061     unsigned int oob;        /* Non zero if operating on OOB data     */
0062     unsigned int counter;    /* counter for the initializations   */
0063     unsigned int max_bitflips;  /* Saved during READ0 cmd         */
0064 };
0065 
0066 /* These map to the positions used by the FCM hardware ECC generator */
0067 
0068 static int fsl_elbc_ooblayout_ecc(struct mtd_info *mtd, int section,
0069                   struct mtd_oob_region *oobregion)
0070 {
0071     struct nand_chip *chip = mtd_to_nand(mtd);
0072     struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
0073 
0074     if (section >= chip->ecc.steps)
0075         return -ERANGE;
0076 
0077     oobregion->offset = (16 * section) + 6;
0078     if (priv->fmr & FMR_ECCM)
0079         oobregion->offset += 2;
0080 
0081     oobregion->length = chip->ecc.bytes;
0082 
0083     return 0;
0084 }
0085 
0086 static int fsl_elbc_ooblayout_free(struct mtd_info *mtd, int section,
0087                    struct mtd_oob_region *oobregion)
0088 {
0089     struct nand_chip *chip = mtd_to_nand(mtd);
0090     struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
0091 
0092     if (section > chip->ecc.steps)
0093         return -ERANGE;
0094 
0095     if (!section) {
0096         oobregion->offset = 0;
0097         if (mtd->writesize > 512)
0098             oobregion->offset++;
0099         oobregion->length = (priv->fmr & FMR_ECCM) ? 7 : 5;
0100     } else {
0101         oobregion->offset = (16 * section) -
0102                     ((priv->fmr & FMR_ECCM) ? 5 : 7);
0103         if (section < chip->ecc.steps)
0104             oobregion->length = 13;
0105         else
0106             oobregion->length = mtd->oobsize - oobregion->offset;
0107     }
0108 
0109     return 0;
0110 }
0111 
0112 static const struct mtd_ooblayout_ops fsl_elbc_ooblayout_ops = {
0113     .ecc = fsl_elbc_ooblayout_ecc,
0114     .free = fsl_elbc_ooblayout_free,
0115 };
0116 
0117 /*
0118  * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
0119  * interfere with ECC positions, that's why we implement our own descriptors.
0120  * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
0121  */
0122 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
0123 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
0124 
0125 static struct nand_bbt_descr bbt_main_descr = {
0126     .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
0127            NAND_BBT_2BIT | NAND_BBT_VERSION,
0128     .offs = 11,
0129     .len = 4,
0130     .veroffs = 15,
0131     .maxblocks = 4,
0132     .pattern = bbt_pattern,
0133 };
0134 
0135 static struct nand_bbt_descr bbt_mirror_descr = {
0136     .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
0137            NAND_BBT_2BIT | NAND_BBT_VERSION,
0138     .offs = 11,
0139     .len = 4,
0140     .veroffs = 15,
0141     .maxblocks = 4,
0142     .pattern = mirror_pattern,
0143 };
0144 
0145 /*=================================*/
0146 
0147 /*
0148  * Set up the FCM hardware block and page address fields, and the fcm
0149  * structure addr field to point to the correct FCM buffer in memory
0150  */
0151 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
0152 {
0153     struct nand_chip *chip = mtd_to_nand(mtd);
0154     struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
0155     struct fsl_lbc_ctrl *ctrl = priv->ctrl;
0156     struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
0157     struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
0158     int buf_num;
0159 
0160     elbc_fcm_ctrl->page = page_addr;
0161 
0162     if (priv->page_size) {
0163         /*
0164          * large page size chip : FPAR[PI] save the lowest 6 bits,
0165          *                        FBAR[BLK] save the other bits.
0166          */
0167         out_be32(&lbc->fbar, page_addr >> 6);
0168         out_be32(&lbc->fpar,
0169                  ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
0170                  (oob ? FPAR_LP_MS : 0) | column);
0171         buf_num = (page_addr & 1) << 2;
0172     } else {
0173         /*
0174          * small page size chip : FPAR[PI] save the lowest 5 bits,
0175          *                        FBAR[BLK] save the other bits.
0176          */
0177         out_be32(&lbc->fbar, page_addr >> 5);
0178         out_be32(&lbc->fpar,
0179                  ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
0180                  (oob ? FPAR_SP_MS : 0) | column);
0181         buf_num = page_addr & 7;
0182     }
0183 
0184     elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024;
0185     elbc_fcm_ctrl->index = column;
0186 
0187     /* for OOB data point to the second half of the buffer */
0188     if (oob)
0189         elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512;
0190 
0191     dev_vdbg(priv->dev, "set_addr: bank=%d, "
0192                 "elbc_fcm_ctrl->addr=0x%p (0x%p), "
0193                         "index %x, pes %d ps %d\n",
0194          buf_num, elbc_fcm_ctrl->addr, priv->vbase,
0195          elbc_fcm_ctrl->index,
0196              chip->phys_erase_shift, chip->page_shift);
0197 }
0198 
0199 /*
0200  * execute FCM command and wait for it to complete
0201  */
0202 static int fsl_elbc_run_command(struct mtd_info *mtd)
0203 {
0204     struct nand_chip *chip = mtd_to_nand(mtd);
0205     struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
0206     struct fsl_lbc_ctrl *ctrl = priv->ctrl;
0207     struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
0208     struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
0209 
0210     /* Setup the FMR[OP] to execute without write protection */
0211     out_be32(&lbc->fmr, priv->fmr | 3);
0212     if (elbc_fcm_ctrl->use_mdr)
0213         out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);
0214 
0215     dev_vdbg(priv->dev,
0216              "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
0217              in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
0218     dev_vdbg(priv->dev,
0219              "fsl_elbc_run_command: fbar=%08x fpar=%08x "
0220              "fbcr=%08x bank=%d\n",
0221              in_be32(&lbc->fbar), in_be32(&lbc->fpar),
0222              in_be32(&lbc->fbcr), priv->bank);
0223 
0224     ctrl->irq_status = 0;
0225     /* execute special operation */
0226     out_be32(&lbc->lsor, priv->bank);
0227 
0228     /* wait for FCM complete flag or timeout */
0229     wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
0230                        FCM_TIMEOUT_MSECS * HZ/1000);
0231     elbc_fcm_ctrl->status = ctrl->irq_status;
0232     /* store mdr value in case it was needed */
0233     if (elbc_fcm_ctrl->use_mdr)
0234         elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr);
0235 
0236     elbc_fcm_ctrl->use_mdr = 0;
0237 
0238     if (elbc_fcm_ctrl->status != LTESR_CC) {
0239         dev_info(priv->dev,
0240                  "command failed: fir %x fcr %x status %x mdr %x\n",
0241                  in_be32(&lbc->fir), in_be32(&lbc->fcr),
0242              elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr);
0243         return -EIO;
0244     }
0245 
0246     if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
0247         return 0;
0248 
0249     elbc_fcm_ctrl->max_bitflips = 0;
0250 
0251     if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) {
0252         uint32_t lteccr = in_be32(&lbc->lteccr);
0253         /*
0254          * if command was a full page read and the ELBC
0255          * has the LTECCR register, then bits 12-15 (ppc order) of
0256          * LTECCR indicates which 512 byte sub-pages had fixed errors.
0257          * bits 28-31 are uncorrectable errors, marked elsewhere.
0258          * for small page nand only 1 bit is used.
0259          * if the ELBC doesn't have the lteccr register it reads 0
0260          * FIXME: 4 bits can be corrected on NANDs with 2k pages, so
0261          * count the number of sub-pages with bitflips and update
0262          * ecc_stats.corrected accordingly.
0263          */
0264         if (lteccr & 0x000F000F)
0265             out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */
0266         if (lteccr & 0x000F0000) {
0267             mtd->ecc_stats.corrected++;
0268             elbc_fcm_ctrl->max_bitflips = 1;
0269         }
0270     }
0271 
0272     return 0;
0273 }
0274 
0275 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
0276 {
0277     struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
0278     struct fsl_lbc_ctrl *ctrl = priv->ctrl;
0279     struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
0280 
0281     if (priv->page_size) {
0282         out_be32(&lbc->fir,
0283                  (FIR_OP_CM0 << FIR_OP0_SHIFT) |
0284                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
0285                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
0286                  (FIR_OP_CM1 << FIR_OP3_SHIFT) |
0287                  (FIR_OP_RBW << FIR_OP4_SHIFT));
0288 
0289         out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
0290                             (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
0291     } else {
0292         out_be32(&lbc->fir,
0293                  (FIR_OP_CM0 << FIR_OP0_SHIFT) |
0294                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
0295                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
0296                  (FIR_OP_RBW << FIR_OP3_SHIFT));
0297 
0298         if (oob)
0299             out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
0300         else
0301             out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
0302     }
0303 }
0304 
0305 /* cmdfunc send commands to the FCM */
0306 static void fsl_elbc_cmdfunc(struct nand_chip *chip, unsigned int command,
0307                              int column, int page_addr)
0308 {
0309     struct mtd_info *mtd = nand_to_mtd(chip);
0310     struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
0311     struct fsl_lbc_ctrl *ctrl = priv->ctrl;
0312     struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
0313     struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
0314 
0315     elbc_fcm_ctrl->use_mdr = 0;
0316 
0317     /* clear the read buffer */
0318     elbc_fcm_ctrl->read_bytes = 0;
0319     if (command != NAND_CMD_PAGEPROG)
0320         elbc_fcm_ctrl->index = 0;
0321 
0322     switch (command) {
0323     /* READ0 and READ1 read the entire buffer to use hardware ECC. */
0324     case NAND_CMD_READ1:
0325         column += 256;
0326         fallthrough;
0327     case NAND_CMD_READ0:
0328         dev_dbg(priv->dev,
0329                 "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
0330                 " 0x%x, column: 0x%x.\n", page_addr, column);
0331 
0332 
0333         out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
0334         set_addr(mtd, 0, page_addr, 0);
0335 
0336         elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
0337         elbc_fcm_ctrl->index += column;
0338 
0339         fsl_elbc_do_read(chip, 0);
0340         fsl_elbc_run_command(mtd);
0341         return;
0342 
0343     /* RNDOUT moves the pointer inside the page */
0344     case NAND_CMD_RNDOUT:
0345         dev_dbg(priv->dev,
0346             "fsl_elbc_cmdfunc: NAND_CMD_RNDOUT, column: 0x%x.\n",
0347             column);
0348 
0349         elbc_fcm_ctrl->index = column;
0350         return;
0351 
0352     /* READOOB reads only the OOB because no ECC is performed. */
0353     case NAND_CMD_READOOB:
0354         dev_vdbg(priv->dev,
0355                  "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
0356              " 0x%x, column: 0x%x.\n", page_addr, column);
0357 
0358         out_be32(&lbc->fbcr, mtd->oobsize - column);
0359         set_addr(mtd, column, page_addr, 1);
0360 
0361         elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
0362 
0363         fsl_elbc_do_read(chip, 1);
0364         fsl_elbc_run_command(mtd);
0365         return;
0366 
0367     case NAND_CMD_READID:
0368     case NAND_CMD_PARAM:
0369         dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command);
0370 
0371         out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
0372                             (FIR_OP_UA  << FIR_OP1_SHIFT) |
0373                             (FIR_OP_RBW << FIR_OP2_SHIFT));
0374         out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
0375         /*
0376          * although currently it's 8 bytes for READID, we always read
0377          * the maximum 256 bytes(for PARAM)
0378          */
0379         out_be32(&lbc->fbcr, 256);
0380         elbc_fcm_ctrl->read_bytes = 256;
0381         elbc_fcm_ctrl->use_mdr = 1;
0382         elbc_fcm_ctrl->mdr = column;
0383         set_addr(mtd, 0, 0, 0);
0384         fsl_elbc_run_command(mtd);
0385         return;
0386 
0387     /* ERASE1 stores the block and page address */
0388     case NAND_CMD_ERASE1:
0389         dev_vdbg(priv->dev,
0390                  "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
0391                  "page_addr: 0x%x.\n", page_addr);
0392         set_addr(mtd, 0, page_addr, 0);
0393         return;
0394 
0395     /* ERASE2 uses the block and page address from ERASE1 */
0396     case NAND_CMD_ERASE2:
0397         dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
0398 
0399         out_be32(&lbc->fir,
0400                  (FIR_OP_CM0 << FIR_OP0_SHIFT) |
0401                  (FIR_OP_PA  << FIR_OP1_SHIFT) |
0402                  (FIR_OP_CM2 << FIR_OP2_SHIFT) |
0403                  (FIR_OP_CW1 << FIR_OP3_SHIFT) |
0404                  (FIR_OP_RS  << FIR_OP4_SHIFT));
0405 
0406         out_be32(&lbc->fcr,
0407                  (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
0408                  (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
0409                  (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
0410 
0411         out_be32(&lbc->fbcr, 0);
0412         elbc_fcm_ctrl->read_bytes = 0;
0413         elbc_fcm_ctrl->use_mdr = 1;
0414 
0415         fsl_elbc_run_command(mtd);
0416         return;
0417 
0418     /* SEQIN sets up the addr buffer and all registers except the length */
0419     case NAND_CMD_SEQIN: {
0420         __be32 fcr;
0421         dev_vdbg(priv->dev,
0422              "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
0423                  "page_addr: 0x%x, column: 0x%x.\n",
0424                  page_addr, column);
0425 
0426         elbc_fcm_ctrl->column = column;
0427         elbc_fcm_ctrl->use_mdr = 1;
0428 
0429         if (column >= mtd->writesize) {
0430             /* OOB area */
0431             column -= mtd->writesize;
0432             elbc_fcm_ctrl->oob = 1;
0433         } else {
0434             WARN_ON(column != 0);
0435             elbc_fcm_ctrl->oob = 0;
0436         }
0437 
0438         fcr = (NAND_CMD_STATUS   << FCR_CMD1_SHIFT) |
0439               (NAND_CMD_SEQIN    << FCR_CMD2_SHIFT) |
0440               (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
0441 
0442         if (priv->page_size) {
0443             out_be32(&lbc->fir,
0444                      (FIR_OP_CM2 << FIR_OP0_SHIFT) |
0445                      (FIR_OP_CA  << FIR_OP1_SHIFT) |
0446                      (FIR_OP_PA  << FIR_OP2_SHIFT) |
0447                      (FIR_OP_WB  << FIR_OP3_SHIFT) |
0448                      (FIR_OP_CM3 << FIR_OP4_SHIFT) |
0449                      (FIR_OP_CW1 << FIR_OP5_SHIFT) |
0450                      (FIR_OP_RS  << FIR_OP6_SHIFT));
0451         } else {
0452             out_be32(&lbc->fir,
0453                      (FIR_OP_CM0 << FIR_OP0_SHIFT) |
0454                      (FIR_OP_CM2 << FIR_OP1_SHIFT) |
0455                      (FIR_OP_CA  << FIR_OP2_SHIFT) |
0456                      (FIR_OP_PA  << FIR_OP3_SHIFT) |
0457                      (FIR_OP_WB  << FIR_OP4_SHIFT) |
0458                      (FIR_OP_CM3 << FIR_OP5_SHIFT) |
0459                      (FIR_OP_CW1 << FIR_OP6_SHIFT) |
0460                      (FIR_OP_RS  << FIR_OP7_SHIFT));
0461 
0462             if (elbc_fcm_ctrl->oob)
0463                 /* OOB area --> READOOB */
0464                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
0465             else
0466                 /* First 256 bytes --> READ0 */
0467                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
0468         }
0469 
0470         out_be32(&lbc->fcr, fcr);
0471         set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob);
0472         return;
0473     }
0474 
0475     /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
0476     case NAND_CMD_PAGEPROG: {
0477         dev_vdbg(priv->dev,
0478                  "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
0479              "writing %d bytes.\n", elbc_fcm_ctrl->index);
0480 
0481         /* if the write did not start at 0 or is not a full page
0482          * then set the exact length, otherwise use a full page
0483          * write so the HW generates the ECC.
0484          */
0485         if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 ||
0486             elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize)
0487             out_be32(&lbc->fbcr,
0488                 elbc_fcm_ctrl->index - elbc_fcm_ctrl->column);
0489         else
0490             out_be32(&lbc->fbcr, 0);
0491 
0492         fsl_elbc_run_command(mtd);
0493         return;
0494     }
0495 
0496     /* CMD_STATUS must read the status byte while CEB is active */
0497     /* Note - it does not wait for the ready line */
0498     case NAND_CMD_STATUS:
0499         out_be32(&lbc->fir,
0500                  (FIR_OP_CM0 << FIR_OP0_SHIFT) |
0501                  (FIR_OP_RBW << FIR_OP1_SHIFT));
0502         out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
0503         out_be32(&lbc->fbcr, 1);
0504         set_addr(mtd, 0, 0, 0);
0505         elbc_fcm_ctrl->read_bytes = 1;
0506 
0507         fsl_elbc_run_command(mtd);
0508 
0509         /* The chip always seems to report that it is
0510          * write-protected, even when it is not.
0511          */
0512         setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP);
0513         return;
0514 
0515     /* RESET without waiting for the ready line */
0516     case NAND_CMD_RESET:
0517         dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
0518         out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
0519         out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
0520         fsl_elbc_run_command(mtd);
0521         return;
0522 
0523     default:
0524         dev_err(priv->dev,
0525                 "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
0526                 command);
0527     }
0528 }
0529 
0530 static void fsl_elbc_select_chip(struct nand_chip *chip, int cs)
0531 {
0532     /* The hardware does not seem to support multiple
0533      * chips per bank.
0534      */
0535 }
0536 
0537 /*
0538  * Write buf to the FCM Controller Data Buffer
0539  */
0540 static void fsl_elbc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
0541 {
0542     struct mtd_info *mtd = nand_to_mtd(chip);
0543     struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
0544     struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
0545     unsigned int bufsize = mtd->writesize + mtd->oobsize;
0546 
0547     if (len <= 0) {
0548         dev_err(priv->dev, "write_buf of %d bytes", len);
0549         elbc_fcm_ctrl->status = 0;
0550         return;
0551     }
0552 
0553     if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) {
0554         dev_err(priv->dev,
0555                 "write_buf beyond end of buffer "
0556                 "(%d requested, %u available)\n",
0557             len, bufsize - elbc_fcm_ctrl->index);
0558         len = bufsize - elbc_fcm_ctrl->index;
0559     }
0560 
0561     memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len);
0562     /*
0563      * This is workaround for the weird elbc hangs during nand write,
0564      * Scott Wood says: "...perhaps difference in how long it takes a
0565      * write to make it through the localbus compared to a write to IMMR
0566      * is causing problems, and sync isn't helping for some reason."
0567      * Reading back the last byte helps though.
0568      */
0569     in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1);
0570 
0571     elbc_fcm_ctrl->index += len;
0572 }
0573 
0574 /*
0575  * read a byte from either the FCM hardware buffer if it has any data left
0576  * otherwise issue a command to read a single byte.
0577  */
0578 static u8 fsl_elbc_read_byte(struct nand_chip *chip)
0579 {
0580     struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
0581     struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
0582 
0583     /* If there are still bytes in the FCM, then use the next byte. */
0584     if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes)
0585         return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]);
0586 
0587     dev_err(priv->dev, "read_byte beyond end of buffer\n");
0588     return ERR_BYTE;
0589 }
0590 
0591 /*
0592  * Read from the FCM Controller Data Buffer
0593  */
0594 static void fsl_elbc_read_buf(struct nand_chip *chip, u8 *buf, int len)
0595 {
0596     struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
0597     struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
0598     int avail;
0599 
0600     if (len < 0)
0601         return;
0602 
0603     avail = min((unsigned int)len,
0604             elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
0605     memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail);
0606     elbc_fcm_ctrl->index += avail;
0607 
0608     if (len > avail)
0609         dev_err(priv->dev,
0610                 "read_buf beyond end of buffer "
0611                 "(%d requested, %d available)\n",
0612                 len, avail);
0613 }
0614 
0615 /* This function is called after Program and Erase Operations to
0616  * check for success or failure.
0617  */
0618 static int fsl_elbc_wait(struct nand_chip *chip)
0619 {
0620     struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
0621     struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
0622 
0623     if (elbc_fcm_ctrl->status != LTESR_CC)
0624         return NAND_STATUS_FAIL;
0625 
0626     /* The chip always seems to report that it is
0627      * write-protected, even when it is not.
0628      */
0629     return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP;
0630 }
0631 
0632 static int fsl_elbc_read_page(struct nand_chip *chip, uint8_t *buf,
0633                   int oob_required, int page)
0634 {
0635     struct mtd_info *mtd = nand_to_mtd(chip);
0636     struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
0637     struct fsl_lbc_ctrl *ctrl = priv->ctrl;
0638     struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
0639 
0640     nand_read_page_op(chip, page, 0, buf, mtd->writesize);
0641     if (oob_required)
0642         fsl_elbc_read_buf(chip, chip->oob_poi, mtd->oobsize);
0643 
0644     if (fsl_elbc_wait(chip) & NAND_STATUS_FAIL)
0645         mtd->ecc_stats.failed++;
0646 
0647     return elbc_fcm_ctrl->max_bitflips;
0648 }
0649 
0650 /* ECC will be calculated automatically, and errors will be detected in
0651  * waitfunc.
0652  */
0653 static int fsl_elbc_write_page(struct nand_chip *chip, const uint8_t *buf,
0654                    int oob_required, int page)
0655 {
0656     struct mtd_info *mtd = nand_to_mtd(chip);
0657 
0658     nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
0659     fsl_elbc_write_buf(chip, chip->oob_poi, mtd->oobsize);
0660 
0661     return nand_prog_page_end_op(chip);
0662 }
0663 
0664 /* ECC will be calculated automatically, and errors will be detected in
0665  * waitfunc.
0666  */
0667 static int fsl_elbc_write_subpage(struct nand_chip *chip, uint32_t offset,
0668                   uint32_t data_len, const uint8_t *buf,
0669                   int oob_required, int page)
0670 {
0671     struct mtd_info *mtd = nand_to_mtd(chip);
0672 
0673     nand_prog_page_begin_op(chip, page, 0, NULL, 0);
0674     fsl_elbc_write_buf(chip, buf, mtd->writesize);
0675     fsl_elbc_write_buf(chip, chip->oob_poi, mtd->oobsize);
0676     return nand_prog_page_end_op(chip);
0677 }
0678 
0679 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
0680 {
0681     struct fsl_lbc_ctrl *ctrl = priv->ctrl;
0682     struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
0683     struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
0684     struct nand_chip *chip = &priv->chip;
0685     struct mtd_info *mtd = nand_to_mtd(chip);
0686 
0687     dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
0688 
0689     /* Fill in fsl_elbc_mtd structure */
0690     mtd->dev.parent = priv->dev;
0691     nand_set_flash_node(chip, priv->dev->of_node);
0692 
0693     /* set timeout to maximum */
0694     priv->fmr = 15 << FMR_CWTO_SHIFT;
0695     if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS)
0696         priv->fmr |= FMR_ECCM;
0697 
0698     /* fill in nand_chip structure */
0699     /* set up function call table */
0700     chip->legacy.read_byte = fsl_elbc_read_byte;
0701     chip->legacy.write_buf = fsl_elbc_write_buf;
0702     chip->legacy.read_buf = fsl_elbc_read_buf;
0703     chip->legacy.select_chip = fsl_elbc_select_chip;
0704     chip->legacy.cmdfunc = fsl_elbc_cmdfunc;
0705     chip->legacy.waitfunc = fsl_elbc_wait;
0706     chip->legacy.set_features = nand_get_set_features_notsupp;
0707     chip->legacy.get_features = nand_get_set_features_notsupp;
0708 
0709     chip->bbt_td = &bbt_main_descr;
0710     chip->bbt_md = &bbt_mirror_descr;
0711 
0712     /* set up nand options */
0713     chip->bbt_options = NAND_BBT_USE_FLASH;
0714 
0715     chip->controller = &elbc_fcm_ctrl->controller;
0716     nand_set_controller_data(chip, priv);
0717 
0718     return 0;
0719 }
0720 
0721 static int fsl_elbc_attach_chip(struct nand_chip *chip)
0722 {
0723     struct mtd_info *mtd = nand_to_mtd(chip);
0724     struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
0725     struct fsl_lbc_ctrl *ctrl = priv->ctrl;
0726     struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
0727     unsigned int al;
0728 
0729     switch (chip->ecc.engine_type) {
0730     /*
0731      * if ECC was not chosen in DT, decide whether to use HW or SW ECC from
0732      * CS Base Register
0733      */
0734     case NAND_ECC_ENGINE_TYPE_NONE:
0735         /* If CS Base Register selects full hardware ECC then use it */
0736         if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
0737             BR_DECC_CHK_GEN) {
0738             chip->ecc.read_page = fsl_elbc_read_page;
0739             chip->ecc.write_page = fsl_elbc_write_page;
0740             chip->ecc.write_subpage = fsl_elbc_write_subpage;
0741 
0742             chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
0743             mtd_set_ooblayout(mtd, &fsl_elbc_ooblayout_ops);
0744             chip->ecc.size = 512;
0745             chip->ecc.bytes = 3;
0746             chip->ecc.strength = 1;
0747         } else {
0748             /* otherwise fall back to default software ECC */
0749             chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
0750             chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
0751         }
0752         break;
0753 
0754     /* if SW ECC was chosen in DT, we do not need to set anything here */
0755     case NAND_ECC_ENGINE_TYPE_SOFT:
0756         break;
0757 
0758     /* should we also implement *_ECC_ENGINE_CONTROLLER to do as above? */
0759     default:
0760         return -EINVAL;
0761     }
0762 
0763     /* calculate FMR Address Length field */
0764     al = 0;
0765     if (chip->pagemask & 0xffff0000)
0766         al++;
0767     if (chip->pagemask & 0xff000000)
0768         al++;
0769 
0770     priv->fmr |= al << FMR_AL_SHIFT;
0771 
0772     dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
0773             nanddev_ntargets(&chip->base));
0774     dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
0775             nanddev_target_size(&chip->base));
0776     dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
0777             chip->pagemask);
0778     dev_dbg(priv->dev, "fsl_elbc_init: nand->legacy.chip_delay = %d\n",
0779             chip->legacy.chip_delay);
0780     dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
0781             chip->badblockpos);
0782     dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
0783             chip->chip_shift);
0784     dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n",
0785             chip->page_shift);
0786     dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
0787             chip->phys_erase_shift);
0788     dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.engine_type = %d\n",
0789         chip->ecc.engine_type);
0790     dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
0791             chip->ecc.steps);
0792     dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
0793             chip->ecc.bytes);
0794     dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
0795             chip->ecc.total);
0796     dev_dbg(priv->dev, "fsl_elbc_init: mtd->ooblayout = %p\n",
0797         mtd->ooblayout);
0798     dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
0799     dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
0800     dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
0801             mtd->erasesize);
0802     dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n",
0803             mtd->writesize);
0804     dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
0805             mtd->oobsize);
0806 
0807     /* adjust Option Register and ECC to match Flash page size */
0808     if (mtd->writesize == 512) {
0809         priv->page_size = 0;
0810         clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
0811     } else if (mtd->writesize == 2048) {
0812         priv->page_size = 1;
0813         setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
0814     } else {
0815         dev_err(priv->dev,
0816                 "fsl_elbc_init: page size %d is not supported\n",
0817                 mtd->writesize);
0818         return -ENOTSUPP;
0819     }
0820 
0821     return 0;
0822 }
0823 
0824 static const struct nand_controller_ops fsl_elbc_controller_ops = {
0825     .attach_chip = fsl_elbc_attach_chip,
0826 };
0827 
0828 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
0829 {
0830     struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
0831     struct mtd_info *mtd = nand_to_mtd(&priv->chip);
0832 
0833     kfree(mtd->name);
0834 
0835     if (priv->vbase)
0836         iounmap(priv->vbase);
0837 
0838     elbc_fcm_ctrl->chips[priv->bank] = NULL;
0839     kfree(priv);
0840     return 0;
0841 }
0842 
0843 static DEFINE_MUTEX(fsl_elbc_nand_mutex);
0844 
0845 static int fsl_elbc_nand_probe(struct platform_device *pdev)
0846 {
0847     struct fsl_lbc_regs __iomem *lbc;
0848     struct fsl_elbc_mtd *priv;
0849     struct resource res;
0850     struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
0851     static const char *part_probe_types[]
0852         = { "cmdlinepart", "RedBoot", "ofpart", NULL };
0853     int ret;
0854     int bank;
0855     struct device *dev;
0856     struct device_node *node = pdev->dev.of_node;
0857     struct mtd_info *mtd;
0858 
0859     if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
0860         return -ENODEV;
0861     lbc = fsl_lbc_ctrl_dev->regs;
0862     dev = fsl_lbc_ctrl_dev->dev;
0863 
0864     /* get, allocate and map the memory resource */
0865     ret = of_address_to_resource(node, 0, &res);
0866     if (ret) {
0867         dev_err(dev, "failed to get resource\n");
0868         return ret;
0869     }
0870 
0871     /* find which chip select it is connected to */
0872     for (bank = 0; bank < MAX_BANKS; bank++)
0873         if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
0874             (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
0875             (in_be32(&lbc->bank[bank].br) &
0876              in_be32(&lbc->bank[bank].or) & BR_BA)
0877              == fsl_lbc_addr(res.start))
0878             break;
0879 
0880     if (bank >= MAX_BANKS) {
0881         dev_err(dev, "address did not match any chip selects\n");
0882         return -ENODEV;
0883     }
0884 
0885     priv = kzalloc(sizeof(*priv), GFP_KERNEL);
0886     if (!priv)
0887         return -ENOMEM;
0888 
0889     mutex_lock(&fsl_elbc_nand_mutex);
0890     if (!fsl_lbc_ctrl_dev->nand) {
0891         elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL);
0892         if (!elbc_fcm_ctrl) {
0893             mutex_unlock(&fsl_elbc_nand_mutex);
0894             ret = -ENOMEM;
0895             goto err;
0896         }
0897         elbc_fcm_ctrl->counter++;
0898 
0899         nand_controller_init(&elbc_fcm_ctrl->controller);
0900         fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
0901     } else {
0902         elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
0903     }
0904     mutex_unlock(&fsl_elbc_nand_mutex);
0905 
0906     elbc_fcm_ctrl->chips[bank] = priv;
0907     priv->bank = bank;
0908     priv->ctrl = fsl_lbc_ctrl_dev;
0909     priv->dev = &pdev->dev;
0910     dev_set_drvdata(priv->dev, priv);
0911 
0912     priv->vbase = ioremap(res.start, resource_size(&res));
0913     if (!priv->vbase) {
0914         dev_err(dev, "failed to map chip region\n");
0915         ret = -ENOMEM;
0916         goto err;
0917     }
0918 
0919     mtd = nand_to_mtd(&priv->chip);
0920     mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
0921     if (!nand_to_mtd(&priv->chip)->name) {
0922         ret = -ENOMEM;
0923         goto err;
0924     }
0925 
0926     ret = fsl_elbc_chip_init(priv);
0927     if (ret)
0928         goto err;
0929 
0930     priv->chip.controller->ops = &fsl_elbc_controller_ops;
0931     ret = nand_scan(&priv->chip, 1);
0932     if (ret)
0933         goto err;
0934 
0935     /* First look for RedBoot table or partitions on the command
0936      * line, these take precedence over device tree information */
0937     ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
0938     if (ret)
0939         goto cleanup_nand;
0940 
0941     pr_info("eLBC NAND device at 0x%llx, bank %d\n",
0942         (unsigned long long)res.start, priv->bank);
0943 
0944     return 0;
0945 
0946 cleanup_nand:
0947     nand_cleanup(&priv->chip);
0948 err:
0949     fsl_elbc_chip_remove(priv);
0950 
0951     return ret;
0952 }
0953 
0954 static int fsl_elbc_nand_remove(struct platform_device *pdev)
0955 {
0956     struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
0957     struct fsl_elbc_mtd *priv = dev_get_drvdata(&pdev->dev);
0958     struct nand_chip *chip = &priv->chip;
0959     int ret;
0960 
0961     ret = mtd_device_unregister(nand_to_mtd(chip));
0962     WARN_ON(ret);
0963     nand_cleanup(chip);
0964 
0965     fsl_elbc_chip_remove(priv);
0966 
0967     mutex_lock(&fsl_elbc_nand_mutex);
0968     elbc_fcm_ctrl->counter--;
0969     if (!elbc_fcm_ctrl->counter) {
0970         fsl_lbc_ctrl_dev->nand = NULL;
0971         kfree(elbc_fcm_ctrl);
0972     }
0973     mutex_unlock(&fsl_elbc_nand_mutex);
0974 
0975     return 0;
0976 
0977 }
0978 
0979 static const struct of_device_id fsl_elbc_nand_match[] = {
0980     { .compatible = "fsl,elbc-fcm-nand", },
0981     {}
0982 };
0983 MODULE_DEVICE_TABLE(of, fsl_elbc_nand_match);
0984 
0985 static struct platform_driver fsl_elbc_nand_driver = {
0986     .driver = {
0987         .name = "fsl,elbc-fcm-nand",
0988         .of_match_table = fsl_elbc_nand_match,
0989     },
0990     .probe = fsl_elbc_nand_probe,
0991     .remove = fsl_elbc_nand_remove,
0992 };
0993 
0994 module_platform_driver(fsl_elbc_nand_driver);
0995 
0996 MODULE_LICENSE("GPL");
0997 MODULE_AUTHOR("Freescale");
0998 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");
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