nand/raw/davinci_nand.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * davinci_nand.c - NAND Flash Driver for DaVinci family chips
0004  *
0005  * Copyright © 2006 Texas Instruments.
0006  *
0007  * Port to 2.6.23 Copyright © 2008 by:
0008  *   Sander Huijsen <Shuijsen@optelecom-nkf.com>
0009  *   Troy Kisky <troy.kisky@boundarydevices.com>
0010  *   Dirk Behme <Dirk.Behme@gmail.com>
0011  */
0012
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/err.h>
0017 #include <linux/iopoll.h>
0018 #include <linux/mtd/rawnand.h>
0019 #include <linux/mtd/partitions.h>
0020 #include <linux/slab.h>
0021 #include <linux/of_device.h>
0022 #include <linux/of.h>
0023
0024 #include <linux/platform_data/mtd-davinci.h>
0025 #include <linux/platform_data/mtd-davinci-aemif.h>
0026
0027 /*
0028  * This is a device driver for the NAND flash controller found on the
0029  * various DaVinci family chips.  It handles up to four SoC chipselects,
0030  * and some flavors of secondary chipselect (e.g. based on A12) as used
0031  * with multichip packages.
0032  *
0033  * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
0034  * available on chips like the DM355 and OMAP-L137 and needed with the
0035  * more error-prone MLC NAND chips.
0036  *
0037  * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
0038  * outputs in a "wire-AND" configuration, with no per-chip signals.
0039  */
0040 struct davinci_nand_info {
0041     struct nand_controller  controller;
0042     struct nand_chip    chip;
0043
0044     struct platform_device  *pdev;
0045
0046     bool            is_readmode;
0047
0048     void __iomem        *base;
0049     void __iomem        *vaddr;
0050
0051     void __iomem        *current_cs;
0052
0053     uint32_t        mask_chipsel;
0054     uint32_t        mask_ale;
0055     uint32_t        mask_cle;
0056
0057     uint32_t        core_chipsel;
0058
0059     struct davinci_aemif_timing *timing;
0060 };
0061
0062 static DEFINE_SPINLOCK(davinci_nand_lock);
0063 static bool ecc4_busy;
0064
0065 static inline struct davinci_nand_info *to_davinci_nand(struct mtd_info *mtd)
0066 {
0067     return container_of(mtd_to_nand(mtd), struct davinci_nand_info, chip);
0068 }
0069
0070 static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
0071         int offset)
0072 {
0073     return __raw_readl(info->base + offset);
0074 }
0075
0076 static inline void davinci_nand_writel(struct davinci_nand_info *info,
0077         int offset, unsigned long value)
0078 {
0079     __raw_writel(value, info->base + offset);
0080 }
0081
0082 /*----------------------------------------------------------------------*/
0083
0084 /*
0085  * 1-bit hardware ECC ... context maintained for each core chipselect
0086  */
0087
0088 static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
0089 {
0090     struct davinci_nand_info *info = to_davinci_nand(mtd);
0091
0092     return davinci_nand_readl(info, NANDF1ECC_OFFSET
0093             + 4 * info->core_chipsel);
0094 }
0095
0096 static void nand_davinci_hwctl_1bit(struct nand_chip *chip, int mode)
0097 {
0098     struct davinci_nand_info *info;
0099     uint32_t nandcfr;
0100     unsigned long flags;
0101
0102     info = to_davinci_nand(nand_to_mtd(chip));
0103
0104     /* Reset ECC hardware */
0105     nand_davinci_readecc_1bit(nand_to_mtd(chip));
0106
0107     spin_lock_irqsave(&davinci_nand_lock, flags);
0108
0109     /* Restart ECC hardware */
0110     nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
0111     nandcfr |= BIT(8 + info->core_chipsel);
0112     davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
0113
0114     spin_unlock_irqrestore(&davinci_nand_lock, flags);
0115 }
0116
0117 /*
0118  * Read hardware ECC value and pack into three bytes
0119  */
0120 static int nand_davinci_calculate_1bit(struct nand_chip *chip,
0121                        const u_char *dat, u_char *ecc_code)
0122 {
0123     unsigned int ecc_val = nand_davinci_readecc_1bit(nand_to_mtd(chip));
0124     unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
0125
0126     /* invert so that erased block ecc is correct */
0127     ecc24 = ~ecc24;
0128     ecc_code[0] = (u_char)(ecc24);
0129     ecc_code[1] = (u_char)(ecc24 >> 8);
0130     ecc_code[2] = (u_char)(ecc24 >> 16);
0131
0132     return 0;
0133 }
0134
0135 static int nand_davinci_correct_1bit(struct nand_chip *chip, u_char *dat,
0136                      u_char *read_ecc, u_char *calc_ecc)
0137 {
0138     uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
0139                       (read_ecc[2] << 16);
0140     uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
0141                       (calc_ecc[2] << 16);
0142     uint32_t diff = eccCalc ^ eccNand;
0143
0144     if (diff) {
0145         if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
0146             /* Correctable error */
0147             if ((diff >> (12 + 3)) < chip->ecc.size) {
0148                 dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
0149                 return 1;
0150             } else {
0151                 return -EBADMSG;
0152             }
0153         } else if (!(diff & (diff - 1))) {
0154             /* Single bit ECC error in the ECC itself,
0155              * nothing to fix */
0156             return 1;
0157         } else {
0158             /* Uncorrectable error */
0159             return -EBADMSG;
0160         }
0161
0162     }
0163     return 0;
0164 }
0165
0166 /*----------------------------------------------------------------------*/
0167
0168 /*
0169  * 4-bit hardware ECC ... context maintained over entire AEMIF
0170  *
0171  * This is a syndrome engine, but we avoid NAND_ECC_PLACEMENT_INTERLEAVED
0172  * since that forces use of a problematic "infix OOB" layout.
0173  * Among other things, it trashes manufacturer bad block markers.
0174  * Also, and specific to this hardware, it ECC-protects the "prepad"
0175  * in the OOB ... while having ECC protection for parts of OOB would
0176  * seem useful, the current MTD stack sometimes wants to update the
0177  * OOB without recomputing ECC.
0178  */
0179
0180 static void nand_davinci_hwctl_4bit(struct nand_chip *chip, int mode)
0181 {
0182     struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
0183     unsigned long flags;
0184     u32 val;
0185
0186     /* Reset ECC hardware */
0187     davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
0188
0189     spin_lock_irqsave(&davinci_nand_lock, flags);
0190
0191     /* Start 4-bit ECC calculation for read/write */
0192     val = davinci_nand_readl(info, NANDFCR_OFFSET);
0193     val &= ~(0x03 << 4);
0194     val |= (info->core_chipsel << 4) | BIT(12);
0195     davinci_nand_writel(info, NANDFCR_OFFSET, val);
0196
0197     info->is_readmode = (mode == NAND_ECC_READ);
0198
0199     spin_unlock_irqrestore(&davinci_nand_lock, flags);
0200 }
0201
0202 /* Read raw ECC code after writing to NAND. */
0203 static void
0204 nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
0205 {
0206     const u32 mask = 0x03ff03ff;
0207
0208     code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
0209     code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
0210     code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
0211     code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
0212 }
0213
0214 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
0215 static int nand_davinci_calculate_4bit(struct nand_chip *chip,
0216                        const u_char *dat, u_char *ecc_code)
0217 {
0218     struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
0219     u32 raw_ecc[4], *p;
0220     unsigned i;
0221
0222     /* After a read, terminate ECC calculation by a dummy read
0223      * of some 4-bit ECC register.  ECC covers everything that
0224      * was read; correct() just uses the hardware state, so
0225      * ecc_code is not needed.
0226      */
0227     if (info->is_readmode) {
0228         davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
0229         return 0;
0230     }
0231
0232     /* Pack eight raw 10-bit ecc values into ten bytes, making
0233      * two passes which each convert four values (in upper and
0234      * lower halves of two 32-bit words) into five bytes.  The
0235      * ROM boot loader uses this same packing scheme.
0236      */
0237     nand_davinci_readecc_4bit(info, raw_ecc);
0238     for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
0239         *ecc_code++ =   p[0]        & 0xff;
0240         *ecc_code++ = ((p[0] >>  8) & 0x03) | ((p[0] >> 14) & 0xfc);
0241         *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] <<  4) & 0xf0);
0242         *ecc_code++ = ((p[1] >>  4) & 0x3f) | ((p[1] >> 10) & 0xc0);
0243         *ecc_code++ =  (p[1] >> 18) & 0xff;
0244     }
0245
0246     return 0;
0247 }
0248
0249 /* Correct up to 4 bits in data we just read, using state left in the
0250  * hardware plus the ecc_code computed when it was first written.
0251  */
0252 static int nand_davinci_correct_4bit(struct nand_chip *chip, u_char *data,
0253                      u_char *ecc_code, u_char *null)
0254 {
0255     int i;
0256     struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
0257     unsigned short ecc10[8];
0258     unsigned short *ecc16;
0259     u32 syndrome[4];
0260     u32 ecc_state;
0261     unsigned num_errors, corrected;
0262     unsigned long timeo;
0263
0264     /* Unpack ten bytes into eight 10 bit values.  We know we're
0265      * little-endian, and use type punning for less shifting/masking.
0266      */
0267     if (WARN_ON(0x01 & (uintptr_t)ecc_code))
0268         return -EINVAL;
0269     ecc16 = (unsigned short *)ecc_code;
0270
0271     ecc10[0] =  (ecc16[0] >>  0) & 0x3ff;
0272     ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
0273     ecc10[2] =  (ecc16[1] >>  4) & 0x3ff;
0274     ecc10[3] = ((ecc16[1] >> 14) & 0x3)  | ((ecc16[2] << 2) & 0x3fc);
0275     ecc10[4] =  (ecc16[2] >>  8)         | ((ecc16[3] << 8) & 0x300);
0276     ecc10[5] =  (ecc16[3] >>  2) & 0x3ff;
0277     ecc10[6] = ((ecc16[3] >> 12) & 0xf)  | ((ecc16[4] << 4) & 0x3f0);
0278     ecc10[7] =  (ecc16[4] >>  6) & 0x3ff;
0279
0280     /* Tell ECC controller about the expected ECC codes. */
0281     for (i = 7; i >= 0; i--)
0282         davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);
0283
0284     /* Allow time for syndrome calculation ... then read it.
0285      * A syndrome of all zeroes 0 means no detected errors.
0286      */
0287     davinci_nand_readl(info, NANDFSR_OFFSET);
0288     nand_davinci_readecc_4bit(info, syndrome);
0289     if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
0290         return 0;
0291
0292     /*
0293      * Clear any previous address calculation by doing a dummy read of an
0294      * error address register.
0295      */
0296     davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
0297
0298     /* Start address calculation, and wait for it to complete.
0299      * We _could_ start reading more data while this is working,
0300      * to speed up the overall page read.
0301      */
0302     davinci_nand_writel(info, NANDFCR_OFFSET,
0303             davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
0304
0305     /*
0306      * ECC_STATE field reads 0x3 (Error correction complete) immediately
0307      * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
0308      * begin trying to poll for the state, you may fall right out of your
0309      * loop without any of the correction calculations having taken place.
0310      * The recommendation from the hardware team is to initially delay as
0311      * long as ECC_STATE reads less than 4. After that, ECC HW has entered
0312      * correction state.
0313      */
0314     timeo = jiffies + usecs_to_jiffies(100);
0315     do {
0316         ecc_state = (davinci_nand_readl(info,
0317                 NANDFSR_OFFSET) >> 8) & 0x0f;
0318         cpu_relax();
0319     } while ((ecc_state < 4) && time_before(jiffies, timeo));
0320
0321     for (;;) {
0322         u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
0323
0324         switch ((fsr >> 8) & 0x0f) {
0325         case 0:     /* no error, should not happen */
0326             davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
0327             return 0;
0328         case 1:     /* five or more errors detected */
0329             davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
0330             return -EBADMSG;
0331         case 2:     /* error addresses computed */
0332         case 3:
0333             num_errors = 1 + ((fsr >> 16) & 0x03);
0334             goto correct;
0335         default:    /* still working on it */
0336             cpu_relax();
0337             continue;
0338         }
0339     }
0340
0341 correct:
0342     /* correct each error */
0343     for (i = 0, corrected = 0; i < num_errors; i++) {
0344         int error_address, error_value;
0345
0346         if (i > 1) {
0347             error_address = davinci_nand_readl(info,
0348                         NAND_ERR_ADD2_OFFSET);
0349             error_value = davinci_nand_readl(info,
0350                         NAND_ERR_ERRVAL2_OFFSET);
0351         } else {
0352             error_address = davinci_nand_readl(info,
0353                         NAND_ERR_ADD1_OFFSET);
0354             error_value = davinci_nand_readl(info,
0355                         NAND_ERR_ERRVAL1_OFFSET);
0356         }
0357
0358         if (i & 1) {
0359             error_address >>= 16;
0360             error_value >>= 16;
0361         }
0362         error_address &= 0x3ff;
0363         error_address = (512 + 7) - error_address;
0364
0365         if (error_address < 512) {
0366             data[error_address] ^= error_value;
0367             corrected++;
0368         }
0369     }
0370
0371     return corrected;
0372 }
0373
0374 /*----------------------------------------------------------------------*/
0375
0376 /* An ECC layout for using 4-bit ECC with small-page flash, storing
0377  * ten ECC bytes plus the manufacturer's bad block marker byte, and
0378  * and not overlapping the default BBT markers.
0379  */
0380 static int hwecc4_ooblayout_small_ecc(struct mtd_info *mtd, int section,
0381                       struct mtd_oob_region *oobregion)
0382 {
0383     if (section > 2)
0384         return -ERANGE;
0385
0386     if (!section) {
0387         oobregion->offset = 0;
0388         oobregion->length = 5;
0389     } else if (section == 1) {
0390         oobregion->offset = 6;
0391         oobregion->length = 2;
0392     } else {
0393         oobregion->offset = 13;
0394         oobregion->length = 3;
0395     }
0396
0397     return 0;
0398 }
0399
0400 static int hwecc4_ooblayout_small_free(struct mtd_info *mtd, int section,
0401                        struct mtd_oob_region *oobregion)
0402 {
0403     if (section > 1)
0404         return -ERANGE;
0405
0406     if (!section) {
0407         oobregion->offset = 8;
0408         oobregion->length = 5;
0409     } else {
0410         oobregion->offset = 16;
0411         oobregion->length = mtd->oobsize - 16;
0412     }
0413
0414     return 0;
0415 }
0416
0417 static const struct mtd_ooblayout_ops hwecc4_small_ooblayout_ops = {
0418     .ecc = hwecc4_ooblayout_small_ecc,
0419     .free = hwecc4_ooblayout_small_free,
0420 };
0421
0422 #if defined(CONFIG_OF)
0423 static const struct of_device_id davinci_nand_of_match[] = {
0424     {.compatible = "ti,davinci-nand", },
0425     {.compatible = "ti,keystone-nand", },
0426     {},
0427 };
0428 MODULE_DEVICE_TABLE(of, davinci_nand_of_match);
0429
0430 static struct davinci_nand_pdata
0431     *nand_davinci_get_pdata(struct platform_device *pdev)
0432 {
0433     if (!dev_get_platdata(&pdev->dev) && pdev->dev.of_node) {
0434         struct davinci_nand_pdata *pdata;
0435         const char *mode;
0436         u32 prop;
0437
0438         pdata =  devm_kzalloc(&pdev->dev,
0439                 sizeof(struct davinci_nand_pdata),
0440                 GFP_KERNEL);
0441         pdev->dev.platform_data = pdata;
0442         if (!pdata)
0443             return ERR_PTR(-ENOMEM);
0444         if (!of_property_read_u32(pdev->dev.of_node,
0445             "ti,davinci-chipselect", &prop))
0446             pdata->core_chipsel = prop;
0447         else
0448             return ERR_PTR(-EINVAL);
0449
0450         if (!of_property_read_u32(pdev->dev.of_node,
0451             "ti,davinci-mask-ale", &prop))
0452             pdata->mask_ale = prop;
0453         if (!of_property_read_u32(pdev->dev.of_node,
0454             "ti,davinci-mask-cle", &prop))
0455             pdata->mask_cle = prop;
0456         if (!of_property_read_u32(pdev->dev.of_node,
0457             "ti,davinci-mask-chipsel", &prop))
0458             pdata->mask_chipsel = prop;
0459         if (!of_property_read_string(pdev->dev.of_node,
0460             "ti,davinci-ecc-mode", &mode)) {
0461             if (!strncmp("none", mode, 4))
0462                 pdata->engine_type = NAND_ECC_ENGINE_TYPE_NONE;
0463             if (!strncmp("soft", mode, 4))
0464                 pdata->engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
0465             if (!strncmp("hw", mode, 2))
0466                 pdata->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
0467         }
0468         if (!of_property_read_u32(pdev->dev.of_node,
0469             "ti,davinci-ecc-bits", &prop))
0470             pdata->ecc_bits = prop;
0471
0472         if (!of_property_read_u32(pdev->dev.of_node,
0473             "ti,davinci-nand-buswidth", &prop) && prop == 16)
0474             pdata->options |= NAND_BUSWIDTH_16;
0475
0476         if (of_property_read_bool(pdev->dev.of_node,
0477             "ti,davinci-nand-use-bbt"))
0478             pdata->bbt_options = NAND_BBT_USE_FLASH;
0479
0480         /*
0481          * Since kernel v4.8, this driver has been fixed to enable
0482          * use of 4-bit hardware ECC with subpages and verified on
0483          * TI's keystone EVMs (K2L, K2HK and K2E).
0484          * However, in the interest of not breaking systems using
0485          * existing UBI partitions, sub-page writes are not being
0486          * (re)enabled. If you want to use subpage writes on Keystone
0487          * platforms (i.e. do not have any existing UBI partitions),
0488          * then use "ti,davinci-nand" as the compatible in your
0489          * device-tree file.
0490          */
0491         if (of_device_is_compatible(pdev->dev.of_node,
0492                         "ti,keystone-nand")) {
0493             pdata->options |= NAND_NO_SUBPAGE_WRITE;
0494         }
0495     }
0496
0497     return dev_get_platdata(&pdev->dev);
0498 }
0499 #else
0500 static struct davinci_nand_pdata
0501     *nand_davinci_get_pdata(struct platform_device *pdev)
0502 {
0503     return dev_get_platdata(&pdev->dev);
0504 }
0505 #endif
0506
0507 static int davinci_nand_attach_chip(struct nand_chip *chip)
0508 {
0509     struct mtd_info *mtd = nand_to_mtd(chip);
0510     struct davinci_nand_info *info = to_davinci_nand(mtd);
0511     struct davinci_nand_pdata *pdata = nand_davinci_get_pdata(info->pdev);
0512     int ret = 0;
0513
0514     if (IS_ERR(pdata))
0515         return PTR_ERR(pdata);
0516
0517     /* Use board-specific ECC config */
0518     chip->ecc.engine_type = pdata->engine_type;
0519     chip->ecc.placement = pdata->ecc_placement;
0520
0521     switch (chip->ecc.engine_type) {
0522     case NAND_ECC_ENGINE_TYPE_NONE:
0523         pdata->ecc_bits = 0;
0524         break;
0525     case NAND_ECC_ENGINE_TYPE_SOFT:
0526         pdata->ecc_bits = 0;
0527         /*
0528          * This driver expects Hamming based ECC when engine_type is set
0529          * to NAND_ECC_ENGINE_TYPE_SOFT. Force ecc.algo to
0530          * NAND_ECC_ALGO_HAMMING to avoid adding an extra ->ecc_algo
0531          * field to davinci_nand_pdata.
0532          */
0533         chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
0534         break;
0535     case NAND_ECC_ENGINE_TYPE_ON_HOST:
0536         if (pdata->ecc_bits == 4) {
0537             int chunks = mtd->writesize / 512;
0538
0539             if (!chunks || mtd->oobsize < 16) {
0540                 dev_dbg(&info->pdev->dev, "too small\n");
0541                 return -EINVAL;
0542             }
0543
0544             /*
0545              * No sanity checks:  CPUs must support this,
0546              * and the chips may not use NAND_BUSWIDTH_16.
0547              */
0548
0549             /* No sharing 4-bit hardware between chipselects yet */
0550             spin_lock_irq(&davinci_nand_lock);
0551             if (ecc4_busy)
0552                 ret = -EBUSY;
0553             else
0554                 ecc4_busy = true;
0555             spin_unlock_irq(&davinci_nand_lock);
0556
0557             if (ret == -EBUSY)
0558                 return ret;
0559
0560             chip->ecc.calculate = nand_davinci_calculate_4bit;
0561             chip->ecc.correct = nand_davinci_correct_4bit;
0562             chip->ecc.hwctl = nand_davinci_hwctl_4bit;
0563             chip->ecc.bytes = 10;
0564             chip->ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
0565             chip->ecc.algo = NAND_ECC_ALGO_BCH;
0566
0567             /*
0568              * Update ECC layout if needed ... for 1-bit HW ECC, the
0569              * default is OK, but it allocates 6 bytes when only 3
0570              * are needed (for each 512 bytes). For 4-bit HW ECC,
0571              * the default is not usable: 10 bytes needed, not 6.
0572              *
0573              * For small page chips, preserve the manufacturer's
0574              * badblock marking data ... and make sure a flash BBT
0575              * table marker fits in the free bytes.
0576              */
0577             if (chunks == 1) {
0578                 mtd_set_ooblayout(mtd,
0579                           &hwecc4_small_ooblayout_ops);
0580             } else if (chunks == 4 || chunks == 8) {
0581                 mtd_set_ooblayout(mtd,
0582                           nand_get_large_page_ooblayout());
0583                 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
0584             } else {
0585                 return -EIO;
0586             }
0587         } else {
0588             /* 1bit ecc hamming */
0589             chip->ecc.calculate = nand_davinci_calculate_1bit;
0590             chip->ecc.correct = nand_davinci_correct_1bit;
0591             chip->ecc.hwctl = nand_davinci_hwctl_1bit;
0592             chip->ecc.bytes = 3;
0593             chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
0594         }
0595         chip->ecc.size = 512;
0596         chip->ecc.strength = pdata->ecc_bits;
0597         break;
0598     default:
0599         return -EINVAL;
0600     }
0601
0602     return ret;
0603 }
0604
0605 static void nand_davinci_data_in(struct davinci_nand_info *info, void *buf,
0606                  unsigned int len, bool force_8bit)
0607 {
0608     u32 alignment = ((uintptr_t)buf | len) & 3;
0609
0610     if (force_8bit || (alignment & 1))
0611         ioread8_rep(info->current_cs, buf, len);
0612     else if (alignment & 3)
0613         ioread16_rep(info->current_cs, buf, len >> 1);
0614     else
0615         ioread32_rep(info->current_cs, buf, len >> 2);
0616 }
0617
0618 static void nand_davinci_data_out(struct davinci_nand_info *info,
0619                   const void *buf, unsigned int len,
0620                   bool force_8bit)
0621 {
0622     u32 alignment = ((uintptr_t)buf | len) & 3;
0623
0624     if (force_8bit || (alignment & 1))
0625         iowrite8_rep(info->current_cs, buf, len);
0626     else if (alignment & 3)
0627         iowrite16_rep(info->current_cs, buf, len >> 1);
0628     else
0629         iowrite32_rep(info->current_cs, buf, len >> 2);
0630 }
0631
0632 static int davinci_nand_exec_instr(struct davinci_nand_info *info,
0633                    const struct nand_op_instr *instr)
0634 {
0635     unsigned int i, timeout_us;
0636     u32 status;
0637     int ret;
0638
0639     switch (instr->type) {
0640     case NAND_OP_CMD_INSTR:
0641         iowrite8(instr->ctx.cmd.opcode,
0642              info->current_cs + info->mask_cle);
0643         break;
0644
0645     case NAND_OP_ADDR_INSTR:
0646         for (i = 0; i < instr->ctx.addr.naddrs; i++) {
0647             iowrite8(instr->ctx.addr.addrs[i],
0648                  info->current_cs + info->mask_ale);
0649         }
0650         break;
0651
0652     case NAND_OP_DATA_IN_INSTR:
0653         nand_davinci_data_in(info, instr->ctx.data.buf.in,
0654                      instr->ctx.data.len,
0655                      instr->ctx.data.force_8bit);
0656         break;
0657
0658     case NAND_OP_DATA_OUT_INSTR:
0659         nand_davinci_data_out(info, instr->ctx.data.buf.out,
0660                       instr->ctx.data.len,
0661                       instr->ctx.data.force_8bit);
0662         break;
0663
0664     case NAND_OP_WAITRDY_INSTR:
0665         timeout_us = instr->ctx.waitrdy.timeout_ms * 1000;
0666         ret = readl_relaxed_poll_timeout(info->base + NANDFSR_OFFSET,
0667                          status, status & BIT(0), 100,
0668                          timeout_us);
0669         if (ret)
0670             return ret;
0671
0672         break;
0673     }
0674
0675     if (instr->delay_ns)
0676         ndelay(instr->delay_ns);
0677
0678     return 0;
0679 }
0680
0681 static int davinci_nand_exec_op(struct nand_chip *chip,
0682                 const struct nand_operation *op,
0683                 bool check_only)
0684 {
0685     struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
0686     unsigned int i;
0687
0688     if (check_only)
0689         return 0;
0690
0691     info->current_cs = info->vaddr + (op->cs * info->mask_chipsel);
0692
0693     for (i = 0; i < op->ninstrs; i++) {
0694         int ret;
0695
0696         ret = davinci_nand_exec_instr(info, &op->instrs[i]);
0697         if (ret)
0698             return ret;
0699     }
0700
0701     return 0;
0702 }
0703
0704 static const struct nand_controller_ops davinci_nand_controller_ops = {
0705     .attach_chip = davinci_nand_attach_chip,
0706     .exec_op = davinci_nand_exec_op,
0707 };
0708
0709 static int nand_davinci_probe(struct platform_device *pdev)
0710 {
0711     struct davinci_nand_pdata   *pdata;
0712     struct davinci_nand_info    *info;
0713     struct resource         *res1;
0714     struct resource         *res2;
0715     void __iomem            *vaddr;
0716     void __iomem            *base;
0717     int             ret;
0718     uint32_t            val;
0719     struct mtd_info         *mtd;
0720
0721     pdata = nand_davinci_get_pdata(pdev);
0722     if (IS_ERR(pdata))
0723         return PTR_ERR(pdata);
0724
0725     /* insist on board-specific configuration */
0726     if (!pdata)
0727         return -ENODEV;
0728
0729     /* which external chipselect will we be managing? */
0730     if (pdata->core_chipsel > 3)
0731         return -ENODEV;
0732
0733     info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
0734     if (!info)
0735         return -ENOMEM;
0736
0737     platform_set_drvdata(pdev, info);
0738
0739     res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0740     res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0741     if (!res1 || !res2) {
0742         dev_err(&pdev->dev, "resource missing\n");
0743         return -EINVAL;
0744     }
0745
0746     vaddr = devm_ioremap_resource(&pdev->dev, res1);
0747     if (IS_ERR(vaddr))
0748         return PTR_ERR(vaddr);
0749
0750     /*
0751      * This registers range is used to setup NAND settings. In case with
0752      * TI AEMIF driver, the same memory address range is requested already
0753      * by AEMIF, so we cannot request it twice, just ioremap.
0754      * The AEMIF and NAND drivers not use the same registers in this range.
0755      */
0756     base = devm_ioremap(&pdev->dev, res2->start, resource_size(res2));
0757     if (!base) {
0758         dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res2);
0759         return -EADDRNOTAVAIL;
0760     }
0761
0762     info->pdev      = pdev;
0763     info->base      = base;
0764     info->vaddr     = vaddr;
0765
0766     mtd         = nand_to_mtd(&info->chip);
0767     mtd->dev.parent     = &pdev->dev;
0768     nand_set_flash_node(&info->chip, pdev->dev.of_node);
0769
0770     /* options such as NAND_BBT_USE_FLASH */
0771     info->chip.bbt_options  = pdata->bbt_options;
0772     /* options such as 16-bit widths */
0773     info->chip.options  = pdata->options;
0774     info->chip.bbt_td   = pdata->bbt_td;
0775     info->chip.bbt_md   = pdata->bbt_md;
0776     info->timing        = pdata->timing;
0777
0778     info->current_cs    = info->vaddr;
0779     info->core_chipsel  = pdata->core_chipsel;
0780     info->mask_chipsel  = pdata->mask_chipsel;
0781
0782     /* use nandboot-capable ALE/CLE masks by default */
0783     info->mask_ale      = pdata->mask_ale ? : MASK_ALE;
0784     info->mask_cle      = pdata->mask_cle ? : MASK_CLE;
0785
0786     spin_lock_irq(&davinci_nand_lock);
0787
0788     /* put CSxNAND into NAND mode */
0789     val = davinci_nand_readl(info, NANDFCR_OFFSET);
0790     val |= BIT(info->core_chipsel);
0791     davinci_nand_writel(info, NANDFCR_OFFSET, val);
0792
0793     spin_unlock_irq(&davinci_nand_lock);
0794
0795     /* Scan to find existence of the device(s) */
0796     nand_controller_init(&info->controller);
0797     info->controller.ops = &davinci_nand_controller_ops;
0798     info->chip.controller = &info->controller;
0799     ret = nand_scan(&info->chip, pdata->mask_chipsel ? 2 : 1);
0800     if (ret < 0) {
0801         dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
0802         return ret;
0803     }
0804
0805     if (pdata->parts)
0806         ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
0807     else
0808         ret = mtd_device_register(mtd, NULL, 0);
0809     if (ret < 0)
0810         goto err_cleanup_nand;
0811
0812     val = davinci_nand_readl(info, NRCSR_OFFSET);
0813     dev_info(&pdev->dev, "controller rev. %d.%d\n",
0814            (val >> 8) & 0xff, val & 0xff);
0815
0816     return 0;
0817
0818 err_cleanup_nand:
0819     nand_cleanup(&info->chip);
0820
0821     return ret;
0822 }
0823
0824 static int nand_davinci_remove(struct platform_device *pdev)
0825 {
0826     struct davinci_nand_info *info = platform_get_drvdata(pdev);
0827     struct nand_chip *chip = &info->chip;
0828     int ret;
0829
0830     spin_lock_irq(&davinci_nand_lock);
0831     if (chip->ecc.placement == NAND_ECC_PLACEMENT_INTERLEAVED)
0832         ecc4_busy = false;
0833     spin_unlock_irq(&davinci_nand_lock);
0834
0835     ret = mtd_device_unregister(nand_to_mtd(chip));
0836     WARN_ON(ret);
0837     nand_cleanup(chip);
0838
0839     return 0;
0840 }
0841
0842 static struct platform_driver nand_davinci_driver = {
0843     .probe      = nand_davinci_probe,
0844     .remove     = nand_davinci_remove,
0845     .driver     = {
0846         .name   = "davinci_nand",
0847         .of_match_table = of_match_ptr(davinci_nand_of_match),
0848     },
0849 };
0850 MODULE_ALIAS("platform:davinci_nand");
0851
0852 module_platform_driver(nand_davinci_driver);
0853
0854 MODULE_LICENSE("GPL");
0855 MODULE_AUTHOR("Texas Instruments");
0856 MODULE_DESCRIPTION("Davinci NAND flash driver");
0857