nand/raw/cs553x_nand.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * (C) 2005, 2006 Red Hat Inc.
0004  *
0005  * Author: David Woodhouse <dwmw2@infradead.org>
0006  *     Tom Sylla <tom.sylla@amd.com>
0007  *
0008  *  Overview:
0009  *   This is a device driver for the NAND flash controller found on
0010  *   the AMD CS5535/CS5536 companion chipsets for the Geode processor.
0011  *   mtd-id for command line partitioning is cs553x_nand_cs[0-3]
0012  *   where 0-3 reflects the chip select for NAND.
0013  */
0014
0015 #include <linux/kernel.h>
0016 #include <linux/slab.h>
0017 #include <linux/init.h>
0018 #include <linux/module.h>
0019 #include <linux/delay.h>
0020 #include <linux/mtd/mtd.h>
0021 #include <linux/mtd/rawnand.h>
0022 #include <linux/mtd/partitions.h>
0023 #include <linux/iopoll.h>
0024
0025 #include <asm/msr.h>
0026
0027 #define NR_CS553X_CONTROLLERS   4
0028
0029 #define MSR_DIVIL_GLD_CAP   0x51400000  /* DIVIL capabilitiies */
0030 #define CAP_CS5535      0x2df000ULL
0031 #define CAP_CS5536      0x5df500ULL
0032
0033 /* NAND Timing MSRs */
0034 #define MSR_NANDF_DATA      0x5140001b  /* NAND Flash Data Timing MSR */
0035 #define MSR_NANDF_CTL       0x5140001c  /* NAND Flash Control Timing */
0036 #define MSR_NANDF_RSVD      0x5140001d  /* Reserved */
0037
0038 /* NAND BAR MSRs */
0039 #define MSR_DIVIL_LBAR_FLSH0    0x51400010  /* Flash Chip Select 0 */
0040 #define MSR_DIVIL_LBAR_FLSH1    0x51400011  /* Flash Chip Select 1 */
0041 #define MSR_DIVIL_LBAR_FLSH2    0x51400012  /* Flash Chip Select 2 */
0042 #define MSR_DIVIL_LBAR_FLSH3    0x51400013  /* Flash Chip Select 3 */
0043     /* Each made up of... */
0044 #define FLSH_LBAR_EN        (1ULL<<32)
0045 #define FLSH_NOR_NAND       (1ULL<<33)  /* 1 for NAND */
0046 #define FLSH_MEM_IO     (1ULL<<34)  /* 1 for MMIO */
0047     /* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */
0048     /* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */
0049
0050 /* Pin function selection MSR (IDE vs. flash on the IDE pins) */
0051 #define MSR_DIVIL_BALL_OPTS 0x51400015
0052 #define PIN_OPT_IDE     (1<<0)  /* 0 for flash, 1 for IDE */
0053
0054 /* Registers within the NAND flash controller BAR -- memory mapped */
0055 #define MM_NAND_DATA        0x00    /* 0 to 0x7ff, in fact */
0056 #define MM_NAND_CTL     0x800   /* Any even address 0x800-0x80e */
0057 #define MM_NAND_IO      0x801   /* Any odd address 0x801-0x80f */
0058 #define MM_NAND_STS     0x810
0059 #define MM_NAND_ECC_LSB     0x811
0060 #define MM_NAND_ECC_MSB     0x812
0061 #define MM_NAND_ECC_COL     0x813
0062 #define MM_NAND_LAC     0x814
0063 #define MM_NAND_ECC_CTL     0x815
0064
0065 /* Registers within the NAND flash controller BAR -- I/O mapped */
0066 #define IO_NAND_DATA        0x00    /* 0 to 3, in fact */
0067 #define IO_NAND_CTL     0x04
0068 #define IO_NAND_IO      0x05
0069 #define IO_NAND_STS     0x06
0070 #define IO_NAND_ECC_CTL     0x08
0071 #define IO_NAND_ECC_LSB     0x09
0072 #define IO_NAND_ECC_MSB     0x0a
0073 #define IO_NAND_ECC_COL     0x0b
0074 #define IO_NAND_LAC     0x0c
0075
0076 #define CS_NAND_CTL_DIST_EN (1<<4)  /* Enable NAND Distract interrupt */
0077 #define CS_NAND_CTL_RDY_INT_MASK    (1<<3)  /* Enable RDY/BUSY# interrupt */
0078 #define CS_NAND_CTL_ALE     (1<<2)
0079 #define CS_NAND_CTL_CLE     (1<<1)
0080 #define CS_NAND_CTL_CE      (1<<0)  /* Keep low; 1 to reset */
0081
0082 #define CS_NAND_STS_FLASH_RDY   (1<<3)
0083 #define CS_NAND_CTLR_BUSY   (1<<2)
0084 #define CS_NAND_CMD_COMP    (1<<1)
0085 #define CS_NAND_DIST_ST     (1<<0)
0086
0087 #define CS_NAND_ECC_PARITY  (1<<2)
0088 #define CS_NAND_ECC_CLRECC  (1<<1)
0089 #define CS_NAND_ECC_ENECC   (1<<0)
0090
0091 struct cs553x_nand_controller {
0092     struct nand_controller base;
0093     struct nand_chip chip;
0094     void __iomem *mmio;
0095 };
0096
0097 static struct cs553x_nand_controller *
0098 to_cs553x(struct nand_controller *controller)
0099 {
0100     return container_of(controller, struct cs553x_nand_controller, base);
0101 }
0102
0103 static int cs553x_write_ctrl_byte(struct cs553x_nand_controller *cs553x,
0104                   u32 ctl, u8 data)
0105 {
0106     u8 status;
0107
0108     writeb(ctl, cs553x->mmio + MM_NAND_CTL);
0109     writeb(data, cs553x->mmio + MM_NAND_IO);
0110     return readb_poll_timeout_atomic(cs553x->mmio + MM_NAND_STS, status,
0111                     !(status & CS_NAND_CTLR_BUSY), 1,
0112                     100000);
0113 }
0114
0115 static void cs553x_data_in(struct cs553x_nand_controller *cs553x, void *buf,
0116                unsigned int len)
0117 {
0118     writeb(0, cs553x->mmio + MM_NAND_CTL);
0119     while (unlikely(len > 0x800)) {
0120         memcpy_fromio(buf, cs553x->mmio, 0x800);
0121         buf += 0x800;
0122         len -= 0x800;
0123     }
0124     memcpy_fromio(buf, cs553x->mmio, len);
0125 }
0126
0127 static void cs553x_data_out(struct cs553x_nand_controller *cs553x,
0128                 const void *buf, unsigned int len)
0129 {
0130     writeb(0, cs553x->mmio + MM_NAND_CTL);
0131     while (unlikely(len > 0x800)) {
0132         memcpy_toio(cs553x->mmio, buf, 0x800);
0133         buf += 0x800;
0134         len -= 0x800;
0135     }
0136     memcpy_toio(cs553x->mmio, buf, len);
0137 }
0138
0139 static int cs553x_wait_ready(struct cs553x_nand_controller *cs553x,
0140                  unsigned int timeout_ms)
0141 {
0142     u8 mask = CS_NAND_CTLR_BUSY | CS_NAND_STS_FLASH_RDY;
0143     u8 status;
0144
0145     return readb_poll_timeout(cs553x->mmio + MM_NAND_STS, status,
0146                   (status & mask) == CS_NAND_STS_FLASH_RDY, 100,
0147                   timeout_ms * 1000);
0148 }
0149
0150 static int cs553x_exec_instr(struct cs553x_nand_controller *cs553x,
0151                  const struct nand_op_instr *instr)
0152 {
0153     unsigned int i;
0154     int ret = 0;
0155
0156     switch (instr->type) {
0157     case NAND_OP_CMD_INSTR:
0158         ret = cs553x_write_ctrl_byte(cs553x, CS_NAND_CTL_CLE,
0159                          instr->ctx.cmd.opcode);
0160         break;
0161
0162     case NAND_OP_ADDR_INSTR:
0163         for (i = 0; i < instr->ctx.addr.naddrs; i++) {
0164             ret = cs553x_write_ctrl_byte(cs553x, CS_NAND_CTL_ALE,
0165                              instr->ctx.addr.addrs[i]);
0166             if (ret)
0167                 break;
0168         }
0169         break;
0170
0171     case NAND_OP_DATA_IN_INSTR:
0172         cs553x_data_in(cs553x, instr->ctx.data.buf.in,
0173                    instr->ctx.data.len);
0174         break;
0175
0176     case NAND_OP_DATA_OUT_INSTR:
0177         cs553x_data_out(cs553x, instr->ctx.data.buf.out,
0178                 instr->ctx.data.len);
0179         break;
0180
0181     case NAND_OP_WAITRDY_INSTR:
0182         ret = cs553x_wait_ready(cs553x, instr->ctx.waitrdy.timeout_ms);
0183         break;
0184     }
0185
0186     if (instr->delay_ns)
0187         ndelay(instr->delay_ns);
0188
0189     return ret;
0190 }
0191
0192 static int cs553x_exec_op(struct nand_chip *this,
0193               const struct nand_operation *op,
0194               bool check_only)
0195 {
0196     struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);
0197     unsigned int i;
0198     int ret;
0199
0200     if (check_only)
0201         return true;
0202
0203     /* De-assert the CE pin */
0204     writeb(0, cs553x->mmio + MM_NAND_CTL);
0205     for (i = 0; i < op->ninstrs; i++) {
0206         ret = cs553x_exec_instr(cs553x, &op->instrs[i]);
0207         if (ret)
0208             break;
0209     }
0210
0211     /* Re-assert the CE pin. */
0212     writeb(CS_NAND_CTL_CE, cs553x->mmio + MM_NAND_CTL);
0213
0214     return ret;
0215 }
0216
0217 static void cs_enable_hwecc(struct nand_chip *this, int mode)
0218 {
0219     struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);
0220
0221     writeb(0x07, cs553x->mmio + MM_NAND_ECC_CTL);
0222 }
0223
0224 static int cs_calculate_ecc(struct nand_chip *this, const u_char *dat,
0225                 u_char *ecc_code)
0226 {
0227     struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);
0228     uint32_t ecc;
0229
0230     ecc = readl(cs553x->mmio + MM_NAND_STS);
0231
0232     ecc_code[1] = ecc >> 8;
0233     ecc_code[0] = ecc >> 16;
0234     ecc_code[2] = ecc >> 24;
0235     return 0;
0236 }
0237
0238 static struct cs553x_nand_controller *controllers[4];
0239
0240 static int cs553x_attach_chip(struct nand_chip *chip)
0241 {
0242     if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
0243         return 0;
0244
0245     chip->ecc.size = 256;
0246     chip->ecc.bytes = 3;
0247     chip->ecc.hwctl  = cs_enable_hwecc;
0248     chip->ecc.calculate = cs_calculate_ecc;
0249     chip->ecc.correct  = rawnand_sw_hamming_correct;
0250     chip->ecc.strength = 1;
0251
0252     return 0;
0253 }
0254
0255 static const struct nand_controller_ops cs553x_nand_controller_ops = {
0256     .exec_op = cs553x_exec_op,
0257     .attach_chip = cs553x_attach_chip,
0258 };
0259
0260 static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
0261 {
0262     struct cs553x_nand_controller *controller;
0263     int err = 0;
0264     struct nand_chip *this;
0265     struct mtd_info *new_mtd;
0266
0267     pr_notice("Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n",
0268           cs, mmio ? "MM" : "P", adr);
0269
0270     if (!mmio) {
0271         pr_notice("PIO mode not yet implemented for CS553X NAND controller\n");
0272         return -ENXIO;
0273     }
0274
0275     /* Allocate memory for MTD device structure and private data */
0276     controller = kzalloc(sizeof(*controller), GFP_KERNEL);
0277     if (!controller) {
0278         err = -ENOMEM;
0279         goto out;
0280     }
0281
0282     this = &controller->chip;
0283     nand_controller_init(&controller->base);
0284     controller->base.ops = &cs553x_nand_controller_ops;
0285     this->controller = &controller->base;
0286     new_mtd = nand_to_mtd(this);
0287
0288     /* Link the private data with the MTD structure */
0289     new_mtd->owner = THIS_MODULE;
0290
0291     /* map physical address */
0292     controller->mmio = ioremap(adr, 4096);
0293     if (!controller->mmio) {
0294         pr_warn("ioremap cs553x NAND @0x%08lx failed\n", adr);
0295         err = -EIO;
0296         goto out_mtd;
0297     }
0298
0299     /* Enable the following for a flash based bad block table */
0300     this->bbt_options = NAND_BBT_USE_FLASH;
0301
0302     new_mtd->name = kasprintf(GFP_KERNEL, "cs553x_nand_cs%d", cs);
0303     if (!new_mtd->name) {
0304         err = -ENOMEM;
0305         goto out_ior;
0306     }
0307
0308     /* Scan to find existence of the device */
0309     err = nand_scan(this, 1);
0310     if (err)
0311         goto out_free;
0312
0313     controllers[cs] = controller;
0314     goto out;
0315
0316 out_free:
0317     kfree(new_mtd->name);
0318 out_ior:
0319     iounmap(controller->mmio);
0320 out_mtd:
0321     kfree(controller);
0322 out:
0323     return err;
0324 }
0325
0326 static int is_geode(void)
0327 {
0328     /* These are the CPUs which will have a CS553[56] companion chip */
0329     if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
0330         boot_cpu_data.x86 == 5 &&
0331         boot_cpu_data.x86_model == 10)
0332         return 1; /* Geode LX */
0333
0334     if ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC ||
0335          boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX) &&
0336         boot_cpu_data.x86 == 5 &&
0337         boot_cpu_data.x86_model == 5)
0338         return 1; /* Geode GX (née GX2) */
0339
0340     return 0;
0341 }
0342
0343 static int __init cs553x_init(void)
0344 {
0345     int err = -ENXIO;
0346     int i;
0347     uint64_t val;
0348
0349     /* If the CPU isn't a Geode GX or LX, abort */
0350     if (!is_geode())
0351         return -ENXIO;
0352
0353     /* If it doesn't have the CS553[56], abort */
0354     rdmsrl(MSR_DIVIL_GLD_CAP, val);
0355     val &= ~0xFFULL;
0356     if (val != CAP_CS5535 && val != CAP_CS5536)
0357         return -ENXIO;
0358
0359     /* If it doesn't have the NAND controller enabled, abort */
0360     rdmsrl(MSR_DIVIL_BALL_OPTS, val);
0361     if (val & PIN_OPT_IDE) {
0362         pr_info("CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
0363         return -ENXIO;
0364     }
0365
0366     for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
0367         rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val);
0368
0369         if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))
0370             err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
0371     }
0372
0373     /* Register all devices together here. This means we can easily hack it to
0374        do mtdconcat etc. if we want to. */
0375     for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
0376         if (controllers[i]) {
0377             /* If any devices registered, return success. Else the last error. */
0378             mtd_device_register(nand_to_mtd(&controllers[i]->chip),
0379                         NULL, 0);
0380             err = 0;
0381         }
0382     }
0383
0384     return err;
0385 }
0386
0387 module_init(cs553x_init);
0388
0389 static void __exit cs553x_cleanup(void)
0390 {
0391     int i;
0392
0393     for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
0394         struct cs553x_nand_controller *controller = controllers[i];
0395         struct nand_chip *this = &controller->chip;
0396         struct mtd_info *mtd = nand_to_mtd(this);
0397         int ret;
0398
0399         if (!mtd)
0400             continue;
0401
0402         /* Release resources, unregister device */
0403         ret = mtd_device_unregister(mtd);
0404         WARN_ON(ret);
0405         nand_cleanup(this);
0406         kfree(mtd->name);
0407         controllers[i] = NULL;
0408
0409         /* unmap physical address */
0410         iounmap(controller->mmio);
0411
0412         /* Free the MTD device structure */
0413         kfree(controller);
0414     }
0415 }
0416
0417 module_exit(cs553x_cleanup);
0418
0419 MODULE_LICENSE("GPL");
0420 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
0421 MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");