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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
0004  *
0005  * The data sheet for this device can be found at:
0006  *    http://wiki.laptop.org/go/Datasheets 
0007  *
0008  * Copyright © 2006 Red Hat, Inc.
0009  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
0010  */
0011 
0012 #define DEBUG
0013 
0014 #include <linux/device.h>
0015 #undef DEBUG
0016 #include <linux/mtd/mtd.h>
0017 #include <linux/mtd/rawnand.h>
0018 #include <linux/mtd/partitions.h>
0019 #include <linux/rslib.h>
0020 #include <linux/pci.h>
0021 #include <linux/delay.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/dma-mapping.h>
0024 #include <linux/slab.h>
0025 #include <linux/module.h>
0026 #include <asm/io.h>
0027 
0028 #define CAFE_NAND_CTRL1     0x00
0029 #define CAFE_NAND_CTRL2     0x04
0030 #define CAFE_NAND_CTRL3     0x08
0031 #define CAFE_NAND_STATUS    0x0c
0032 #define CAFE_NAND_IRQ       0x10
0033 #define CAFE_NAND_IRQ_MASK  0x14
0034 #define CAFE_NAND_DATA_LEN  0x18
0035 #define CAFE_NAND_ADDR1     0x1c
0036 #define CAFE_NAND_ADDR2     0x20
0037 #define CAFE_NAND_TIMING1   0x24
0038 #define CAFE_NAND_TIMING2   0x28
0039 #define CAFE_NAND_TIMING3   0x2c
0040 #define CAFE_NAND_NONMEM    0x30
0041 #define CAFE_NAND_ECC_RESULT    0x3C
0042 #define CAFE_NAND_DMA_CTRL  0x40
0043 #define CAFE_NAND_DMA_ADDR0 0x44
0044 #define CAFE_NAND_DMA_ADDR1 0x48
0045 #define CAFE_NAND_ECC_SYN01 0x50
0046 #define CAFE_NAND_ECC_SYN23 0x54
0047 #define CAFE_NAND_ECC_SYN45 0x58
0048 #define CAFE_NAND_ECC_SYN67 0x5c
0049 #define CAFE_NAND_READ_DATA 0x1000
0050 #define CAFE_NAND_WRITE_DATA    0x2000
0051 
0052 #define CAFE_GLOBAL_CTRL    0x3004
0053 #define CAFE_GLOBAL_IRQ     0x3008
0054 #define CAFE_GLOBAL_IRQ_MASK    0x300c
0055 #define CAFE_NAND_RESET     0x3034
0056 
0057 /* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */
0058 #define CTRL1_CHIPSELECT    (1<<19)
0059 
0060 struct cafe_priv {
0061     struct nand_chip nand;
0062     struct pci_dev *pdev;
0063     void __iomem *mmio;
0064     struct rs_control *rs;
0065     uint32_t ctl1;
0066     uint32_t ctl2;
0067     int datalen;
0068     int nr_data;
0069     int data_pos;
0070     int page_addr;
0071     bool usedma;
0072     dma_addr_t dmaaddr;
0073     unsigned char *dmabuf;
0074 };
0075 
0076 static int usedma = 1;
0077 module_param(usedma, int, 0644);
0078 
0079 static int skipbbt = 0;
0080 module_param(skipbbt, int, 0644);
0081 
0082 static int debug = 0;
0083 module_param(debug, int, 0644);
0084 
0085 static int regdebug = 0;
0086 module_param(regdebug, int, 0644);
0087 
0088 static int checkecc = 1;
0089 module_param(checkecc, int, 0644);
0090 
0091 static unsigned int numtimings;
0092 static int timing[3];
0093 module_param_array(timing, int, &numtimings, 0644);
0094 
0095 static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
0096 
0097 /* Hrm. Why isn't this already conditional on something in the struct device? */
0098 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
0099 
0100 /* Make it easier to switch to PIO if we need to */
0101 #define cafe_readl(cafe, addr)          readl((cafe)->mmio + CAFE_##addr)
0102 #define cafe_writel(cafe, datum, addr)      writel(datum, (cafe)->mmio + CAFE_##addr)
0103 
0104 static int cafe_device_ready(struct nand_chip *chip)
0105 {
0106     struct cafe_priv *cafe = nand_get_controller_data(chip);
0107     int result = !!(cafe_readl(cafe, NAND_STATUS) & 0x40000000);
0108     uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
0109 
0110     cafe_writel(cafe, irqs, NAND_IRQ);
0111 
0112     cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
0113         result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
0114         cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
0115 
0116     return result;
0117 }
0118 
0119 
0120 static void cafe_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
0121 {
0122     struct cafe_priv *cafe = nand_get_controller_data(chip);
0123 
0124     if (cafe->usedma)
0125         memcpy(cafe->dmabuf + cafe->datalen, buf, len);
0126     else
0127         memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
0128 
0129     cafe->datalen += len;
0130 
0131     cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
0132         len, cafe->datalen);
0133 }
0134 
0135 static void cafe_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
0136 {
0137     struct cafe_priv *cafe = nand_get_controller_data(chip);
0138 
0139     if (cafe->usedma)
0140         memcpy(buf, cafe->dmabuf + cafe->datalen, len);
0141     else
0142         memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
0143 
0144     cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
0145           len, cafe->datalen);
0146     cafe->datalen += len;
0147 }
0148 
0149 static uint8_t cafe_read_byte(struct nand_chip *chip)
0150 {
0151     struct cafe_priv *cafe = nand_get_controller_data(chip);
0152     uint8_t d;
0153 
0154     cafe_read_buf(chip, &d, 1);
0155     cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
0156 
0157     return d;
0158 }
0159 
0160 static void cafe_nand_cmdfunc(struct nand_chip *chip, unsigned command,
0161                   int column, int page_addr)
0162 {
0163     struct mtd_info *mtd = nand_to_mtd(chip);
0164     struct cafe_priv *cafe = nand_get_controller_data(chip);
0165     int adrbytes = 0;
0166     uint32_t ctl1;
0167     uint32_t doneint = 0x80000000;
0168 
0169     cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
0170         command, column, page_addr);
0171 
0172     if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
0173         /* Second half of a command we already calculated */
0174         cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
0175         ctl1 = cafe->ctl1;
0176         cafe->ctl2 &= ~(1<<30);
0177         cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
0178               cafe->ctl1, cafe->nr_data);
0179         goto do_command;
0180     }
0181     /* Reset ECC engine */
0182     cafe_writel(cafe, 0, NAND_CTRL2);
0183 
0184     /* Emulate NAND_CMD_READOOB on large-page chips */
0185     if (mtd->writesize > 512 &&
0186         command == NAND_CMD_READOOB) {
0187         column += mtd->writesize;
0188         command = NAND_CMD_READ0;
0189     }
0190 
0191     /* FIXME: Do we need to send read command before sending data
0192        for small-page chips, to position the buffer correctly? */
0193 
0194     if (column != -1) {
0195         cafe_writel(cafe, column, NAND_ADDR1);
0196         adrbytes = 2;
0197         if (page_addr != -1)
0198             goto write_adr2;
0199     } else if (page_addr != -1) {
0200         cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
0201         page_addr >>= 16;
0202     write_adr2:
0203         cafe_writel(cafe, page_addr, NAND_ADDR2);
0204         adrbytes += 2;
0205         if (mtd->size > mtd->writesize << 16)
0206             adrbytes++;
0207     }
0208 
0209     cafe->data_pos = cafe->datalen = 0;
0210 
0211     /* Set command valid bit, mask in the chip select bit  */
0212     ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
0213 
0214     /* Set RD or WR bits as appropriate */
0215     if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
0216         ctl1 |= (1<<26); /* rd */
0217         /* Always 5 bytes, for now */
0218         cafe->datalen = 4;
0219         /* And one address cycle -- even for STATUS, since the controller doesn't work without */
0220         adrbytes = 1;
0221     } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
0222            command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
0223         ctl1 |= 1<<26; /* rd */
0224         /* For now, assume just read to end of page */
0225         cafe->datalen = mtd->writesize + mtd->oobsize - column;
0226     } else if (command == NAND_CMD_SEQIN)
0227         ctl1 |= 1<<25; /* wr */
0228 
0229     /* Set number of address bytes */
0230     if (adrbytes)
0231         ctl1 |= ((adrbytes-1)|8) << 27;
0232 
0233     if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
0234         /* Ignore the first command of a pair; the hardware
0235            deals with them both at once, later */
0236         cafe->ctl1 = ctl1;
0237         cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
0238               cafe->ctl1, cafe->datalen);
0239         return;
0240     }
0241     /* RNDOUT and READ0 commands need a following byte */
0242     if (command == NAND_CMD_RNDOUT)
0243         cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
0244     else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
0245         cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
0246 
0247  do_command:
0248     cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
0249         cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
0250 
0251     /* NB: The datasheet lies -- we really should be subtracting 1 here */
0252     cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
0253     cafe_writel(cafe, 0x90000000, NAND_IRQ);
0254     if (cafe->usedma && (ctl1 & (3<<25))) {
0255         uint32_t dmactl = 0xc0000000 + cafe->datalen;
0256         /* If WR or RD bits set, set up DMA */
0257         if (ctl1 & (1<<26)) {
0258             /* It's a read */
0259             dmactl |= (1<<29);
0260             /* ... so it's done when the DMA is done, not just
0261                the command. */
0262             doneint = 0x10000000;
0263         }
0264         cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
0265     }
0266     cafe->datalen = 0;
0267 
0268     if (unlikely(regdebug)) {
0269         int i;
0270         printk("About to write command %08x to register 0\n", ctl1);
0271         for (i=4; i< 0x5c; i+=4)
0272             printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
0273     }
0274 
0275     cafe_writel(cafe, ctl1, NAND_CTRL1);
0276     /* Apply this short delay always to ensure that we do wait tWB in
0277      * any case on any machine. */
0278     ndelay(100);
0279 
0280     if (1) {
0281         int c;
0282         uint32_t irqs;
0283 
0284         for (c = 500000; c != 0; c--) {
0285             irqs = cafe_readl(cafe, NAND_IRQ);
0286             if (irqs & doneint)
0287                 break;
0288             udelay(1);
0289             if (!(c % 100000))
0290                 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
0291             cpu_relax();
0292         }
0293         cafe_writel(cafe, doneint, NAND_IRQ);
0294         cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
0295                  command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
0296     }
0297 
0298     WARN_ON(cafe->ctl2 & (1<<30));
0299 
0300     switch (command) {
0301 
0302     case NAND_CMD_CACHEDPROG:
0303     case NAND_CMD_PAGEPROG:
0304     case NAND_CMD_ERASE1:
0305     case NAND_CMD_ERASE2:
0306     case NAND_CMD_SEQIN:
0307     case NAND_CMD_RNDIN:
0308     case NAND_CMD_STATUS:
0309     case NAND_CMD_RNDOUT:
0310         cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
0311         return;
0312     }
0313     nand_wait_ready(chip);
0314     cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
0315 }
0316 
0317 static void cafe_select_chip(struct nand_chip *chip, int chipnr)
0318 {
0319     struct cafe_priv *cafe = nand_get_controller_data(chip);
0320 
0321     cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
0322 
0323     /* Mask the appropriate bit into the stored value of ctl1
0324        which will be used by cafe_nand_cmdfunc() */
0325     if (chipnr)
0326         cafe->ctl1 |= CTRL1_CHIPSELECT;
0327     else
0328         cafe->ctl1 &= ~CTRL1_CHIPSELECT;
0329 }
0330 
0331 static irqreturn_t cafe_nand_interrupt(int irq, void *id)
0332 {
0333     struct mtd_info *mtd = id;
0334     struct nand_chip *chip = mtd_to_nand(mtd);
0335     struct cafe_priv *cafe = nand_get_controller_data(chip);
0336     uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
0337     cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
0338     if (!irqs)
0339         return IRQ_NONE;
0340 
0341     cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
0342     return IRQ_HANDLED;
0343 }
0344 
0345 static int cafe_nand_write_oob(struct nand_chip *chip, int page)
0346 {
0347     struct mtd_info *mtd = nand_to_mtd(chip);
0348 
0349     return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
0350                  mtd->oobsize);
0351 }
0352 
0353 /* Don't use -- use nand_read_oob_std for now */
0354 static int cafe_nand_read_oob(struct nand_chip *chip, int page)
0355 {
0356     struct mtd_info *mtd = nand_to_mtd(chip);
0357 
0358     return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
0359 }
0360 /**
0361  * cafe_nand_read_page_syndrome - [REPLACEABLE] hardware ecc syndrome based page read
0362  * @chip:   nand chip info structure
0363  * @buf:    buffer to store read data
0364  * @oob_required:   caller expects OOB data read to chip->oob_poi
0365  * @page:   page number to read
0366  *
0367  * The hw generator calculates the error syndrome automatically. Therefore
0368  * we need a special oob layout and handling.
0369  */
0370 static int cafe_nand_read_page(struct nand_chip *chip, uint8_t *buf,
0371                    int oob_required, int page)
0372 {
0373     struct mtd_info *mtd = nand_to_mtd(chip);
0374     struct cafe_priv *cafe = nand_get_controller_data(chip);
0375     unsigned int max_bitflips = 0;
0376 
0377     cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
0378              cafe_readl(cafe, NAND_ECC_RESULT),
0379              cafe_readl(cafe, NAND_ECC_SYN01));
0380 
0381     nand_read_page_op(chip, page, 0, buf, mtd->writesize);
0382     chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
0383 
0384     if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
0385         unsigned short syn[8], pat[4];
0386         int pos[4];
0387         u8 *oob = chip->oob_poi;
0388         int i, n;
0389 
0390         for (i=0; i<8; i+=2) {
0391             uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
0392 
0393             syn[i] = cafe->rs->codec->index_of[tmp & 0xfff];
0394             syn[i+1] = cafe->rs->codec->index_of[(tmp >> 16) & 0xfff];
0395         }
0396 
0397         n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
0398                 pat);
0399 
0400         for (i = 0; i < n; i++) {
0401             int p = pos[i];
0402 
0403             /* The 12-bit symbols are mapped to bytes here */
0404 
0405             if (p > 1374) {
0406                 /* out of range */
0407                 n = -1374;
0408             } else if (p == 0) {
0409                 /* high four bits do not correspond to data */
0410                 if (pat[i] > 0xff)
0411                     n = -2048;
0412                 else
0413                     buf[0] ^= pat[i];
0414             } else if (p == 1365) {
0415                 buf[2047] ^= pat[i] >> 4;
0416                 oob[0] ^= pat[i] << 4;
0417             } else if (p > 1365) {
0418                 if ((p & 1) == 1) {
0419                     oob[3*p/2 - 2048] ^= pat[i] >> 4;
0420                     oob[3*p/2 - 2047] ^= pat[i] << 4;
0421                 } else {
0422                     oob[3*p/2 - 2049] ^= pat[i] >> 8;
0423                     oob[3*p/2 - 2048] ^= pat[i];
0424                 }
0425             } else if ((p & 1) == 1) {
0426                 buf[3*p/2] ^= pat[i] >> 4;
0427                 buf[3*p/2 + 1] ^= pat[i] << 4;
0428             } else {
0429                 buf[3*p/2 - 1] ^= pat[i] >> 8;
0430                 buf[3*p/2] ^= pat[i];
0431             }
0432         }
0433 
0434         if (n < 0) {
0435             dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
0436                 cafe_readl(cafe, NAND_ADDR2) * 2048);
0437             for (i = 0; i < 0x5c; i += 4)
0438                 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
0439             mtd->ecc_stats.failed++;
0440         } else {
0441             dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
0442             mtd->ecc_stats.corrected += n;
0443             max_bitflips = max_t(unsigned int, max_bitflips, n);
0444         }
0445     }
0446 
0447     return max_bitflips;
0448 }
0449 
0450 static int cafe_ooblayout_ecc(struct mtd_info *mtd, int section,
0451                   struct mtd_oob_region *oobregion)
0452 {
0453     struct nand_chip *chip = mtd_to_nand(mtd);
0454 
0455     if (section)
0456         return -ERANGE;
0457 
0458     oobregion->offset = 0;
0459     oobregion->length = chip->ecc.total;
0460 
0461     return 0;
0462 }
0463 
0464 static int cafe_ooblayout_free(struct mtd_info *mtd, int section,
0465                    struct mtd_oob_region *oobregion)
0466 {
0467     struct nand_chip *chip = mtd_to_nand(mtd);
0468 
0469     if (section)
0470         return -ERANGE;
0471 
0472     oobregion->offset = chip->ecc.total;
0473     oobregion->length = mtd->oobsize - chip->ecc.total;
0474 
0475     return 0;
0476 }
0477 
0478 static const struct mtd_ooblayout_ops cafe_ooblayout_ops = {
0479     .ecc = cafe_ooblayout_ecc,
0480     .free = cafe_ooblayout_free,
0481 };
0482 
0483 /* Ick. The BBT code really ought to be able to work this bit out
0484    for itself from the above, at least for the 2KiB case */
0485 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
0486 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
0487 
0488 static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
0489 static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
0490 
0491 
0492 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
0493     .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
0494         | NAND_BBT_2BIT | NAND_BBT_VERSION,
0495     .offs = 14,
0496     .len = 4,
0497     .veroffs = 18,
0498     .maxblocks = 4,
0499     .pattern = cafe_bbt_pattern_2048
0500 };
0501 
0502 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
0503     .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
0504         | NAND_BBT_2BIT | NAND_BBT_VERSION,
0505     .offs = 14,
0506     .len = 4,
0507     .veroffs = 18,
0508     .maxblocks = 4,
0509     .pattern = cafe_mirror_pattern_2048
0510 };
0511 
0512 static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
0513     .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
0514         | NAND_BBT_2BIT | NAND_BBT_VERSION,
0515     .offs = 14,
0516     .len = 1,
0517     .veroffs = 15,
0518     .maxblocks = 4,
0519     .pattern = cafe_bbt_pattern_512
0520 };
0521 
0522 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
0523     .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
0524         | NAND_BBT_2BIT | NAND_BBT_VERSION,
0525     .offs = 14,
0526     .len = 1,
0527     .veroffs = 15,
0528     .maxblocks = 4,
0529     .pattern = cafe_mirror_pattern_512
0530 };
0531 
0532 
0533 static int cafe_nand_write_page_lowlevel(struct nand_chip *chip,
0534                      const uint8_t *buf, int oob_required,
0535                      int page)
0536 {
0537     struct mtd_info *mtd = nand_to_mtd(chip);
0538     struct cafe_priv *cafe = nand_get_controller_data(chip);
0539 
0540     nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
0541     chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
0542 
0543     /* Set up ECC autogeneration */
0544     cafe->ctl2 |= (1<<30);
0545 
0546     return nand_prog_page_end_op(chip);
0547 }
0548 
0549 /* F_2[X]/(X**6+X+1)  */
0550 static unsigned short gf64_mul(u8 a, u8 b)
0551 {
0552     u8 c;
0553     unsigned int i;
0554 
0555     c = 0;
0556     for (i = 0; i < 6; i++) {
0557         if (a & 1)
0558             c ^= b;
0559         a >>= 1;
0560         b <<= 1;
0561         if ((b & 0x40) != 0)
0562             b ^= 0x43;
0563     }
0564 
0565     return c;
0566 }
0567 
0568 /* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X]  */
0569 static u16 gf4096_mul(u16 a, u16 b)
0570 {
0571     u8 ah, al, bh, bl, ch, cl;
0572 
0573     ah = a >> 6;
0574     al = a & 0x3f;
0575     bh = b >> 6;
0576     bl = b & 0x3f;
0577 
0578     ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
0579     cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
0580 
0581     return (ch << 6) ^ cl;
0582 }
0583 
0584 static int cafe_mul(int x)
0585 {
0586     if (x == 0)
0587         return 1;
0588     return gf4096_mul(x, 0xe01);
0589 }
0590 
0591 static int cafe_nand_attach_chip(struct nand_chip *chip)
0592 {
0593     struct mtd_info *mtd = nand_to_mtd(chip);
0594     struct cafe_priv *cafe = nand_get_controller_data(chip);
0595     int err = 0;
0596 
0597     cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112,
0598                       &cafe->dmaaddr, GFP_KERNEL);
0599     if (!cafe->dmabuf)
0600         return -ENOMEM;
0601 
0602     /* Set up DMA address */
0603     cafe_writel(cafe, lower_32_bits(cafe->dmaaddr), NAND_DMA_ADDR0);
0604     cafe_writel(cafe, upper_32_bits(cafe->dmaaddr), NAND_DMA_ADDR1);
0605 
0606     cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
0607              cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
0608 
0609     /* Restore the DMA flag */
0610     cafe->usedma = usedma;
0611 
0612     cafe->ctl2 = BIT(27); /* Reed-Solomon ECC */
0613     if (mtd->writesize == 2048)
0614         cafe->ctl2 |= BIT(29); /* 2KiB page size */
0615 
0616     /* Set up ECC according to the type of chip we found */
0617     mtd_set_ooblayout(mtd, &cafe_ooblayout_ops);
0618     if (mtd->writesize == 2048) {
0619         cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
0620         cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
0621     } else if (mtd->writesize == 512) {
0622         cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
0623         cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
0624     } else {
0625         dev_warn(&cafe->pdev->dev,
0626              "Unexpected NAND flash writesize %d. Aborting\n",
0627              mtd->writesize);
0628         err = -ENOTSUPP;
0629         goto out_free_dma;
0630     }
0631 
0632     cafe->nand.ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
0633     cafe->nand.ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
0634     cafe->nand.ecc.size = mtd->writesize;
0635     cafe->nand.ecc.bytes = 14;
0636     cafe->nand.ecc.strength = 4;
0637     cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
0638     cafe->nand.ecc.write_oob = cafe_nand_write_oob;
0639     cafe->nand.ecc.read_page = cafe_nand_read_page;
0640     cafe->nand.ecc.read_oob = cafe_nand_read_oob;
0641 
0642     return 0;
0643 
0644  out_free_dma:
0645     dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
0646 
0647     return err;
0648 }
0649 
0650 static void cafe_nand_detach_chip(struct nand_chip *chip)
0651 {
0652     struct cafe_priv *cafe = nand_get_controller_data(chip);
0653 
0654     dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
0655 }
0656 
0657 static const struct nand_controller_ops cafe_nand_controller_ops = {
0658     .attach_chip = cafe_nand_attach_chip,
0659     .detach_chip = cafe_nand_detach_chip,
0660 };
0661 
0662 static int cafe_nand_probe(struct pci_dev *pdev,
0663                      const struct pci_device_id *ent)
0664 {
0665     struct mtd_info *mtd;
0666     struct cafe_priv *cafe;
0667     uint32_t ctrl;
0668     int err = 0;
0669 
0670     /* Very old versions shared the same PCI ident for all three
0671        functions on the chip. Verify the class too... */
0672     if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH)
0673         return -ENODEV;
0674 
0675     err = pci_enable_device(pdev);
0676     if (err)
0677         return err;
0678 
0679     pci_set_master(pdev);
0680 
0681     cafe = kzalloc(sizeof(*cafe), GFP_KERNEL);
0682     if (!cafe) {
0683         err = -ENOMEM;
0684         goto out_disable_device;
0685     }
0686 
0687     mtd = nand_to_mtd(&cafe->nand);
0688     mtd->dev.parent = &pdev->dev;
0689     nand_set_controller_data(&cafe->nand, cafe);
0690 
0691     cafe->pdev = pdev;
0692     cafe->mmio = pci_iomap(pdev, 0, 0);
0693     if (!cafe->mmio) {
0694         dev_warn(&pdev->dev, "failed to iomap\n");
0695         err = -ENOMEM;
0696         goto out_free_mtd;
0697     }
0698 
0699     cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
0700     if (!cafe->rs) {
0701         err = -ENOMEM;
0702         goto out_ior;
0703     }
0704 
0705     cafe->nand.legacy.cmdfunc = cafe_nand_cmdfunc;
0706     cafe->nand.legacy.dev_ready = cafe_device_ready;
0707     cafe->nand.legacy.read_byte = cafe_read_byte;
0708     cafe->nand.legacy.read_buf = cafe_read_buf;
0709     cafe->nand.legacy.write_buf = cafe_write_buf;
0710     cafe->nand.legacy.select_chip = cafe_select_chip;
0711     cafe->nand.legacy.set_features = nand_get_set_features_notsupp;
0712     cafe->nand.legacy.get_features = nand_get_set_features_notsupp;
0713 
0714     cafe->nand.legacy.chip_delay = 0;
0715 
0716     /* Enable the following for a flash based bad block table */
0717     cafe->nand.bbt_options = NAND_BBT_USE_FLASH;
0718 
0719     if (skipbbt)
0720         cafe->nand.options |= NAND_SKIP_BBTSCAN | NAND_NO_BBM_QUIRK;
0721 
0722     if (numtimings && numtimings != 3) {
0723         dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
0724     }
0725 
0726     if (numtimings == 3) {
0727         cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
0728                  timing[0], timing[1], timing[2]);
0729     } else {
0730         timing[0] = cafe_readl(cafe, NAND_TIMING1);
0731         timing[1] = cafe_readl(cafe, NAND_TIMING2);
0732         timing[2] = cafe_readl(cafe, NAND_TIMING3);
0733 
0734         if (timing[0] | timing[1] | timing[2]) {
0735             cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
0736                      timing[0], timing[1], timing[2]);
0737         } else {
0738             dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
0739             timing[0] = timing[1] = timing[2] = 0xffffffff;
0740         }
0741     }
0742 
0743     /* Start off by resetting the NAND controller completely */
0744     cafe_writel(cafe, 1, NAND_RESET);
0745     cafe_writel(cafe, 0, NAND_RESET);
0746 
0747     cafe_writel(cafe, timing[0], NAND_TIMING1);
0748     cafe_writel(cafe, timing[1], NAND_TIMING2);
0749     cafe_writel(cafe, timing[2], NAND_TIMING3);
0750 
0751     cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
0752     err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
0753               "CAFE NAND", mtd);
0754     if (err) {
0755         dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
0756         goto out_free_rs;
0757     }
0758 
0759     /* Disable master reset, enable NAND clock */
0760     ctrl = cafe_readl(cafe, GLOBAL_CTRL);
0761     ctrl &= 0xffffeff0;
0762     ctrl |= 0x00007000;
0763     cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
0764     cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
0765     cafe_writel(cafe, 0, NAND_DMA_CTRL);
0766 
0767     cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
0768     cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
0769 
0770     /* Enable NAND IRQ in global IRQ mask register */
0771     cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
0772     cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
0773         cafe_readl(cafe, GLOBAL_CTRL),
0774         cafe_readl(cafe, GLOBAL_IRQ_MASK));
0775 
0776     /* Do not use the DMA during the NAND identification */
0777     cafe->usedma = 0;
0778 
0779     /* Scan to find existence of the device */
0780     cafe->nand.legacy.dummy_controller.ops = &cafe_nand_controller_ops;
0781     err = nand_scan(&cafe->nand, 2);
0782     if (err)
0783         goto out_irq;
0784 
0785     pci_set_drvdata(pdev, mtd);
0786 
0787     mtd->name = "cafe_nand";
0788     err = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
0789     if (err)
0790         goto out_cleanup_nand;
0791 
0792     goto out;
0793 
0794  out_cleanup_nand:
0795     nand_cleanup(&cafe->nand);
0796  out_irq:
0797     /* Disable NAND IRQ in global IRQ mask register */
0798     cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
0799     free_irq(pdev->irq, mtd);
0800  out_free_rs:
0801     free_rs(cafe->rs);
0802  out_ior:
0803     pci_iounmap(pdev, cafe->mmio);
0804  out_free_mtd:
0805     kfree(cafe);
0806  out_disable_device:
0807     pci_disable_device(pdev);
0808  out:
0809     return err;
0810 }
0811 
0812 static void cafe_nand_remove(struct pci_dev *pdev)
0813 {
0814     struct mtd_info *mtd = pci_get_drvdata(pdev);
0815     struct nand_chip *chip = mtd_to_nand(mtd);
0816     struct cafe_priv *cafe = nand_get_controller_data(chip);
0817     int ret;
0818 
0819     /* Disable NAND IRQ in global IRQ mask register */
0820     cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
0821     free_irq(pdev->irq, mtd);
0822     ret = mtd_device_unregister(mtd);
0823     WARN_ON(ret);
0824     nand_cleanup(chip);
0825     free_rs(cafe->rs);
0826     pci_iounmap(pdev, cafe->mmio);
0827     dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
0828     kfree(cafe);
0829     pci_disable_device(pdev);
0830 }
0831 
0832 static const struct pci_device_id cafe_nand_tbl[] = {
0833     { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND,
0834       PCI_ANY_ID, PCI_ANY_ID },
0835     { }
0836 };
0837 
0838 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
0839 
0840 static int cafe_nand_resume(struct pci_dev *pdev)
0841 {
0842     uint32_t ctrl;
0843     struct mtd_info *mtd = pci_get_drvdata(pdev);
0844     struct nand_chip *chip = mtd_to_nand(mtd);
0845     struct cafe_priv *cafe = nand_get_controller_data(chip);
0846 
0847        /* Start off by resetting the NAND controller completely */
0848     cafe_writel(cafe, 1, NAND_RESET);
0849     cafe_writel(cafe, 0, NAND_RESET);
0850     cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
0851 
0852     /* Restore timing configuration */
0853     cafe_writel(cafe, timing[0], NAND_TIMING1);
0854     cafe_writel(cafe, timing[1], NAND_TIMING2);
0855     cafe_writel(cafe, timing[2], NAND_TIMING3);
0856 
0857         /* Disable master reset, enable NAND clock */
0858     ctrl = cafe_readl(cafe, GLOBAL_CTRL);
0859     ctrl &= 0xffffeff0;
0860     ctrl |= 0x00007000;
0861     cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
0862     cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
0863     cafe_writel(cafe, 0, NAND_DMA_CTRL);
0864     cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
0865     cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
0866 
0867     /* Set up DMA address */
0868     cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
0869     if (sizeof(cafe->dmaaddr) > 4)
0870     /* Shift in two parts to shut the compiler up */
0871         cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
0872     else
0873         cafe_writel(cafe, 0, NAND_DMA_ADDR1);
0874 
0875     /* Enable NAND IRQ in global IRQ mask register */
0876     cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
0877     return 0;
0878 }
0879 
0880 static struct pci_driver cafe_nand_pci_driver = {
0881     .name = "CAFÉ NAND",
0882     .id_table = cafe_nand_tbl,
0883     .probe = cafe_nand_probe,
0884     .remove = cafe_nand_remove,
0885     .resume = cafe_nand_resume,
0886 };
0887 
0888 module_pci_driver(cafe_nand_pci_driver);
0889 
0890 MODULE_LICENSE("GPL");
0891 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
0892 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");
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