raw/bcm47xxnflash/ops_bcm4706.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * BCM47XX NAND flash driver
0004  *
0005  * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
0006  */
0007
0008 #include "bcm47xxnflash.h"
0009
0010 #include <linux/module.h>
0011 #include <linux/kernel.h>
0012 #include <linux/slab.h>
0013 #include <linux/delay.h>
0014 #include <linux/bcma/bcma.h>
0015
0016 /* Broadcom uses 1'000'000 but it seems to be too many. Tests on WNDR4500 has
0017  * shown ~1000 retries as maxiumum. */
0018 #define NFLASH_READY_RETRIES        10000
0019
0020 #define NFLASH_SECTOR_SIZE      512
0021
0022 #define NCTL_CMD0           0x00010000
0023 #define NCTL_COL            0x00020000  /* Update column with value from BCMA_CC_NFLASH_COL_ADDR */
0024 #define NCTL_ROW            0x00040000  /* Update row (page) with value from BCMA_CC_NFLASH_ROW_ADDR */
0025 #define NCTL_CMD1W          0x00080000
0026 #define NCTL_READ           0x00100000
0027 #define NCTL_WRITE          0x00200000
0028 #define NCTL_SPECADDR           0x01000000
0029 #define NCTL_READY          0x04000000
0030 #define NCTL_ERR            0x08000000
0031 #define NCTL_CSA            0x40000000
0032 #define NCTL_START          0x80000000
0033
0034 /**************************************************
0035  * Various helpers
0036  **************************************************/
0037
0038 static inline u8 bcm47xxnflash_ops_bcm4706_ns_to_cycle(u16 ns, u16 clock)
0039 {
0040     return ((ns * 1000 * clock) / 1000000) + 1;
0041 }
0042
0043 static int bcm47xxnflash_ops_bcm4706_ctl_cmd(struct bcma_drv_cc *cc, u32 code)
0044 {
0045     int i = 0;
0046
0047     bcma_cc_write32(cc, BCMA_CC_NFLASH_CTL, NCTL_START | code);
0048     for (i = 0; i < NFLASH_READY_RETRIES; i++) {
0049         if (!(bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_START)) {
0050             i = 0;
0051             break;
0052         }
0053     }
0054     if (i) {
0055         pr_err("NFLASH control command not ready!\n");
0056         return -EBUSY;
0057     }
0058     return 0;
0059 }
0060
0061 static int bcm47xxnflash_ops_bcm4706_poll(struct bcma_drv_cc *cc)
0062 {
0063     int i;
0064
0065     for (i = 0; i < NFLASH_READY_RETRIES; i++) {
0066         if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_READY) {
0067             if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) &
0068                 BCMA_CC_NFLASH_CTL_ERR) {
0069                 pr_err("Error on polling\n");
0070                 return -EBUSY;
0071             } else {
0072                 return 0;
0073             }
0074         }
0075     }
0076
0077     pr_err("Polling timeout!\n");
0078     return -EBUSY;
0079 }
0080
0081 /**************************************************
0082  * R/W
0083  **************************************************/
0084
0085 static void bcm47xxnflash_ops_bcm4706_read(struct mtd_info *mtd, uint8_t *buf,
0086                        int len)
0087 {
0088     struct nand_chip *nand_chip = mtd_to_nand(mtd);
0089     struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
0090
0091     u32 ctlcode;
0092     u32 *dest = (u32 *)buf;
0093     int i;
0094     int toread;
0095
0096     BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
0097     /* Don't validate column using nand_chip->page_shift, it may be bigger
0098      * when accessing OOB */
0099
0100     while (len) {
0101         /* We can read maximum of 0x200 bytes at once */
0102         toread = min(len, 0x200);
0103
0104         /* Set page and column */
0105         bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_COL_ADDR,
0106                 b47n->curr_column);
0107         bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_ROW_ADDR,
0108                 b47n->curr_page_addr);
0109
0110         /* Prepare to read */
0111         ctlcode = NCTL_CSA | NCTL_CMD1W | NCTL_ROW | NCTL_COL |
0112               NCTL_CMD0;
0113         ctlcode |= NAND_CMD_READSTART << 8;
0114         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode))
0115             return;
0116         if (bcm47xxnflash_ops_bcm4706_poll(b47n->cc))
0117             return;
0118
0119         /* Eventually read some data :) */
0120         for (i = 0; i < toread; i += 4, dest++) {
0121             ctlcode = NCTL_CSA | 0x30000000 | NCTL_READ;
0122             if (i == toread - 4) /* Last read goes without that */
0123                 ctlcode &= ~NCTL_CSA;
0124             if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
0125                                   ctlcode))
0126                 return;
0127             *dest = bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA);
0128         }
0129
0130         b47n->curr_column += toread;
0131         len -= toread;
0132     }
0133 }
0134
0135 static void bcm47xxnflash_ops_bcm4706_write(struct mtd_info *mtd,
0136                         const uint8_t *buf, int len)
0137 {
0138     struct nand_chip *nand_chip = mtd_to_nand(mtd);
0139     struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
0140     struct bcma_drv_cc *cc = b47n->cc;
0141
0142     u32 ctlcode;
0143     const u32 *data = (u32 *)buf;
0144     int i;
0145
0146     BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
0147     /* Don't validate column using nand_chip->page_shift, it may be bigger
0148      * when accessing OOB */
0149
0150     for (i = 0; i < len; i += 4, data++) {
0151         bcma_cc_write32(cc, BCMA_CC_NFLASH_DATA, *data);
0152
0153         ctlcode = NCTL_CSA | 0x30000000 | NCTL_WRITE;
0154         if (i == len - 4) /* Last read goes without that */
0155             ctlcode &= ~NCTL_CSA;
0156         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode)) {
0157             pr_err("%s ctl_cmd didn't work!\n", __func__);
0158             return;
0159         }
0160     }
0161
0162     b47n->curr_column += len;
0163 }
0164
0165 /**************************************************
0166  * NAND chip ops
0167  **************************************************/
0168
0169 static void bcm47xxnflash_ops_bcm4706_cmd_ctrl(struct nand_chip *nand_chip,
0170                            int cmd, unsigned int ctrl)
0171 {
0172     struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
0173     u32 code = 0;
0174
0175     if (cmd == NAND_CMD_NONE)
0176         return;
0177
0178     if (cmd & NAND_CTRL_CLE)
0179         code = cmd | NCTL_CMD0;
0180
0181     /* nCS is not needed for reset command */
0182     if (cmd != NAND_CMD_RESET)
0183         code |= NCTL_CSA;
0184
0185     bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, code);
0186 }
0187
0188 /* Default nand_select_chip calls cmd_ctrl, which is not used in BCM4706 */
0189 static void bcm47xxnflash_ops_bcm4706_select_chip(struct nand_chip *chip,
0190                           int cs)
0191 {
0192     return;
0193 }
0194
0195 static int bcm47xxnflash_ops_bcm4706_dev_ready(struct nand_chip *nand_chip)
0196 {
0197     struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
0198
0199     return !!(bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_CTL) & NCTL_READY);
0200 }
0201
0202 /*
0203  * Default nand_command and nand_command_lp don't match BCM4706 hardware layout.
0204  * For example, reading chip id is performed in a non-standard way.
0205  * Setting column and page is also handled differently, we use a special
0206  * registers of ChipCommon core. Hacking cmd_ctrl to understand and convert
0207  * standard commands would be much more complicated.
0208  */
0209 static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct nand_chip *nand_chip,
0210                           unsigned command, int column,
0211                           int page_addr)
0212 {
0213     struct mtd_info *mtd = nand_to_mtd(nand_chip);
0214     struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
0215     struct bcma_drv_cc *cc = b47n->cc;
0216     u32 ctlcode;
0217     int i;
0218
0219     if (column != -1)
0220         b47n->curr_column = column;
0221     if (page_addr != -1)
0222         b47n->curr_page_addr = page_addr;
0223
0224     switch (command) {
0225     case NAND_CMD_RESET:
0226         nand_chip->legacy.cmd_ctrl(nand_chip, command, NAND_CTRL_CLE);
0227
0228         ndelay(100);
0229         nand_wait_ready(nand_chip);
0230         break;
0231     case NAND_CMD_READID:
0232         ctlcode = NCTL_CSA | 0x01000000 | NCTL_CMD1W | NCTL_CMD0;
0233         ctlcode |= NAND_CMD_READID;
0234         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) {
0235             pr_err("READID error\n");
0236             break;
0237         }
0238
0239         /*
0240          * Reading is specific, last one has to go without NCTL_CSA
0241          * bit. We don't know how many reads NAND subsystem is going
0242          * to perform, so cache everything.
0243          */
0244         for (i = 0; i < ARRAY_SIZE(b47n->id_data); i++) {
0245             ctlcode = NCTL_CSA | NCTL_READ;
0246             if (i == ARRAY_SIZE(b47n->id_data) - 1)
0247                 ctlcode &= ~NCTL_CSA;
0248             if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
0249                                   ctlcode)) {
0250                 pr_err("READID error\n");
0251                 break;
0252             }
0253             b47n->id_data[i] =
0254                 bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA)
0255                 & 0xFF;
0256         }
0257
0258         break;
0259     case NAND_CMD_STATUS:
0260         ctlcode = NCTL_CSA | NCTL_CMD0 | NAND_CMD_STATUS;
0261         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
0262             pr_err("STATUS command error\n");
0263         break;
0264     case NAND_CMD_READ0:
0265         break;
0266     case NAND_CMD_READOOB:
0267         if (page_addr != -1)
0268             b47n->curr_column += mtd->writesize;
0269         break;
0270     case NAND_CMD_ERASE1:
0271         bcma_cc_write32(cc, BCMA_CC_NFLASH_ROW_ADDR,
0272                 b47n->curr_page_addr);
0273         ctlcode = NCTL_ROW | NCTL_CMD1W | NCTL_CMD0 |
0274               NAND_CMD_ERASE1 | (NAND_CMD_ERASE2 << 8);
0275         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
0276             pr_err("ERASE1 failed\n");
0277         break;
0278     case NAND_CMD_ERASE2:
0279         break;
0280     case NAND_CMD_SEQIN:
0281         /* Set page and column */
0282         bcma_cc_write32(cc, BCMA_CC_NFLASH_COL_ADDR,
0283                 b47n->curr_column);
0284         bcma_cc_write32(cc, BCMA_CC_NFLASH_ROW_ADDR,
0285                 b47n->curr_page_addr);
0286
0287         /* Prepare to write */
0288         ctlcode = 0x40000000 | NCTL_ROW | NCTL_COL | NCTL_CMD0;
0289         ctlcode |= NAND_CMD_SEQIN;
0290         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
0291             pr_err("SEQIN failed\n");
0292         break;
0293     case NAND_CMD_PAGEPROG:
0294         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, NCTL_CMD0 |
0295                               NAND_CMD_PAGEPROG))
0296             pr_err("PAGEPROG failed\n");
0297         if (bcm47xxnflash_ops_bcm4706_poll(cc))
0298             pr_err("PAGEPROG not ready\n");
0299         break;
0300     default:
0301         pr_err("Command 0x%X unsupported\n", command);
0302         break;
0303     }
0304     b47n->curr_command = command;
0305 }
0306
0307 static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct nand_chip *nand_chip)
0308 {
0309     struct mtd_info *mtd = nand_to_mtd(nand_chip);
0310     struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
0311     struct bcma_drv_cc *cc = b47n->cc;
0312     u32 tmp = 0;
0313
0314     switch (b47n->curr_command) {
0315     case NAND_CMD_READID:
0316         if (b47n->curr_column >= ARRAY_SIZE(b47n->id_data)) {
0317             pr_err("Requested invalid id_data: %d\n",
0318                    b47n->curr_column);
0319             return 0;
0320         }
0321         return b47n->id_data[b47n->curr_column++];
0322     case NAND_CMD_STATUS:
0323         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, NCTL_READ))
0324             return 0;
0325         return bcma_cc_read32(cc, BCMA_CC_NFLASH_DATA) & 0xff;
0326     case NAND_CMD_READOOB:
0327         bcm47xxnflash_ops_bcm4706_read(mtd, (u8 *)&tmp, 4);
0328         return tmp & 0xFF;
0329     }
0330
0331     pr_err("Invalid command for byte read: 0x%X\n", b47n->curr_command);
0332     return 0;
0333 }
0334
0335 static void bcm47xxnflash_ops_bcm4706_read_buf(struct nand_chip *nand_chip,
0336                            uint8_t *buf, int len)
0337 {
0338     struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
0339
0340     switch (b47n->curr_command) {
0341     case NAND_CMD_READ0:
0342     case NAND_CMD_READOOB:
0343         bcm47xxnflash_ops_bcm4706_read(nand_to_mtd(nand_chip), buf,
0344                            len);
0345         return;
0346     }
0347
0348     pr_err("Invalid command for buf read: 0x%X\n", b47n->curr_command);
0349 }
0350
0351 static void bcm47xxnflash_ops_bcm4706_write_buf(struct nand_chip *nand_chip,
0352                         const uint8_t *buf, int len)
0353 {
0354     struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
0355
0356     switch (b47n->curr_command) {
0357     case NAND_CMD_SEQIN:
0358         bcm47xxnflash_ops_bcm4706_write(nand_to_mtd(nand_chip), buf,
0359                         len);
0360         return;
0361     }
0362
0363     pr_err("Invalid command for buf write: 0x%X\n", b47n->curr_command);
0364 }
0365
0366 /**************************************************
0367  * Init
0368  **************************************************/
0369
0370 int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
0371 {
0372     struct nand_chip *nand_chip = (struct nand_chip *)&b47n->nand_chip;
0373     int err;
0374     u32 freq;
0375     u16 clock;
0376     u8 w0, w1, w2, w3, w4;
0377
0378     unsigned long chipsize; /* MiB */
0379     u8 tbits, col_bits, col_size, row_bits, row_bsize;
0380     u32 val;
0381
0382     nand_chip->legacy.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
0383     nand_chip->legacy.cmd_ctrl = bcm47xxnflash_ops_bcm4706_cmd_ctrl;
0384     nand_chip->legacy.dev_ready = bcm47xxnflash_ops_bcm4706_dev_ready;
0385     b47n->nand_chip.legacy.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc;
0386     b47n->nand_chip.legacy.read_byte = bcm47xxnflash_ops_bcm4706_read_byte;
0387     b47n->nand_chip.legacy.read_buf = bcm47xxnflash_ops_bcm4706_read_buf;
0388     b47n->nand_chip.legacy.write_buf = bcm47xxnflash_ops_bcm4706_write_buf;
0389     b47n->nand_chip.legacy.set_features = nand_get_set_features_notsupp;
0390     b47n->nand_chip.legacy.get_features = nand_get_set_features_notsupp;
0391
0392     nand_chip->legacy.chip_delay = 50;
0393     b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH;
0394     /* TODO: implement ECC */
0395     b47n->nand_chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_NONE;
0396
0397     /* Enable NAND flash access */
0398     bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
0399               BCMA_CC_4706_FLASHSCFG_NF1);
0400
0401     /* Configure wait counters */
0402     if (b47n->cc->status & BCMA_CC_CHIPST_4706_PKG_OPTION) {
0403         /* 400 MHz */
0404         freq = 400000000 / 4;
0405     } else {
0406         freq = bcma_chipco_pll_read(b47n->cc, 4);
0407         freq = (freq & 0xFFF) >> 3;
0408         /* Fixed reference clock 25 MHz and m = 2 */
0409         freq = (freq * 25000000 / 2) / 4;
0410     }
0411     clock = freq / 1000000;
0412     w0 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(15, clock);
0413     w1 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(20, clock);
0414     w2 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
0415     w3 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
0416     w4 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(100, clock);
0417     bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_WAITCNT0,
0418             (w4 << 24 | w3 << 18 | w2 << 12 | w1 << 6 | w0));
0419
0420     /* Scan NAND */
0421     err = nand_scan(&b47n->nand_chip, 1);
0422     if (err) {
0423         pr_err("Could not scan NAND flash: %d\n", err);
0424         goto exit;
0425     }
0426
0427     /* Configure FLASH */
0428     chipsize = nanddev_target_size(&b47n->nand_chip.base) >> 20;
0429     tbits = ffs(chipsize); /* find first bit set */
0430     if (!tbits || tbits != fls(chipsize)) {
0431         pr_err("Invalid flash size: 0x%lX\n", chipsize);
0432         err = -ENOTSUPP;
0433         goto exit;
0434     }
0435     tbits += 19; /* Broadcom increases *index* by 20, we increase *pos* */
0436
0437     col_bits = b47n->nand_chip.page_shift + 1;
0438     col_size = (col_bits + 7) / 8;
0439
0440     row_bits = tbits - col_bits + 1;
0441     row_bsize = (row_bits + 7) / 8;
0442
0443     val = ((row_bsize - 1) << 6) | ((col_size - 1) << 4) | 2;
0444     bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_CONF, val);
0445
0446 exit:
0447     if (err)
0448         bcma_cc_mask32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
0449                    ~BCMA_CC_4706_FLASHSCFG_NF1);
0450     return err;
0451 }