nand/raw/au1550nd.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Copyright (C) 2004 Embedded Edge, LLC
0004  */
0005
0006 #include <linux/delay.h>
0007 #include <linux/slab.h>
0008 #include <linux/module.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/mtd/mtd.h>
0011 #include <linux/mtd/rawnand.h>
0012 #include <linux/mtd/partitions.h>
0013 #include <linux/platform_device.h>
0014 #include <asm/io.h>
0015 #include <asm/mach-au1x00/au1000.h>
0016 #include <asm/mach-au1x00/au1550nd.h>
0017
0018
0019 struct au1550nd_ctx {
0020     struct nand_controller controller;
0021     struct nand_chip chip;
0022
0023     int cs;
0024     void __iomem *base;
0025 };
0026
0027 static struct au1550nd_ctx *chip_to_au_ctx(struct nand_chip *this)
0028 {
0029     return container_of(this, struct au1550nd_ctx, chip);
0030 }
0031
0032 /**
0033  * au_write_buf -  write buffer to chip
0034  * @this:   NAND chip object
0035  * @buf:    data buffer
0036  * @len:    number of bytes to write
0037  *
0038  * write function for 8bit buswidth
0039  */
0040 static void au_write_buf(struct nand_chip *this, const void *buf,
0041              unsigned int len)
0042 {
0043     struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
0044     const u8 *p = buf;
0045     int i;
0046
0047     for (i = 0; i < len; i++) {
0048         writeb(p[i], ctx->base + MEM_STNAND_DATA);
0049         wmb(); /* drain writebuffer */
0050     }
0051 }
0052
0053 /**
0054  * au_read_buf -  read chip data into buffer
0055  * @this:   NAND chip object
0056  * @buf:    buffer to store date
0057  * @len:    number of bytes to read
0058  *
0059  * read function for 8bit buswidth
0060  */
0061 static void au_read_buf(struct nand_chip *this, void *buf,
0062             unsigned int len)
0063 {
0064     struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
0065     u8 *p = buf;
0066     int i;
0067
0068     for (i = 0; i < len; i++) {
0069         p[i] = readb(ctx->base + MEM_STNAND_DATA);
0070         wmb(); /* drain writebuffer */
0071     }
0072 }
0073
0074 /**
0075  * au_write_buf16 -  write buffer to chip
0076  * @this:   NAND chip object
0077  * @buf:    data buffer
0078  * @len:    number of bytes to write
0079  *
0080  * write function for 16bit buswidth
0081  */
0082 static void au_write_buf16(struct nand_chip *this, const void *buf,
0083                unsigned int len)
0084 {
0085     struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
0086     const u16 *p = buf;
0087     unsigned int i;
0088
0089     len >>= 1;
0090     for (i = 0; i < len; i++) {
0091         writew(p[i], ctx->base + MEM_STNAND_DATA);
0092         wmb(); /* drain writebuffer */
0093     }
0094 }
0095
0096 /**
0097  * au_read_buf16 -  read chip data into buffer
0098  * @this:   NAND chip object
0099  * @buf:    buffer to store date
0100  * @len:    number of bytes to read
0101  *
0102  * read function for 16bit buswidth
0103  */
0104 static void au_read_buf16(struct nand_chip *this, void *buf, unsigned int len)
0105 {
0106     struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
0107     unsigned int i;
0108     u16 *p = buf;
0109
0110     len >>= 1;
0111     for (i = 0; i < len; i++) {
0112         p[i] = readw(ctx->base + MEM_STNAND_DATA);
0113         wmb(); /* drain writebuffer */
0114     }
0115 }
0116
0117 static int find_nand_cs(unsigned long nand_base)
0118 {
0119     void __iomem *base =
0120             (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
0121     unsigned long addr, staddr, start, mask, end;
0122     int i;
0123
0124     for (i = 0; i < 4; i++) {
0125         addr = 0x1000 + (i * 0x10);         /* CSx */
0126         staddr = __raw_readl(base + addr + 0x08);   /* STADDRx */
0127         /* figure out the decoded range of this CS */
0128         start = (staddr << 4) & 0xfffc0000;
0129         mask = (staddr << 18) & 0xfffc0000;
0130         end = (start | (start - 1)) & ~(start ^ mask);
0131         if ((nand_base >= start) && (nand_base < end))
0132             return i;
0133     }
0134
0135     return -ENODEV;
0136 }
0137
0138 static int au1550nd_waitrdy(struct nand_chip *this, unsigned int timeout_ms)
0139 {
0140     unsigned long timeout_jiffies = jiffies;
0141
0142     timeout_jiffies += msecs_to_jiffies(timeout_ms) + 1;
0143     do {
0144         if (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1)
0145             return 0;
0146
0147         usleep_range(10, 100);
0148     } while (time_before(jiffies, timeout_jiffies));
0149
0150     return -ETIMEDOUT;
0151 }
0152
0153 static int au1550nd_exec_instr(struct nand_chip *this,
0154                    const struct nand_op_instr *instr)
0155 {
0156     struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
0157     unsigned int i;
0158     int ret = 0;
0159
0160     switch (instr->type) {
0161     case NAND_OP_CMD_INSTR:
0162         writeb(instr->ctx.cmd.opcode,
0163                ctx->base + MEM_STNAND_CMD);
0164         /* Drain the writebuffer */
0165         wmb();
0166         break;
0167
0168     case NAND_OP_ADDR_INSTR:
0169         for (i = 0; i < instr->ctx.addr.naddrs; i++) {
0170             writeb(instr->ctx.addr.addrs[i],
0171                    ctx->base + MEM_STNAND_ADDR);
0172             /* Drain the writebuffer */
0173             wmb();
0174         }
0175         break;
0176
0177     case NAND_OP_DATA_IN_INSTR:
0178         if ((this->options & NAND_BUSWIDTH_16) &&
0179             !instr->ctx.data.force_8bit)
0180             au_read_buf16(this, instr->ctx.data.buf.in,
0181                       instr->ctx.data.len);
0182         else
0183             au_read_buf(this, instr->ctx.data.buf.in,
0184                     instr->ctx.data.len);
0185         break;
0186
0187     case NAND_OP_DATA_OUT_INSTR:
0188         if ((this->options & NAND_BUSWIDTH_16) &&
0189             !instr->ctx.data.force_8bit)
0190             au_write_buf16(this, instr->ctx.data.buf.out,
0191                        instr->ctx.data.len);
0192         else
0193             au_write_buf(this, instr->ctx.data.buf.out,
0194                      instr->ctx.data.len);
0195         break;
0196
0197     case NAND_OP_WAITRDY_INSTR:
0198         ret = au1550nd_waitrdy(this, instr->ctx.waitrdy.timeout_ms);
0199         break;
0200     default:
0201         return -EINVAL;
0202     }
0203
0204     if (instr->delay_ns)
0205         ndelay(instr->delay_ns);
0206
0207     return ret;
0208 }
0209
0210 static int au1550nd_exec_op(struct nand_chip *this,
0211                 const struct nand_operation *op,
0212                 bool check_only)
0213 {
0214     struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
0215     unsigned int i;
0216     int ret;
0217
0218     if (check_only)
0219         return 0;
0220
0221     /* assert (force assert) chip enable */
0222     alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
0223     /* Drain the writebuffer */
0224     wmb();
0225
0226     for (i = 0; i < op->ninstrs; i++) {
0227         ret = au1550nd_exec_instr(this, &op->instrs[i]);
0228         if (ret)
0229             break;
0230     }
0231
0232     /* deassert chip enable */
0233     alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
0234     /* Drain the writebuffer */
0235     wmb();
0236
0237     return ret;
0238 }
0239
0240 static int au1550nd_attach_chip(struct nand_chip *chip)
0241 {
0242     if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
0243         chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
0244         chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
0245
0246     return 0;
0247 }
0248
0249 static const struct nand_controller_ops au1550nd_ops = {
0250     .exec_op = au1550nd_exec_op,
0251     .attach_chip = au1550nd_attach_chip,
0252 };
0253
0254 static int au1550nd_probe(struct platform_device *pdev)
0255 {
0256     struct au1550nd_platdata *pd;
0257     struct au1550nd_ctx *ctx;
0258     struct nand_chip *this;
0259     struct mtd_info *mtd;
0260     struct resource *r;
0261     int ret, cs;
0262
0263     pd = dev_get_platdata(&pdev->dev);
0264     if (!pd) {
0265         dev_err(&pdev->dev, "missing platform data\n");
0266         return -ENODEV;
0267     }
0268
0269     ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
0270     if (!ctx)
0271         return -ENOMEM;
0272
0273     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0274     if (!r) {
0275         dev_err(&pdev->dev, "no NAND memory resource\n");
0276         ret = -ENODEV;
0277         goto out1;
0278     }
0279     if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
0280         dev_err(&pdev->dev, "cannot claim NAND memory area\n");
0281         ret = -ENOMEM;
0282         goto out1;
0283     }
0284
0285     ctx->base = ioremap(r->start, 0x1000);
0286     if (!ctx->base) {
0287         dev_err(&pdev->dev, "cannot remap NAND memory area\n");
0288         ret = -ENODEV;
0289         goto out2;
0290     }
0291
0292     this = &ctx->chip;
0293     mtd = nand_to_mtd(this);
0294     mtd->dev.parent = &pdev->dev;
0295
0296     /* figure out which CS# r->start belongs to */
0297     cs = find_nand_cs(r->start);
0298     if (cs < 0) {
0299         dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
0300         ret = -ENODEV;
0301         goto out3;
0302     }
0303     ctx->cs = cs;
0304
0305     nand_controller_init(&ctx->controller);
0306     ctx->controller.ops = &au1550nd_ops;
0307     this->controller = &ctx->controller;
0308
0309     if (pd->devwidth)
0310         this->options |= NAND_BUSWIDTH_16;
0311
0312     /*
0313      * This driver assumes that the default ECC engine should be TYPE_SOFT.
0314      * Set ->engine_type before registering the NAND devices in order to
0315      * provide a driver specific default value.
0316      */
0317     this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
0318
0319     ret = nand_scan(this, 1);
0320     if (ret) {
0321         dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
0322         goto out3;
0323     }
0324
0325     mtd_device_register(mtd, pd->parts, pd->num_parts);
0326
0327     platform_set_drvdata(pdev, ctx);
0328
0329     return 0;
0330
0331 out3:
0332     iounmap(ctx->base);
0333 out2:
0334     release_mem_region(r->start, resource_size(r));
0335 out1:
0336     kfree(ctx);
0337     return ret;
0338 }
0339
0340 static int au1550nd_remove(struct platform_device *pdev)
0341 {
0342     struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
0343     struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0344     struct nand_chip *chip = &ctx->chip;
0345     int ret;
0346
0347     ret = mtd_device_unregister(nand_to_mtd(chip));
0348     WARN_ON(ret);
0349     nand_cleanup(chip);
0350     iounmap(ctx->base);
0351     release_mem_region(r->start, 0x1000);
0352     kfree(ctx);
0353     return 0;
0354 }
0355
0356 static struct platform_driver au1550nd_driver = {
0357     .driver = {
0358         .name   = "au1550-nand",
0359     },
0360     .probe      = au1550nd_probe,
0361     .remove     = au1550nd_remove,
0362 };
0363
0364 module_platform_driver(au1550nd_driver);
0365
0366 MODULE_LICENSE("GPL");
0367 MODULE_AUTHOR("Embedded Edge, LLC");
0368 MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");