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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Arasan NAND Flash Controller Driver
0004  *
0005  * Copyright (C) 2014 - 2020 Xilinx, Inc.
0006  * Author:
0007  *   Miquel Raynal <miquel.raynal@bootlin.com>
0008  * Original work (fully rewritten):
0009  *   Punnaiah Choudary Kalluri <punnaia@xilinx.com>
0010  *   Naga Sureshkumar Relli <nagasure@xilinx.com>
0011  */
0012 
0013 #include <linux/bch.h>
0014 #include <linux/bitfield.h>
0015 #include <linux/clk.h>
0016 #include <linux/delay.h>
0017 #include <linux/dma-mapping.h>
0018 #include <linux/gpio/consumer.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/iopoll.h>
0021 #include <linux/module.h>
0022 #include <linux/mtd/mtd.h>
0023 #include <linux/mtd/partitions.h>
0024 #include <linux/mtd/rawnand.h>
0025 #include <linux/of.h>
0026 #include <linux/platform_device.h>
0027 #include <linux/slab.h>
0028 
0029 #define PKT_REG             0x00
0030 #define   PKT_SIZE(x)           FIELD_PREP(GENMASK(10, 0), (x))
0031 #define   PKT_STEPS(x)          FIELD_PREP(GENMASK(23, 12), (x))
0032 
0033 #define MEM_ADDR1_REG           0x04
0034 
0035 #define MEM_ADDR2_REG           0x08
0036 #define   ADDR2_STRENGTH(x)     FIELD_PREP(GENMASK(27, 25), (x))
0037 #define   ADDR2_CS(x)           FIELD_PREP(GENMASK(31, 30), (x))
0038 
0039 #define CMD_REG             0x0C
0040 #define   CMD_1(x)          FIELD_PREP(GENMASK(7, 0), (x))
0041 #define   CMD_2(x)          FIELD_PREP(GENMASK(15, 8), (x))
0042 #define   CMD_PAGE_SIZE(x)      FIELD_PREP(GENMASK(25, 23), (x))
0043 #define   CMD_DMA_ENABLE        BIT(27)
0044 #define   CMD_NADDRS(x)         FIELD_PREP(GENMASK(30, 28), (x))
0045 #define   CMD_ECC_ENABLE        BIT(31)
0046 
0047 #define PROG_REG            0x10
0048 #define   PROG_PGRD         BIT(0)
0049 #define   PROG_ERASE            BIT(2)
0050 #define   PROG_STATUS           BIT(3)
0051 #define   PROG_PGPROG           BIT(4)
0052 #define   PROG_RDID         BIT(6)
0053 #define   PROG_RDPARAM          BIT(7)
0054 #define   PROG_RST          BIT(8)
0055 #define   PROG_GET_FEATURE      BIT(9)
0056 #define   PROG_SET_FEATURE      BIT(10)
0057 #define   PROG_CHG_RD_COL_ENH       BIT(14)
0058 
0059 #define INTR_STS_EN_REG         0x14
0060 #define INTR_SIG_EN_REG         0x18
0061 #define INTR_STS_REG            0x1C
0062 #define   WRITE_READY           BIT(0)
0063 #define   READ_READY            BIT(1)
0064 #define   XFER_COMPLETE         BIT(2)
0065 #define   DMA_BOUNDARY          BIT(6)
0066 #define   EVENT_MASK            GENMASK(7, 0)
0067 
0068 #define READY_STS_REG           0x20
0069 
0070 #define DMA_ADDR0_REG           0x50
0071 #define DMA_ADDR1_REG           0x24
0072 
0073 #define FLASH_STS_REG           0x28
0074 
0075 #define TIMING_REG          0x2C
0076 #define   TCCS_TIME_500NS       0
0077 #define   TCCS_TIME_300NS       3
0078 #define   TCCS_TIME_200NS       2
0079 #define   TCCS_TIME_100NS       1
0080 #define   FAST_TCAD         BIT(2)
0081 #define   DQS_BUFF_SEL_IN(x)        FIELD_PREP(GENMASK(6, 3), (x))
0082 #define   DQS_BUFF_SEL_OUT(x)       FIELD_PREP(GENMASK(18, 15), (x))
0083 
0084 #define DATA_PORT_REG           0x30
0085 
0086 #define ECC_CONF_REG            0x34
0087 #define   ECC_CONF_COL(x)       FIELD_PREP(GENMASK(15, 0), (x))
0088 #define   ECC_CONF_LEN(x)       FIELD_PREP(GENMASK(26, 16), (x))
0089 #define   ECC_CONF_BCH_EN       BIT(27)
0090 
0091 #define ECC_ERR_CNT_REG         0x38
0092 #define   GET_PKT_ERR_CNT(x)        FIELD_GET(GENMASK(7, 0), (x))
0093 #define   GET_PAGE_ERR_CNT(x)       FIELD_GET(GENMASK(16, 8), (x))
0094 
0095 #define ECC_SP_REG          0x3C
0096 #define   ECC_SP_CMD1(x)        FIELD_PREP(GENMASK(7, 0), (x))
0097 #define   ECC_SP_CMD2(x)        FIELD_PREP(GENMASK(15, 8), (x))
0098 #define   ECC_SP_ADDRS(x)       FIELD_PREP(GENMASK(30, 28), (x))
0099 
0100 #define ECC_1ERR_CNT_REG        0x40
0101 #define ECC_2ERR_CNT_REG        0x44
0102 
0103 #define DATA_INTERFACE_REG      0x6C
0104 #define   DIFACE_SDR_MODE(x)        FIELD_PREP(GENMASK(2, 0), (x))
0105 #define   DIFACE_DDR_MODE(x)        FIELD_PREP(GENMASK(5, 3), (x))
0106 #define   DIFACE_SDR            0
0107 #define   DIFACE_NVDDR          BIT(9)
0108 
0109 #define ANFC_MAX_CS         2
0110 #define ANFC_DFLT_TIMEOUT_US        1000000
0111 #define ANFC_MAX_CHUNK_SIZE     SZ_1M
0112 #define ANFC_MAX_PARAM_SIZE     SZ_4K
0113 #define ANFC_MAX_STEPS          SZ_2K
0114 #define ANFC_MAX_PKT_SIZE       (SZ_2K - 1)
0115 #define ANFC_MAX_ADDR_CYC       5U
0116 #define ANFC_RSVD_ECC_BYTES     21
0117 
0118 #define ANFC_XLNX_SDR_DFLT_CORE_CLK 100000000
0119 #define ANFC_XLNX_SDR_HS_CORE_CLK   80000000
0120 
0121 static struct gpio_desc *anfc_default_cs_array[2] = {NULL, NULL};
0122 
0123 /**
0124  * struct anfc_op - Defines how to execute an operation
0125  * @pkt_reg: Packet register
0126  * @addr1_reg: Memory address 1 register
0127  * @addr2_reg: Memory address 2 register
0128  * @cmd_reg: Command register
0129  * @prog_reg: Program register
0130  * @steps: Number of "packets" to read/write
0131  * @rdy_timeout_ms: Timeout for waits on Ready/Busy pin
0132  * @len: Data transfer length
0133  * @read: Data transfer direction from the controller point of view
0134  * @buf: Data buffer
0135  */
0136 struct anfc_op {
0137     u32 pkt_reg;
0138     u32 addr1_reg;
0139     u32 addr2_reg;
0140     u32 cmd_reg;
0141     u32 prog_reg;
0142     int steps;
0143     unsigned int rdy_timeout_ms;
0144     unsigned int len;
0145     bool read;
0146     u8 *buf;
0147 };
0148 
0149 /**
0150  * struct anand - Defines the NAND chip related information
0151  * @node:       Used to store NAND chips into a list
0152  * @chip:       NAND chip information structure
0153  * @rb:         Ready-busy line
0154  * @page_sz:        Register value of the page_sz field to use
0155  * @clk:        Expected clock frequency to use
0156  * @data_iface:     Data interface timing mode to use
0157  * @timings:        NV-DDR specific timings to use
0158  * @ecc_conf:       Hardware ECC configuration value
0159  * @strength:       Register value of the ECC strength
0160  * @raddr_cycles:   Row address cycle information
0161  * @caddr_cycles:   Column address cycle information
0162  * @ecc_bits:       Exact number of ECC bits per syndrome
0163  * @ecc_total:      Total number of ECC bytes
0164  * @errloc:     Array of errors located with soft BCH
0165  * @hw_ecc:     Buffer to store syndromes computed by hardware
0166  * @bch:        BCH structure
0167  * @cs_idx:     Array of chip-select for this device, values are indexes
0168  *          of the controller structure @gpio_cs array
0169  * @ncs_idx:        Size of the @cs_idx array
0170  */
0171 struct anand {
0172     struct list_head node;
0173     struct nand_chip chip;
0174     unsigned int rb;
0175     unsigned int page_sz;
0176     unsigned long clk;
0177     u32 data_iface;
0178     u32 timings;
0179     u32 ecc_conf;
0180     u32 strength;
0181     u16 raddr_cycles;
0182     u16 caddr_cycles;
0183     unsigned int ecc_bits;
0184     unsigned int ecc_total;
0185     unsigned int *errloc;
0186     u8 *hw_ecc;
0187     struct bch_control *bch;
0188     int *cs_idx;
0189     int ncs_idx;
0190 };
0191 
0192 /**
0193  * struct arasan_nfc - Defines the Arasan NAND flash controller driver instance
0194  * @dev:        Pointer to the device structure
0195  * @base:       Remapped register area
0196  * @controller_clk:     Pointer to the system clock
0197  * @bus_clk:        Pointer to the flash clock
0198  * @controller:     Base controller structure
0199  * @chips:      List of all NAND chips attached to the controller
0200  * @cur_clk:        Current clock rate
0201  * @cs_array:       CS array. Native CS are left empty, the other cells are
0202  *          populated with their corresponding GPIO descriptor.
0203  * @ncs:        Size of @cs_array
0204  * @cur_cs:     Index in @cs_array of the currently in use CS
0205  * @native_cs:      Currently selected native CS
0206  * @spare_cs:       Native CS that is not wired (may be selected when a GPIO
0207  *          CS is in use)
0208  */
0209 struct arasan_nfc {
0210     struct device *dev;
0211     void __iomem *base;
0212     struct clk *controller_clk;
0213     struct clk *bus_clk;
0214     struct nand_controller controller;
0215     struct list_head chips;
0216     unsigned int cur_clk;
0217     struct gpio_desc **cs_array;
0218     unsigned int ncs;
0219     int cur_cs;
0220     unsigned int native_cs;
0221     unsigned int spare_cs;
0222 };
0223 
0224 static struct anand *to_anand(struct nand_chip *nand)
0225 {
0226     return container_of(nand, struct anand, chip);
0227 }
0228 
0229 static struct arasan_nfc *to_anfc(struct nand_controller *ctrl)
0230 {
0231     return container_of(ctrl, struct arasan_nfc, controller);
0232 }
0233 
0234 static int anfc_wait_for_event(struct arasan_nfc *nfc, unsigned int event)
0235 {
0236     u32 val;
0237     int ret;
0238 
0239     ret = readl_relaxed_poll_timeout(nfc->base + INTR_STS_REG, val,
0240                      val & event, 0,
0241                      ANFC_DFLT_TIMEOUT_US);
0242     if (ret) {
0243         dev_err(nfc->dev, "Timeout waiting for event 0x%x\n", event);
0244         return -ETIMEDOUT;
0245     }
0246 
0247     writel_relaxed(event, nfc->base + INTR_STS_REG);
0248 
0249     return 0;
0250 }
0251 
0252 static int anfc_wait_for_rb(struct arasan_nfc *nfc, struct nand_chip *chip,
0253                 unsigned int timeout_ms)
0254 {
0255     struct anand *anand = to_anand(chip);
0256     u32 val;
0257     int ret;
0258 
0259     /* There is no R/B interrupt, we must poll a register */
0260     ret = readl_relaxed_poll_timeout(nfc->base + READY_STS_REG, val,
0261                      val & BIT(anand->rb),
0262                      1, timeout_ms * 1000);
0263     if (ret) {
0264         dev_err(nfc->dev, "Timeout waiting for R/B 0x%x\n",
0265             readl_relaxed(nfc->base + READY_STS_REG));
0266         return -ETIMEDOUT;
0267     }
0268 
0269     return 0;
0270 }
0271 
0272 static void anfc_trigger_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op)
0273 {
0274     writel_relaxed(nfc_op->pkt_reg, nfc->base + PKT_REG);
0275     writel_relaxed(nfc_op->addr1_reg, nfc->base + MEM_ADDR1_REG);
0276     writel_relaxed(nfc_op->addr2_reg, nfc->base + MEM_ADDR2_REG);
0277     writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG);
0278     writel_relaxed(nfc_op->prog_reg, nfc->base + PROG_REG);
0279 }
0280 
0281 static int anfc_pkt_len_config(unsigned int len, unsigned int *steps,
0282                    unsigned int *pktsize)
0283 {
0284     unsigned int nb, sz;
0285 
0286     for (nb = 1; nb < ANFC_MAX_STEPS; nb *= 2) {
0287         sz = len / nb;
0288         if (sz <= ANFC_MAX_PKT_SIZE)
0289             break;
0290     }
0291 
0292     if (sz * nb != len)
0293         return -ENOTSUPP;
0294 
0295     if (steps)
0296         *steps = nb;
0297 
0298     if (pktsize)
0299         *pktsize = sz;
0300 
0301     return 0;
0302 }
0303 
0304 static bool anfc_is_gpio_cs(struct arasan_nfc *nfc, int nfc_cs)
0305 {
0306     return nfc_cs >= 0 && nfc->cs_array[nfc_cs];
0307 }
0308 
0309 static int anfc_relative_to_absolute_cs(struct anand *anand, int num)
0310 {
0311     return anand->cs_idx[num];
0312 }
0313 
0314 static void anfc_assert_cs(struct arasan_nfc *nfc, unsigned int nfc_cs_idx)
0315 {
0316     /* CS did not change: do nothing */
0317     if (nfc->cur_cs == nfc_cs_idx)
0318         return;
0319 
0320     /* Deassert the previous CS if it was a GPIO */
0321     if (anfc_is_gpio_cs(nfc, nfc->cur_cs))
0322         gpiod_set_value_cansleep(nfc->cs_array[nfc->cur_cs], 1);
0323 
0324     /* Assert the new one */
0325     if (anfc_is_gpio_cs(nfc, nfc_cs_idx)) {
0326         nfc->native_cs = nfc->spare_cs;
0327         gpiod_set_value_cansleep(nfc->cs_array[nfc_cs_idx], 0);
0328     } else {
0329         nfc->native_cs = nfc_cs_idx;
0330     }
0331 
0332     nfc->cur_cs = nfc_cs_idx;
0333 }
0334 
0335 static int anfc_select_target(struct nand_chip *chip, int target)
0336 {
0337     struct anand *anand = to_anand(chip);
0338     struct arasan_nfc *nfc = to_anfc(chip->controller);
0339     unsigned int nfc_cs_idx = anfc_relative_to_absolute_cs(anand, target);
0340     int ret;
0341 
0342     anfc_assert_cs(nfc, nfc_cs_idx);
0343 
0344     /* Update the controller timings and the potential ECC configuration */
0345     writel_relaxed(anand->data_iface, nfc->base + DATA_INTERFACE_REG);
0346     writel_relaxed(anand->timings, nfc->base + TIMING_REG);
0347 
0348     /* Update clock frequency */
0349     if (nfc->cur_clk != anand->clk) {
0350         clk_disable_unprepare(nfc->bus_clk);
0351         ret = clk_set_rate(nfc->bus_clk, anand->clk);
0352         if (ret) {
0353             dev_err(nfc->dev, "Failed to change clock rate\n");
0354             return ret;
0355         }
0356 
0357         ret = clk_prepare_enable(nfc->bus_clk);
0358         if (ret) {
0359             dev_err(nfc->dev,
0360                 "Failed to re-enable the bus clock\n");
0361             return ret;
0362         }
0363 
0364         nfc->cur_clk = anand->clk;
0365     }
0366 
0367     return 0;
0368 }
0369 
0370 /*
0371  * When using the embedded hardware ECC engine, the controller is in charge of
0372  * feeding the engine with, first, the ECC residue present in the data array.
0373  * A typical read operation is:
0374  * 1/ Assert the read operation by sending the relevant command/address cycles
0375  *    but targeting the column of the first ECC bytes in the OOB area instead of
0376  *    the main data directly.
0377  * 2/ After having read the relevant number of ECC bytes, the controller uses
0378  *    the RNDOUT/RNDSTART commands which are set into the "ECC Spare Command
0379  *    Register" to move the pointer back at the beginning of the main data.
0380  * 3/ It will read the content of the main area for a given size (pktsize) and
0381  *    will feed the ECC engine with this buffer again.
0382  * 4/ The ECC engine derives the ECC bytes for the given data and compare them
0383  *    with the ones already received. It eventually trigger status flags and
0384  *    then set the "Buffer Read Ready" flag.
0385  * 5/ The corrected data is then available for reading from the data port
0386  *    register.
0387  *
0388  * The hardware BCH ECC engine is known to be inconstent in BCH mode and never
0389  * reports uncorrectable errors. Because of this bug, we have to use the
0390  * software BCH implementation in the read path.
0391  */
0392 static int anfc_read_page_hw_ecc(struct nand_chip *chip, u8 *buf,
0393                  int oob_required, int page)
0394 {
0395     struct arasan_nfc *nfc = to_anfc(chip->controller);
0396     struct mtd_info *mtd = nand_to_mtd(chip);
0397     struct anand *anand = to_anand(chip);
0398     unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0);
0399     unsigned int max_bitflips = 0;
0400     dma_addr_t dma_addr;
0401     int step, ret;
0402     struct anfc_op nfc_op = {
0403         .pkt_reg =
0404             PKT_SIZE(chip->ecc.size) |
0405             PKT_STEPS(chip->ecc.steps),
0406         .addr1_reg =
0407             (page & 0xFF) << (8 * (anand->caddr_cycles)) |
0408             (((page >> 8) & 0xFF) << (8 * (1 + anand->caddr_cycles))),
0409         .addr2_reg =
0410             ((page >> 16) & 0xFF) |
0411             ADDR2_STRENGTH(anand->strength) |
0412             ADDR2_CS(nfc->native_cs),
0413         .cmd_reg =
0414             CMD_1(NAND_CMD_READ0) |
0415             CMD_2(NAND_CMD_READSTART) |
0416             CMD_PAGE_SIZE(anand->page_sz) |
0417             CMD_DMA_ENABLE |
0418             CMD_NADDRS(anand->caddr_cycles +
0419                    anand->raddr_cycles),
0420         .prog_reg = PROG_PGRD,
0421     };
0422 
0423     dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_FROM_DEVICE);
0424     if (dma_mapping_error(nfc->dev, dma_addr)) {
0425         dev_err(nfc->dev, "Buffer mapping error");
0426         return -EIO;
0427     }
0428 
0429     writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);
0430     writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG);
0431 
0432     anfc_trigger_op(nfc, &nfc_op);
0433 
0434     ret = anfc_wait_for_event(nfc, XFER_COMPLETE);
0435     dma_unmap_single(nfc->dev, dma_addr, len, DMA_FROM_DEVICE);
0436     if (ret) {
0437         dev_err(nfc->dev, "Error reading page %d\n", page);
0438         return ret;
0439     }
0440 
0441     /* Store the raw OOB bytes as well */
0442     ret = nand_change_read_column_op(chip, mtd->writesize, chip->oob_poi,
0443                      mtd->oobsize, 0);
0444     if (ret)
0445         return ret;
0446 
0447     /*
0448      * For each step, compute by softare the BCH syndrome over the raw data.
0449      * Compare the theoretical amount of errors and compare with the
0450      * hardware engine feedback.
0451      */
0452     for (step = 0; step < chip->ecc.steps; step++) {
0453         u8 *raw_buf = &buf[step * chip->ecc.size];
0454         unsigned int bit, byte;
0455         int bf, i;
0456 
0457         /* Extract the syndrome, it is not necessarily aligned */
0458         memset(anand->hw_ecc, 0, chip->ecc.bytes);
0459         nand_extract_bits(anand->hw_ecc, 0,
0460                   &chip->oob_poi[mtd->oobsize - anand->ecc_total],
0461                   anand->ecc_bits * step, anand->ecc_bits);
0462 
0463         bf = bch_decode(anand->bch, raw_buf, chip->ecc.size,
0464                 anand->hw_ecc, NULL, NULL, anand->errloc);
0465         if (!bf) {
0466             continue;
0467         } else if (bf > 0) {
0468             for (i = 0; i < bf; i++) {
0469                 /* Only correct the data, not the syndrome */
0470                 if (anand->errloc[i] < (chip->ecc.size * 8)) {
0471                     bit = BIT(anand->errloc[i] & 7);
0472                     byte = anand->errloc[i] >> 3;
0473                     raw_buf[byte] ^= bit;
0474                 }
0475             }
0476 
0477             mtd->ecc_stats.corrected += bf;
0478             max_bitflips = max_t(unsigned int, max_bitflips, bf);
0479 
0480             continue;
0481         }
0482 
0483         bf = nand_check_erased_ecc_chunk(raw_buf, chip->ecc.size,
0484                          NULL, 0, NULL, 0,
0485                          chip->ecc.strength);
0486         if (bf > 0) {
0487             mtd->ecc_stats.corrected += bf;
0488             max_bitflips = max_t(unsigned int, max_bitflips, bf);
0489             memset(raw_buf, 0xFF, chip->ecc.size);
0490         } else if (bf < 0) {
0491             mtd->ecc_stats.failed++;
0492         }
0493     }
0494 
0495     return 0;
0496 }
0497 
0498 static int anfc_sel_read_page_hw_ecc(struct nand_chip *chip, u8 *buf,
0499                      int oob_required, int page)
0500 {
0501     int ret;
0502 
0503     ret = anfc_select_target(chip, chip->cur_cs);
0504     if (ret)
0505         return ret;
0506 
0507     return anfc_read_page_hw_ecc(chip, buf, oob_required, page);
0508 };
0509 
0510 static int anfc_write_page_hw_ecc(struct nand_chip *chip, const u8 *buf,
0511                   int oob_required, int page)
0512 {
0513     struct anand *anand = to_anand(chip);
0514     struct arasan_nfc *nfc = to_anfc(chip->controller);
0515     struct mtd_info *mtd = nand_to_mtd(chip);
0516     unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0);
0517     dma_addr_t dma_addr;
0518     int ret;
0519     struct anfc_op nfc_op = {
0520         .pkt_reg =
0521             PKT_SIZE(chip->ecc.size) |
0522             PKT_STEPS(chip->ecc.steps),
0523         .addr1_reg =
0524             (page & 0xFF) << (8 * (anand->caddr_cycles)) |
0525             (((page >> 8) & 0xFF) << (8 * (1 + anand->caddr_cycles))),
0526         .addr2_reg =
0527             ((page >> 16) & 0xFF) |
0528             ADDR2_STRENGTH(anand->strength) |
0529             ADDR2_CS(nfc->native_cs),
0530         .cmd_reg =
0531             CMD_1(NAND_CMD_SEQIN) |
0532             CMD_2(NAND_CMD_PAGEPROG) |
0533             CMD_PAGE_SIZE(anand->page_sz) |
0534             CMD_DMA_ENABLE |
0535             CMD_NADDRS(anand->caddr_cycles +
0536                    anand->raddr_cycles) |
0537             CMD_ECC_ENABLE,
0538         .prog_reg = PROG_PGPROG,
0539     };
0540 
0541     writel_relaxed(anand->ecc_conf, nfc->base + ECC_CONF_REG);
0542     writel_relaxed(ECC_SP_CMD1(NAND_CMD_RNDIN) |
0543                ECC_SP_ADDRS(anand->caddr_cycles),
0544                nfc->base + ECC_SP_REG);
0545 
0546     dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_TO_DEVICE);
0547     if (dma_mapping_error(nfc->dev, dma_addr)) {
0548         dev_err(nfc->dev, "Buffer mapping error");
0549         return -EIO;
0550     }
0551 
0552     writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);
0553     writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG);
0554 
0555     anfc_trigger_op(nfc, &nfc_op);
0556     ret = anfc_wait_for_event(nfc, XFER_COMPLETE);
0557     dma_unmap_single(nfc->dev, dma_addr, len, DMA_TO_DEVICE);
0558     if (ret) {
0559         dev_err(nfc->dev, "Error writing page %d\n", page);
0560         return ret;
0561     }
0562 
0563     /* Spare data is not protected */
0564     if (oob_required)
0565         ret = nand_write_oob_std(chip, page);
0566 
0567     return ret;
0568 }
0569 
0570 static int anfc_sel_write_page_hw_ecc(struct nand_chip *chip, const u8 *buf,
0571                       int oob_required, int page)
0572 {
0573     int ret;
0574 
0575     ret = anfc_select_target(chip, chip->cur_cs);
0576     if (ret)
0577         return ret;
0578 
0579     return anfc_write_page_hw_ecc(chip, buf, oob_required, page);
0580 };
0581 
0582 /* NAND framework ->exec_op() hooks and related helpers */
0583 static int anfc_parse_instructions(struct nand_chip *chip,
0584                    const struct nand_subop *subop,
0585                    struct anfc_op *nfc_op)
0586 {
0587     struct arasan_nfc *nfc = to_anfc(chip->controller);
0588     struct anand *anand = to_anand(chip);
0589     const struct nand_op_instr *instr = NULL;
0590     bool first_cmd = true;
0591     unsigned int op_id;
0592     int ret, i;
0593 
0594     memset(nfc_op, 0, sizeof(*nfc_op));
0595     nfc_op->addr2_reg = ADDR2_CS(nfc->native_cs);
0596     nfc_op->cmd_reg = CMD_PAGE_SIZE(anand->page_sz);
0597 
0598     for (op_id = 0; op_id < subop->ninstrs; op_id++) {
0599         unsigned int offset, naddrs, pktsize;
0600         const u8 *addrs;
0601         u8 *buf;
0602 
0603         instr = &subop->instrs[op_id];
0604 
0605         switch (instr->type) {
0606         case NAND_OP_CMD_INSTR:
0607             if (first_cmd)
0608                 nfc_op->cmd_reg |= CMD_1(instr->ctx.cmd.opcode);
0609             else
0610                 nfc_op->cmd_reg |= CMD_2(instr->ctx.cmd.opcode);
0611 
0612             first_cmd = false;
0613             break;
0614 
0615         case NAND_OP_ADDR_INSTR:
0616             offset = nand_subop_get_addr_start_off(subop, op_id);
0617             naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
0618             addrs = &instr->ctx.addr.addrs[offset];
0619             nfc_op->cmd_reg |= CMD_NADDRS(naddrs);
0620 
0621             for (i = 0; i < min(ANFC_MAX_ADDR_CYC, naddrs); i++) {
0622                 if (i < 4)
0623                     nfc_op->addr1_reg |= (u32)addrs[i] << i * 8;
0624                 else
0625                     nfc_op->addr2_reg |= addrs[i];
0626             }
0627 
0628             break;
0629         case NAND_OP_DATA_IN_INSTR:
0630             nfc_op->read = true;
0631             fallthrough;
0632         case NAND_OP_DATA_OUT_INSTR:
0633             offset = nand_subop_get_data_start_off(subop, op_id);
0634             buf = instr->ctx.data.buf.in;
0635             nfc_op->buf = &buf[offset];
0636             nfc_op->len = nand_subop_get_data_len(subop, op_id);
0637             ret = anfc_pkt_len_config(nfc_op->len, &nfc_op->steps,
0638                           &pktsize);
0639             if (ret)
0640                 return ret;
0641 
0642             /*
0643              * Number of DATA cycles must be aligned on 4, this
0644              * means the controller might read/write more than
0645              * requested. This is harmless most of the time as extra
0646              * DATA are discarded in the write path and read pointer
0647              * adjusted in the read path.
0648              *
0649              * FIXME: The core should mark operations where
0650              * reading/writing more is allowed so the exec_op()
0651              * implementation can take the right decision when the
0652              * alignment constraint is not met: adjust the number of
0653              * DATA cycles when it's allowed, reject the operation
0654              * otherwise.
0655              */
0656             nfc_op->pkt_reg |= PKT_SIZE(round_up(pktsize, 4)) |
0657                        PKT_STEPS(nfc_op->steps);
0658             break;
0659         case NAND_OP_WAITRDY_INSTR:
0660             nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms;
0661             break;
0662         }
0663     }
0664 
0665     return 0;
0666 }
0667 
0668 static int anfc_rw_pio_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op)
0669 {
0670     unsigned int dwords = (nfc_op->len / 4) / nfc_op->steps;
0671     unsigned int last_len = nfc_op->len % 4;
0672     unsigned int offset, dir;
0673     u8 *buf = nfc_op->buf;
0674     int ret, i;
0675 
0676     for (i = 0; i < nfc_op->steps; i++) {
0677         dir = nfc_op->read ? READ_READY : WRITE_READY;
0678         ret = anfc_wait_for_event(nfc, dir);
0679         if (ret) {
0680             dev_err(nfc->dev, "PIO %s ready signal not received\n",
0681                 nfc_op->read ? "Read" : "Write");
0682             return ret;
0683         }
0684 
0685         offset = i * (dwords * 4);
0686         if (nfc_op->read)
0687             ioread32_rep(nfc->base + DATA_PORT_REG, &buf[offset],
0688                      dwords);
0689         else
0690             iowrite32_rep(nfc->base + DATA_PORT_REG, &buf[offset],
0691                       dwords);
0692     }
0693 
0694     if (last_len) {
0695         u32 remainder;
0696 
0697         offset = nfc_op->len - last_len;
0698 
0699         if (nfc_op->read) {
0700             remainder = readl_relaxed(nfc->base + DATA_PORT_REG);
0701             memcpy(&buf[offset], &remainder, last_len);
0702         } else {
0703             memcpy(&remainder, &buf[offset], last_len);
0704             writel_relaxed(remainder, nfc->base + DATA_PORT_REG);
0705         }
0706     }
0707 
0708     return anfc_wait_for_event(nfc, XFER_COMPLETE);
0709 }
0710 
0711 static int anfc_misc_data_type_exec(struct nand_chip *chip,
0712                     const struct nand_subop *subop,
0713                     u32 prog_reg)
0714 {
0715     struct arasan_nfc *nfc = to_anfc(chip->controller);
0716     struct anfc_op nfc_op = {};
0717     int ret;
0718 
0719     ret = anfc_parse_instructions(chip, subop, &nfc_op);
0720     if (ret)
0721         return ret;
0722 
0723     nfc_op.prog_reg = prog_reg;
0724     anfc_trigger_op(nfc, &nfc_op);
0725 
0726     if (nfc_op.rdy_timeout_ms) {
0727         ret = anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
0728         if (ret)
0729             return ret;
0730     }
0731 
0732     return anfc_rw_pio_op(nfc, &nfc_op);
0733 }
0734 
0735 static int anfc_param_read_type_exec(struct nand_chip *chip,
0736                      const struct nand_subop *subop)
0737 {
0738     return anfc_misc_data_type_exec(chip, subop, PROG_RDPARAM);
0739 }
0740 
0741 static int anfc_data_read_type_exec(struct nand_chip *chip,
0742                     const struct nand_subop *subop)
0743 {
0744     u32 prog_reg = PROG_PGRD;
0745 
0746     /*
0747      * Experience shows that while in SDR mode sending a CHANGE READ COLUMN
0748      * command through the READ PAGE "type" always works fine, when in
0749      * NV-DDR mode the same command simply fails. However, it was also
0750      * spotted that any CHANGE READ COLUMN command sent through the CHANGE
0751      * READ COLUMN ENHANCED "type" would correctly work in both cases (SDR
0752      * and NV-DDR). So, for simplicity, let's program the controller with
0753      * the CHANGE READ COLUMN ENHANCED "type" whenever we are requested to
0754      * perform a CHANGE READ COLUMN operation.
0755      */
0756     if (subop->instrs[0].ctx.cmd.opcode == NAND_CMD_RNDOUT &&
0757         subop->instrs[2].ctx.cmd.opcode == NAND_CMD_RNDOUTSTART)
0758         prog_reg = PROG_CHG_RD_COL_ENH;
0759 
0760     return anfc_misc_data_type_exec(chip, subop, prog_reg);
0761 }
0762 
0763 static int anfc_param_write_type_exec(struct nand_chip *chip,
0764                       const struct nand_subop *subop)
0765 {
0766     return anfc_misc_data_type_exec(chip, subop, PROG_SET_FEATURE);
0767 }
0768 
0769 static int anfc_data_write_type_exec(struct nand_chip *chip,
0770                      const struct nand_subop *subop)
0771 {
0772     return anfc_misc_data_type_exec(chip, subop, PROG_PGPROG);
0773 }
0774 
0775 static int anfc_misc_zerolen_type_exec(struct nand_chip *chip,
0776                        const struct nand_subop *subop,
0777                        u32 prog_reg)
0778 {
0779     struct arasan_nfc *nfc = to_anfc(chip->controller);
0780     struct anfc_op nfc_op = {};
0781     int ret;
0782 
0783     ret = anfc_parse_instructions(chip, subop, &nfc_op);
0784     if (ret)
0785         return ret;
0786 
0787     nfc_op.prog_reg = prog_reg;
0788     anfc_trigger_op(nfc, &nfc_op);
0789 
0790     ret = anfc_wait_for_event(nfc, XFER_COMPLETE);
0791     if (ret)
0792         return ret;
0793 
0794     if (nfc_op.rdy_timeout_ms)
0795         ret = anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
0796 
0797     return ret;
0798 }
0799 
0800 static int anfc_status_type_exec(struct nand_chip *chip,
0801                  const struct nand_subop *subop)
0802 {
0803     struct arasan_nfc *nfc = to_anfc(chip->controller);
0804     u32 tmp;
0805     int ret;
0806 
0807     /* See anfc_check_op() for details about this constraint */
0808     if (subop->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS)
0809         return -ENOTSUPP;
0810 
0811     ret = anfc_misc_zerolen_type_exec(chip, subop, PROG_STATUS);
0812     if (ret)
0813         return ret;
0814 
0815     tmp = readl_relaxed(nfc->base + FLASH_STS_REG);
0816     memcpy(subop->instrs[1].ctx.data.buf.in, &tmp, 1);
0817 
0818     return 0;
0819 }
0820 
0821 static int anfc_reset_type_exec(struct nand_chip *chip,
0822                 const struct nand_subop *subop)
0823 {
0824     return anfc_misc_zerolen_type_exec(chip, subop, PROG_RST);
0825 }
0826 
0827 static int anfc_erase_type_exec(struct nand_chip *chip,
0828                 const struct nand_subop *subop)
0829 {
0830     return anfc_misc_zerolen_type_exec(chip, subop, PROG_ERASE);
0831 }
0832 
0833 static int anfc_wait_type_exec(struct nand_chip *chip,
0834                    const struct nand_subop *subop)
0835 {
0836     struct arasan_nfc *nfc = to_anfc(chip->controller);
0837     struct anfc_op nfc_op = {};
0838     int ret;
0839 
0840     ret = anfc_parse_instructions(chip, subop, &nfc_op);
0841     if (ret)
0842         return ret;
0843 
0844     return anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
0845 }
0846 
0847 static const struct nand_op_parser anfc_op_parser = NAND_OP_PARSER(
0848     NAND_OP_PARSER_PATTERN(
0849         anfc_param_read_type_exec,
0850         NAND_OP_PARSER_PAT_CMD_ELEM(false),
0851         NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
0852         NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
0853         NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, ANFC_MAX_CHUNK_SIZE)),
0854     NAND_OP_PARSER_PATTERN(
0855         anfc_param_write_type_exec,
0856         NAND_OP_PARSER_PAT_CMD_ELEM(false),
0857         NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
0858         NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, ANFC_MAX_PARAM_SIZE)),
0859     NAND_OP_PARSER_PATTERN(
0860         anfc_data_read_type_exec,
0861         NAND_OP_PARSER_PAT_CMD_ELEM(false),
0862         NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
0863         NAND_OP_PARSER_PAT_CMD_ELEM(false),
0864         NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
0865         NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, ANFC_MAX_CHUNK_SIZE)),
0866     NAND_OP_PARSER_PATTERN(
0867         anfc_data_write_type_exec,
0868         NAND_OP_PARSER_PAT_CMD_ELEM(false),
0869         NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
0870         NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, ANFC_MAX_CHUNK_SIZE),
0871         NAND_OP_PARSER_PAT_CMD_ELEM(false)),
0872     NAND_OP_PARSER_PATTERN(
0873         anfc_reset_type_exec,
0874         NAND_OP_PARSER_PAT_CMD_ELEM(false),
0875         NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
0876     NAND_OP_PARSER_PATTERN(
0877         anfc_erase_type_exec,
0878         NAND_OP_PARSER_PAT_CMD_ELEM(false),
0879         NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
0880         NAND_OP_PARSER_PAT_CMD_ELEM(false),
0881         NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
0882     NAND_OP_PARSER_PATTERN(
0883         anfc_status_type_exec,
0884         NAND_OP_PARSER_PAT_CMD_ELEM(false),
0885         NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, ANFC_MAX_CHUNK_SIZE)),
0886     NAND_OP_PARSER_PATTERN(
0887         anfc_wait_type_exec,
0888         NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
0889     );
0890 
0891 static int anfc_check_op(struct nand_chip *chip,
0892              const struct nand_operation *op)
0893 {
0894     const struct nand_op_instr *instr;
0895     int op_id;
0896 
0897     /*
0898      * The controller abstracts all the NAND operations and do not support
0899      * data only operations.
0900      *
0901      * TODO: The nand_op_parser framework should be extended to
0902      * support custom checks on DATA instructions.
0903      */
0904     for (op_id = 0; op_id < op->ninstrs; op_id++) {
0905         instr = &op->instrs[op_id];
0906 
0907         switch (instr->type) {
0908         case NAND_OP_ADDR_INSTR:
0909             if (instr->ctx.addr.naddrs > ANFC_MAX_ADDR_CYC)
0910                 return -ENOTSUPP;
0911 
0912             break;
0913         case NAND_OP_DATA_IN_INSTR:
0914         case NAND_OP_DATA_OUT_INSTR:
0915             if (instr->ctx.data.len > ANFC_MAX_CHUNK_SIZE)
0916                 return -ENOTSUPP;
0917 
0918             if (anfc_pkt_len_config(instr->ctx.data.len, 0, 0))
0919                 return -ENOTSUPP;
0920 
0921             break;
0922         default:
0923             break;
0924         }
0925     }
0926 
0927     /*
0928      * The controller does not allow to proceed with a CMD+DATA_IN cycle
0929      * manually on the bus by reading data from the data register. Instead,
0930      * the controller abstract a status read operation with its own status
0931      * register after ordering a read status operation. Hence, we cannot
0932      * support any CMD+DATA_IN operation other than a READ STATUS.
0933      *
0934      * TODO: The nand_op_parser() framework should be extended to describe
0935      * fixed patterns instead of open-coding this check here.
0936      */
0937     if (op->ninstrs == 2 &&
0938         op->instrs[0].type == NAND_OP_CMD_INSTR &&
0939         op->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS &&
0940         op->instrs[1].type == NAND_OP_DATA_IN_INSTR)
0941         return -ENOTSUPP;
0942 
0943     return nand_op_parser_exec_op(chip, &anfc_op_parser, op, true);
0944 }
0945 
0946 static int anfc_exec_op(struct nand_chip *chip,
0947             const struct nand_operation *op,
0948             bool check_only)
0949 {
0950     int ret;
0951 
0952     if (check_only)
0953         return anfc_check_op(chip, op);
0954 
0955     ret = anfc_select_target(chip, op->cs);
0956     if (ret)
0957         return ret;
0958 
0959     return nand_op_parser_exec_op(chip, &anfc_op_parser, op, check_only);
0960 }
0961 
0962 static int anfc_setup_interface(struct nand_chip *chip, int target,
0963                 const struct nand_interface_config *conf)
0964 {
0965     struct anand *anand = to_anand(chip);
0966     struct arasan_nfc *nfc = to_anfc(chip->controller);
0967     struct device_node *np = nfc->dev->of_node;
0968     const struct nand_sdr_timings *sdr;
0969     const struct nand_nvddr_timings *nvddr;
0970     unsigned int tccs_min, dqs_mode, fast_tcad;
0971 
0972     if (nand_interface_is_nvddr(conf)) {
0973         nvddr = nand_get_nvddr_timings(conf);
0974         if (IS_ERR(nvddr))
0975             return PTR_ERR(nvddr);
0976 
0977         /*
0978          * The controller only supports data payload requests which are
0979          * a multiple of 4. In practice, most data accesses are 4-byte
0980          * aligned and this is not an issue. However, rounding up will
0981          * simply be refused by the controller if we reached the end of
0982          * the device *and* we are using the NV-DDR interface(!). In
0983          * this situation, unaligned data requests ending at the device
0984          * boundary will confuse the controller and cannot be performed.
0985          *
0986          * This is something that happens in nand_read_subpage() when
0987          * selecting software ECC support and must be avoided.
0988          */
0989         if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT)
0990             return -ENOTSUPP;
0991     } else {
0992         sdr = nand_get_sdr_timings(conf);
0993         if (IS_ERR(sdr))
0994             return PTR_ERR(sdr);
0995     }
0996 
0997     if (target < 0)
0998         return 0;
0999 
1000     if (nand_interface_is_sdr(conf)) {
1001         anand->data_iface = DIFACE_SDR |
1002                     DIFACE_SDR_MODE(conf->timings.mode);
1003         anand->timings = 0;
1004     } else {
1005         anand->data_iface = DIFACE_NVDDR |
1006                     DIFACE_DDR_MODE(conf->timings.mode);
1007 
1008         if (conf->timings.nvddr.tCCS_min <= 100000)
1009             tccs_min = TCCS_TIME_100NS;
1010         else if (conf->timings.nvddr.tCCS_min <= 200000)
1011             tccs_min = TCCS_TIME_200NS;
1012         else if (conf->timings.nvddr.tCCS_min <= 300000)
1013             tccs_min = TCCS_TIME_300NS;
1014         else
1015             tccs_min = TCCS_TIME_500NS;
1016 
1017         fast_tcad = 0;
1018         if (conf->timings.nvddr.tCAD_min < 45000)
1019             fast_tcad = FAST_TCAD;
1020 
1021         switch (conf->timings.mode) {
1022         case 5:
1023         case 4:
1024             dqs_mode = 2;
1025             break;
1026         case 3:
1027             dqs_mode = 3;
1028             break;
1029         case 2:
1030             dqs_mode = 4;
1031             break;
1032         case 1:
1033             dqs_mode = 5;
1034             break;
1035         case 0:
1036         default:
1037             dqs_mode = 6;
1038             break;
1039         }
1040 
1041         anand->timings = tccs_min | fast_tcad |
1042                  DQS_BUFF_SEL_IN(dqs_mode) |
1043                  DQS_BUFF_SEL_OUT(dqs_mode);
1044     }
1045 
1046     if (nand_interface_is_sdr(conf)) {
1047         anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;
1048     } else {
1049         /* ONFI timings are defined in picoseconds */
1050         anand->clk = div_u64((u64)NSEC_PER_SEC * 1000,
1051                      conf->timings.nvddr.tCK_min);
1052     }
1053 
1054     /*
1055      * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work
1056      * with f > 90MHz (default clock is 100MHz) but signals are unstable
1057      * with higher modes. Hence we decrease a little bit the clock rate to
1058      * 80MHz when using SDR modes 2-5 with this SoC.
1059      */
1060     if (of_device_is_compatible(np, "xlnx,zynqmp-nand-controller") &&
1061         nand_interface_is_sdr(conf) && conf->timings.mode >= 2)
1062         anand->clk = ANFC_XLNX_SDR_HS_CORE_CLK;
1063 
1064     return 0;
1065 }
1066 
1067 static int anfc_calc_hw_ecc_bytes(int step_size, int strength)
1068 {
1069     unsigned int bch_gf_mag, ecc_bits;
1070 
1071     switch (step_size) {
1072     case SZ_512:
1073         bch_gf_mag = 13;
1074         break;
1075     case SZ_1K:
1076         bch_gf_mag = 14;
1077         break;
1078     default:
1079         return -EINVAL;
1080     }
1081 
1082     ecc_bits = bch_gf_mag * strength;
1083 
1084     return DIV_ROUND_UP(ecc_bits, 8);
1085 }
1086 
1087 static const int anfc_hw_ecc_512_strengths[] = {4, 8, 12};
1088 
1089 static const int anfc_hw_ecc_1024_strengths[] = {24};
1090 
1091 static const struct nand_ecc_step_info anfc_hw_ecc_step_infos[] = {
1092     {
1093         .stepsize = SZ_512,
1094         .strengths = anfc_hw_ecc_512_strengths,
1095         .nstrengths = ARRAY_SIZE(anfc_hw_ecc_512_strengths),
1096     },
1097     {
1098         .stepsize = SZ_1K,
1099         .strengths = anfc_hw_ecc_1024_strengths,
1100         .nstrengths = ARRAY_SIZE(anfc_hw_ecc_1024_strengths),
1101     },
1102 };
1103 
1104 static const struct nand_ecc_caps anfc_hw_ecc_caps = {
1105     .stepinfos = anfc_hw_ecc_step_infos,
1106     .nstepinfos = ARRAY_SIZE(anfc_hw_ecc_step_infos),
1107     .calc_ecc_bytes = anfc_calc_hw_ecc_bytes,
1108 };
1109 
1110 static int anfc_init_hw_ecc_controller(struct arasan_nfc *nfc,
1111                        struct nand_chip *chip)
1112 {
1113     struct anand *anand = to_anand(chip);
1114     struct mtd_info *mtd = nand_to_mtd(chip);
1115     struct nand_ecc_ctrl *ecc = &chip->ecc;
1116     unsigned int bch_prim_poly = 0, bch_gf_mag = 0, ecc_offset;
1117     int ret;
1118 
1119     switch (mtd->writesize) {
1120     case SZ_512:
1121     case SZ_2K:
1122     case SZ_4K:
1123     case SZ_8K:
1124     case SZ_16K:
1125         break;
1126     default:
1127         dev_err(nfc->dev, "Unsupported page size %d\n", mtd->writesize);
1128         return -EINVAL;
1129     }
1130 
1131     ret = nand_ecc_choose_conf(chip, &anfc_hw_ecc_caps, mtd->oobsize);
1132     if (ret)
1133         return ret;
1134 
1135     switch (ecc->strength) {
1136     case 12:
1137         anand->strength = 0x1;
1138         break;
1139     case 8:
1140         anand->strength = 0x2;
1141         break;
1142     case 4:
1143         anand->strength = 0x3;
1144         break;
1145     case 24:
1146         anand->strength = 0x4;
1147         break;
1148     default:
1149         dev_err(nfc->dev, "Unsupported strength %d\n", ecc->strength);
1150         return -EINVAL;
1151     }
1152 
1153     switch (ecc->size) {
1154     case SZ_512:
1155         bch_gf_mag = 13;
1156         bch_prim_poly = 0x201b;
1157         break;
1158     case SZ_1K:
1159         bch_gf_mag = 14;
1160         bch_prim_poly = 0x4443;
1161         break;
1162     default:
1163         dev_err(nfc->dev, "Unsupported step size %d\n", ecc->strength);
1164         return -EINVAL;
1165     }
1166 
1167     mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
1168 
1169     ecc->steps = mtd->writesize / ecc->size;
1170     ecc->algo = NAND_ECC_ALGO_BCH;
1171     anand->ecc_bits = bch_gf_mag * ecc->strength;
1172     ecc->bytes = DIV_ROUND_UP(anand->ecc_bits, 8);
1173     anand->ecc_total = DIV_ROUND_UP(anand->ecc_bits * ecc->steps, 8);
1174     ecc_offset = mtd->writesize + mtd->oobsize - anand->ecc_total;
1175     anand->ecc_conf = ECC_CONF_COL(ecc_offset) |
1176               ECC_CONF_LEN(anand->ecc_total) |
1177               ECC_CONF_BCH_EN;
1178 
1179     anand->errloc = devm_kmalloc_array(nfc->dev, ecc->strength,
1180                        sizeof(*anand->errloc), GFP_KERNEL);
1181     if (!anand->errloc)
1182         return -ENOMEM;
1183 
1184     anand->hw_ecc = devm_kmalloc(nfc->dev, ecc->bytes, GFP_KERNEL);
1185     if (!anand->hw_ecc)
1186         return -ENOMEM;
1187 
1188     /* Enforce bit swapping to fit the hardware */
1189     anand->bch = bch_init(bch_gf_mag, ecc->strength, bch_prim_poly, true);
1190     if (!anand->bch)
1191         return -EINVAL;
1192 
1193     ecc->read_page = anfc_sel_read_page_hw_ecc;
1194     ecc->write_page = anfc_sel_write_page_hw_ecc;
1195 
1196     return 0;
1197 }
1198 
1199 static int anfc_attach_chip(struct nand_chip *chip)
1200 {
1201     struct anand *anand = to_anand(chip);
1202     struct arasan_nfc *nfc = to_anfc(chip->controller);
1203     struct mtd_info *mtd = nand_to_mtd(chip);
1204     int ret = 0;
1205 
1206     if (mtd->writesize <= SZ_512)
1207         anand->caddr_cycles = 1;
1208     else
1209         anand->caddr_cycles = 2;
1210 
1211     if (chip->options & NAND_ROW_ADDR_3)
1212         anand->raddr_cycles = 3;
1213     else
1214         anand->raddr_cycles = 2;
1215 
1216     switch (mtd->writesize) {
1217     case 512:
1218         anand->page_sz = 0;
1219         break;
1220     case 1024:
1221         anand->page_sz = 5;
1222         break;
1223     case 2048:
1224         anand->page_sz = 1;
1225         break;
1226     case 4096:
1227         anand->page_sz = 2;
1228         break;
1229     case 8192:
1230         anand->page_sz = 3;
1231         break;
1232     case 16384:
1233         anand->page_sz = 4;
1234         break;
1235     default:
1236         return -EINVAL;
1237     }
1238 
1239     /* These hooks are valid for all ECC providers */
1240     chip->ecc.read_page_raw = nand_monolithic_read_page_raw;
1241     chip->ecc.write_page_raw = nand_monolithic_write_page_raw;
1242 
1243     switch (chip->ecc.engine_type) {
1244     case NAND_ECC_ENGINE_TYPE_NONE:
1245     case NAND_ECC_ENGINE_TYPE_SOFT:
1246     case NAND_ECC_ENGINE_TYPE_ON_DIE:
1247         break;
1248     case NAND_ECC_ENGINE_TYPE_ON_HOST:
1249         ret = anfc_init_hw_ecc_controller(nfc, chip);
1250         break;
1251     default:
1252         dev_err(nfc->dev, "Unsupported ECC mode: %d\n",
1253             chip->ecc.engine_type);
1254         return -EINVAL;
1255     }
1256 
1257     return ret;
1258 }
1259 
1260 static void anfc_detach_chip(struct nand_chip *chip)
1261 {
1262     struct anand *anand = to_anand(chip);
1263 
1264     if (anand->bch)
1265         bch_free(anand->bch);
1266 }
1267 
1268 static const struct nand_controller_ops anfc_ops = {
1269     .exec_op = anfc_exec_op,
1270     .setup_interface = anfc_setup_interface,
1271     .attach_chip = anfc_attach_chip,
1272     .detach_chip = anfc_detach_chip,
1273 };
1274 
1275 static int anfc_chip_init(struct arasan_nfc *nfc, struct device_node *np)
1276 {
1277     struct anand *anand;
1278     struct nand_chip *chip;
1279     struct mtd_info *mtd;
1280     int rb, ret, i;
1281 
1282     anand = devm_kzalloc(nfc->dev, sizeof(*anand), GFP_KERNEL);
1283     if (!anand)
1284         return -ENOMEM;
1285 
1286     /* Chip-select init */
1287     anand->ncs_idx = of_property_count_elems_of_size(np, "reg", sizeof(u32));
1288     if (anand->ncs_idx <= 0 || anand->ncs_idx > nfc->ncs) {
1289         dev_err(nfc->dev, "Invalid reg property\n");
1290         return -EINVAL;
1291     }
1292 
1293     anand->cs_idx = devm_kcalloc(nfc->dev, anand->ncs_idx,
1294                      sizeof(*anand->cs_idx), GFP_KERNEL);
1295     if (!anand->cs_idx)
1296         return -ENOMEM;
1297 
1298     for (i = 0; i < anand->ncs_idx; i++) {
1299         ret = of_property_read_u32_index(np, "reg", i,
1300                          &anand->cs_idx[i]);
1301         if (ret) {
1302             dev_err(nfc->dev, "invalid CS property: %d\n", ret);
1303             return ret;
1304         }
1305     }
1306 
1307     /* Ready-busy init */
1308     ret = of_property_read_u32(np, "nand-rb", &rb);
1309     if (ret)
1310         return ret;
1311 
1312     if (rb >= ANFC_MAX_CS) {
1313         dev_err(nfc->dev, "Wrong RB %d\n", rb);
1314         return -EINVAL;
1315     }
1316 
1317     anand->rb = rb;
1318 
1319     chip = &anand->chip;
1320     mtd = nand_to_mtd(chip);
1321     mtd->dev.parent = nfc->dev;
1322     chip->controller = &nfc->controller;
1323     chip->options = NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
1324             NAND_USES_DMA;
1325 
1326     nand_set_flash_node(chip, np);
1327     if (!mtd->name) {
1328         dev_err(nfc->dev, "NAND label property is mandatory\n");
1329         return -EINVAL;
1330     }
1331 
1332     ret = nand_scan(chip, anand->ncs_idx);
1333     if (ret) {
1334         dev_err(nfc->dev, "Scan operation failed\n");
1335         return ret;
1336     }
1337 
1338     ret = mtd_device_register(mtd, NULL, 0);
1339     if (ret) {
1340         nand_cleanup(chip);
1341         return ret;
1342     }
1343 
1344     list_add_tail(&anand->node, &nfc->chips);
1345 
1346     return 0;
1347 }
1348 
1349 static void anfc_chips_cleanup(struct arasan_nfc *nfc)
1350 {
1351     struct anand *anand, *tmp;
1352     struct nand_chip *chip;
1353     int ret;
1354 
1355     list_for_each_entry_safe(anand, tmp, &nfc->chips, node) {
1356         chip = &anand->chip;
1357         ret = mtd_device_unregister(nand_to_mtd(chip));
1358         WARN_ON(ret);
1359         nand_cleanup(chip);
1360         list_del(&anand->node);
1361     }
1362 }
1363 
1364 static int anfc_chips_init(struct arasan_nfc *nfc)
1365 {
1366     struct device_node *np = nfc->dev->of_node, *nand_np;
1367     int nchips = of_get_child_count(np);
1368     int ret;
1369 
1370     if (!nchips) {
1371         dev_err(nfc->dev, "Incorrect number of NAND chips (%d)\n",
1372             nchips);
1373         return -EINVAL;
1374     }
1375 
1376     for_each_child_of_node(np, nand_np) {
1377         ret = anfc_chip_init(nfc, nand_np);
1378         if (ret) {
1379             of_node_put(nand_np);
1380             anfc_chips_cleanup(nfc);
1381             break;
1382         }
1383     }
1384 
1385     return ret;
1386 }
1387 
1388 static void anfc_reset(struct arasan_nfc *nfc)
1389 {
1390     /* Disable interrupt signals */
1391     writel_relaxed(0, nfc->base + INTR_SIG_EN_REG);
1392 
1393     /* Enable interrupt status */
1394     writel_relaxed(EVENT_MASK, nfc->base + INTR_STS_EN_REG);
1395 
1396     nfc->cur_cs = -1;
1397 }
1398 
1399 static int anfc_parse_cs(struct arasan_nfc *nfc)
1400 {
1401     int ret;
1402 
1403     /* Check the gpio-cs property */
1404     ret = rawnand_dt_parse_gpio_cs(nfc->dev, &nfc->cs_array, &nfc->ncs);
1405     if (ret)
1406         return ret;
1407 
1408     /*
1409      * The controller native CS cannot be both disabled at the same time.
1410      * Hence, only one native CS can be used if GPIO CS are needed, so that
1411      * the other is selected when a non-native CS must be asserted (not
1412      * wired physically or configured as GPIO instead of NAND CS). In this
1413      * case, the "not" chosen CS is assigned to nfc->spare_cs and selected
1414      * whenever a GPIO CS must be asserted.
1415      */
1416     if (nfc->cs_array && nfc->ncs > 2) {
1417         if (!nfc->cs_array[0] && !nfc->cs_array[1]) {
1418             dev_err(nfc->dev,
1419                 "Assign a single native CS when using GPIOs\n");
1420             return -EINVAL;
1421         }
1422 
1423         if (nfc->cs_array[0])
1424             nfc->spare_cs = 0;
1425         else
1426             nfc->spare_cs = 1;
1427     }
1428 
1429     if (!nfc->cs_array) {
1430         nfc->cs_array = anfc_default_cs_array;
1431         nfc->ncs = ANFC_MAX_CS;
1432         return 0;
1433     }
1434 
1435     return 0;
1436 }
1437 
1438 static int anfc_probe(struct platform_device *pdev)
1439 {
1440     struct arasan_nfc *nfc;
1441     int ret;
1442 
1443     nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
1444     if (!nfc)
1445         return -ENOMEM;
1446 
1447     nfc->dev = &pdev->dev;
1448     nand_controller_init(&nfc->controller);
1449     nfc->controller.ops = &anfc_ops;
1450     INIT_LIST_HEAD(&nfc->chips);
1451 
1452     nfc->base = devm_platform_ioremap_resource(pdev, 0);
1453     if (IS_ERR(nfc->base))
1454         return PTR_ERR(nfc->base);
1455 
1456     anfc_reset(nfc);
1457 
1458     nfc->controller_clk = devm_clk_get(&pdev->dev, "controller");
1459     if (IS_ERR(nfc->controller_clk))
1460         return PTR_ERR(nfc->controller_clk);
1461 
1462     nfc->bus_clk = devm_clk_get(&pdev->dev, "bus");
1463     if (IS_ERR(nfc->bus_clk))
1464         return PTR_ERR(nfc->bus_clk);
1465 
1466     ret = clk_prepare_enable(nfc->controller_clk);
1467     if (ret)
1468         return ret;
1469 
1470     ret = clk_prepare_enable(nfc->bus_clk);
1471     if (ret)
1472         goto disable_controller_clk;
1473 
1474     ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1475     if (ret)
1476         goto disable_bus_clk;
1477 
1478     ret = anfc_parse_cs(nfc);
1479     if (ret)
1480         goto disable_bus_clk;
1481 
1482     ret = anfc_chips_init(nfc);
1483     if (ret)
1484         goto disable_bus_clk;
1485 
1486     platform_set_drvdata(pdev, nfc);
1487 
1488     return 0;
1489 
1490 disable_bus_clk:
1491     clk_disable_unprepare(nfc->bus_clk);
1492 
1493 disable_controller_clk:
1494     clk_disable_unprepare(nfc->controller_clk);
1495 
1496     return ret;
1497 }
1498 
1499 static int anfc_remove(struct platform_device *pdev)
1500 {
1501     struct arasan_nfc *nfc = platform_get_drvdata(pdev);
1502 
1503     anfc_chips_cleanup(nfc);
1504 
1505     clk_disable_unprepare(nfc->bus_clk);
1506     clk_disable_unprepare(nfc->controller_clk);
1507 
1508     return 0;
1509 }
1510 
1511 static const struct of_device_id anfc_ids[] = {
1512     {
1513         .compatible = "xlnx,zynqmp-nand-controller",
1514     },
1515     {
1516         .compatible = "arasan,nfc-v3p10",
1517     },
1518     {}
1519 };
1520 MODULE_DEVICE_TABLE(of, anfc_ids);
1521 
1522 static struct platform_driver anfc_driver = {
1523     .driver = {
1524         .name = "arasan-nand-controller",
1525         .of_match_table = anfc_ids,
1526     },
1527     .probe = anfc_probe,
1528     .remove = anfc_remove,
1529 };
1530 module_platform_driver(anfc_driver);
1531 
1532 MODULE_LICENSE("GPL v2");
1533 MODULE_AUTHOR("Punnaiah Choudary Kalluri <punnaia@xilinx.com>");
1534 MODULE_AUTHOR("Naga Sureshkumar Relli <nagasure@xilinx.com>");
1535 MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
1536 MODULE_DESCRIPTION("Arasan NAND Flash Controller Driver");
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