mtd/maps/physmap-ixp4xx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Intel IXP4xx OF physmap add-on
0004  * Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
0005  *
0006  * Based on the ixp4xx.c map driver, originally written by:
0007  * Intel Corporation
0008  * Deepak Saxena <dsaxena@mvista.com>
0009  * Copyright (C) 2002 Intel Corporation
0010  * Copyright (C) 2003-2004 MontaVista Software, Inc.
0011  */
0012 #include <linux/export.h>
0013 #include <linux/of.h>
0014 #include <linux/of_device.h>
0015 #include <linux/mtd/map.h>
0016 #include <linux/mtd/xip.h>
0017 #include "physmap-ixp4xx.h"
0018
0019 /*
0020  * Read/write a 16 bit word from flash address 'addr'.
0021  *
0022  * When the cpu is in little-endian mode it swizzles the address lines
0023  * ('address coherency') so we need to undo the swizzling to ensure commands
0024  * and the like end up on the correct flash address.
0025  *
0026  * To further complicate matters, due to the way the expansion bus controller
0027  * handles 32 bit reads, the byte stream ABCD is stored on the flash as:
0028  *     D15    D0
0029  *     +---+---+
0030  *     | A | B | 0
0031  *     +---+---+
0032  *     | C | D | 2
0033  *     +---+---+
0034  * This means that on LE systems each 16 bit word must be swapped. Note that
0035  * this requires CONFIG_MTD_CFI_BE_BYTE_SWAP to be enabled to 'unswap' the CFI
0036  * data and other flash commands which are always in D7-D0.
0037  */
0038 #ifndef CONFIG_CPU_BIG_ENDIAN
0039
0040 static inline u16 flash_read16(void __iomem *addr)
0041 {
0042     return be16_to_cpu(__raw_readw((void __iomem *)((unsigned long)addr ^ 0x2)));
0043 }
0044
0045 static inline void flash_write16(u16 d, void __iomem *addr)
0046 {
0047     __raw_writew(cpu_to_be16(d), (void __iomem *)((unsigned long)addr ^ 0x2));
0048 }
0049
0050 #define BYTE0(h)    ((h) & 0xFF)
0051 #define BYTE1(h)    (((h) >> 8) & 0xFF)
0052
0053 #else
0054
0055 static inline u16 flash_read16(const void __iomem *addr)
0056 {
0057     return __raw_readw(addr);
0058 }
0059
0060 static inline void flash_write16(u16 d, void __iomem *addr)
0061 {
0062     __raw_writew(d, addr);
0063 }
0064
0065 #define BYTE0(h)    (((h) >> 8) & 0xFF)
0066 #define BYTE1(h)    ((h) & 0xFF)
0067 #endif
0068
0069 static map_word ixp4xx_read16(struct map_info *map, unsigned long ofs)
0070 {
0071     map_word val;
0072
0073     val.x[0] = flash_read16(map->virt + ofs);
0074     return val;
0075 }
0076
0077 /*
0078  * The IXP4xx expansion bus only allows 16-bit wide acceses
0079  * when attached to a 16-bit wide device (such as the 28F128J3A),
0080  * so we can't just memcpy_fromio().
0081  */
0082 static void ixp4xx_copy_from(struct map_info *map, void *to,
0083                  unsigned long from, ssize_t len)
0084 {
0085     u8 *dest = (u8 *) to;
0086     void __iomem *src = map->virt + from;
0087
0088     if (len <= 0)
0089         return;
0090
0091     if (from & 1) {
0092         *dest++ = BYTE1(flash_read16(src-1));
0093         src++;
0094         --len;
0095     }
0096
0097     while (len >= 2) {
0098         u16 data = flash_read16(src);
0099         *dest++ = BYTE0(data);
0100         *dest++ = BYTE1(data);
0101         src += 2;
0102         len -= 2;
0103     }
0104
0105     if (len > 0)
0106         *dest++ = BYTE0(flash_read16(src));
0107 }
0108
0109 static void ixp4xx_write16(struct map_info *map, map_word d, unsigned long adr)
0110 {
0111     flash_write16(d.x[0], map->virt + adr);
0112 }
0113
0114 int of_flash_probe_ixp4xx(struct platform_device *pdev,
0115               struct device_node *np,
0116               struct map_info *map)
0117 {
0118     struct device *dev = &pdev->dev;
0119
0120     /* Multiplatform guard */
0121     if (!of_device_is_compatible(np, "intel,ixp4xx-flash"))
0122         return 0;
0123
0124     map->read = ixp4xx_read16;
0125     map->write = ixp4xx_write16;
0126     map->copy_from = ixp4xx_copy_from;
0127     map->copy_to = NULL;
0128
0129     dev_info(dev, "initialized Intel IXP4xx-specific physmap control\n");
0130
0131     return 0;
0132 }