mtd/maps/nettel.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /****************************************************************************/
0003
0004 /*
0005  *      nettel.c -- mappings for NETtel/SecureEdge/SnapGear (x86) boards.
0006  *
0007  *      (C) Copyright 2000-2001, Greg Ungerer (gerg@snapgear.com)
0008  *      (C) Copyright 2001-2002, SnapGear (www.snapgear.com)
0009  */
0010
0011 /****************************************************************************/
0012
0013 #include <linux/module.h>
0014 #include <linux/init.h>
0015 #include <linux/types.h>
0016 #include <linux/kernel.h>
0017 #include <linux/mtd/mtd.h>
0018 #include <linux/mtd/map.h>
0019 #include <linux/mtd/partitions.h>
0020 #include <linux/mtd/cfi.h>
0021 #include <linux/reboot.h>
0022 #include <linux/err.h>
0023 #include <linux/kdev_t.h>
0024 #include <linux/root_dev.h>
0025 #include <asm/io.h>
0026
0027 /****************************************************************************/
0028
0029 #define INTEL_BUSWIDTH      1
0030 #define AMD_WINDOW_MAXSIZE  0x00200000
0031 #define AMD_BUSWIDTH        1
0032
0033 /*
0034  *  PAR masks and shifts, assuming 64K pages.
0035  */
0036 #define SC520_PAR_ADDR_MASK 0x00003fff
0037 #define SC520_PAR_ADDR_SHIFT    16
0038 #define SC520_PAR_TO_ADDR(par) \
0039     (((par)&SC520_PAR_ADDR_MASK) << SC520_PAR_ADDR_SHIFT)
0040
0041 #define SC520_PAR_SIZE_MASK 0x01ffc000
0042 #define SC520_PAR_SIZE_SHIFT    2
0043 #define SC520_PAR_TO_SIZE(par) \
0044     ((((par)&SC520_PAR_SIZE_MASK) << SC520_PAR_SIZE_SHIFT) + (64*1024))
0045
0046 #define SC520_PAR(cs, addr, size) \
0047     ((cs) | \
0048     ((((size)-(64*1024)) >> SC520_PAR_SIZE_SHIFT) & SC520_PAR_SIZE_MASK) | \
0049     (((addr) >> SC520_PAR_ADDR_SHIFT) & SC520_PAR_ADDR_MASK))
0050
0051 #define SC520_PAR_BOOTCS    0x8a000000
0052 #define SC520_PAR_ROMCS1    0xaa000000
0053 #define SC520_PAR_ROMCS2    0xca000000  /* Cache disabled, 64K page */
0054
0055 static void *nettel_mmcrp = NULL;
0056
0057 #ifdef CONFIG_MTD_CFI_INTELEXT
0058 static struct mtd_info *intel_mtd;
0059 #endif
0060 static struct mtd_info *amd_mtd;
0061
0062 /****************************************************************************/
0063
0064 /****************************************************************************/
0065
0066 #ifdef CONFIG_MTD_CFI_INTELEXT
0067 static struct map_info nettel_intel_map = {
0068     .name = "SnapGear Intel",
0069     .size = 0,
0070     .bankwidth = INTEL_BUSWIDTH,
0071 };
0072
0073 static struct mtd_partition nettel_intel_partitions[] = {
0074     {
0075         .name = "SnapGear kernel",
0076         .offset = 0,
0077         .size = 0x000e0000
0078     },
0079     {
0080         .name = "SnapGear filesystem",
0081         .offset = 0x00100000,
0082     },
0083     {
0084         .name = "SnapGear config",
0085         .offset = 0x000e0000,
0086         .size = 0x00020000
0087     },
0088     {
0089         .name = "SnapGear Intel",
0090         .offset = 0
0091     },
0092     {
0093         .name = "SnapGear BIOS Config",
0094         .offset = 0x007e0000,
0095         .size = 0x00020000
0096     },
0097     {
0098         .name = "SnapGear BIOS",
0099         .offset = 0x007e0000,
0100         .size = 0x00020000
0101     },
0102 };
0103 #endif
0104
0105 static struct map_info nettel_amd_map = {
0106     .name = "SnapGear AMD",
0107     .size = AMD_WINDOW_MAXSIZE,
0108     .bankwidth = AMD_BUSWIDTH,
0109 };
0110
0111 static const struct mtd_partition nettel_amd_partitions[] = {
0112     {
0113         .name = "SnapGear BIOS config",
0114         .offset = 0x000e0000,
0115         .size = 0x00010000
0116     },
0117     {
0118         .name = "SnapGear BIOS",
0119         .offset = 0x000f0000,
0120         .size = 0x00010000
0121     },
0122     {
0123         .name = "SnapGear AMD",
0124         .offset = 0
0125     },
0126     {
0127         .name = "SnapGear high BIOS",
0128         .offset = 0x001f0000,
0129         .size = 0x00010000
0130     }
0131 };
0132
0133 #define NUM_AMD_PARTITIONS ARRAY_SIZE(nettel_amd_partitions)
0134
0135 /****************************************************************************/
0136
0137 #ifdef CONFIG_MTD_CFI_INTELEXT
0138
0139 /*
0140  *  Set the Intel flash back to read mode since some old boot
0141  *  loaders don't.
0142  */
0143 static int nettel_reboot_notifier(struct notifier_block *nb, unsigned long val, void *v)
0144 {
0145     struct cfi_private *cfi = nettel_intel_map.fldrv_priv;
0146     unsigned long b;
0147
0148     /* Make sure all FLASH chips are put back into read mode */
0149     for (b = 0; (b < nettel_intel_partitions[3].size); b += 0x100000) {
0150         cfi_send_gen_cmd(0xff, 0x55, b, &nettel_intel_map, cfi,
0151             cfi->device_type, NULL);
0152     }
0153     return(NOTIFY_OK);
0154 }
0155
0156 static struct notifier_block nettel_notifier_block = {
0157     nettel_reboot_notifier, NULL, 0
0158 };
0159
0160 #endif
0161
0162 /****************************************************************************/
0163
0164 static int __init nettel_init(void)
0165 {
0166     volatile unsigned long *amdpar;
0167     unsigned long amdaddr, maxsize;
0168     int num_amd_partitions=0;
0169 #ifdef CONFIG_MTD_CFI_INTELEXT
0170     volatile unsigned long *intel0par, *intel1par;
0171     unsigned long orig_bootcspar, orig_romcs1par;
0172     unsigned long intel0addr, intel0size;
0173     unsigned long intel1addr, intel1size;
0174     int intelboot, intel0cs, intel1cs;
0175     int num_intel_partitions;
0176 #endif
0177     int rc = 0;
0178
0179     nettel_mmcrp = (void *) ioremap(0xfffef000, 4096);
0180     if (nettel_mmcrp == NULL) {
0181         printk("SNAPGEAR: failed to disable MMCR cache??\n");
0182         return(-EIO);
0183     }
0184
0185     /* Set CPU clock to be 33.000MHz */
0186     *((unsigned char *) (nettel_mmcrp + 0xc64)) = 0x01;
0187
0188     amdpar = (volatile unsigned long *) (nettel_mmcrp + 0xc4);
0189
0190 #ifdef CONFIG_MTD_CFI_INTELEXT
0191     intelboot = 0;
0192     intel0cs = SC520_PAR_ROMCS1;
0193     intel0par = (volatile unsigned long *) (nettel_mmcrp + 0xc0);
0194     intel1cs = SC520_PAR_ROMCS2;
0195     intel1par = (volatile unsigned long *) (nettel_mmcrp + 0xbc);
0196
0197     /*
0198      *  Save the CS settings then ensure ROMCS1 and ROMCS2 are off,
0199      *  otherwise they might clash with where we try to map BOOTCS.
0200      */
0201     orig_bootcspar = *amdpar;
0202     orig_romcs1par = *intel0par;
0203     *intel0par = 0;
0204     *intel1par = 0;
0205 #endif
0206
0207     /*
0208      *  The first thing to do is determine if we have a separate
0209      *  boot FLASH device. Typically this is a small (1 to 2MB)
0210      *  AMD FLASH part. It seems that device size is about the
0211      *  only way to tell if this is the case...
0212      */
0213     amdaddr = 0x20000000;
0214     maxsize = AMD_WINDOW_MAXSIZE;
0215
0216     *amdpar = SC520_PAR(SC520_PAR_BOOTCS, amdaddr, maxsize);
0217     __asm__ ("wbinvd");
0218
0219     nettel_amd_map.phys = amdaddr;
0220     nettel_amd_map.virt = ioremap(amdaddr, maxsize);
0221     if (!nettel_amd_map.virt) {
0222         printk("SNAPGEAR: failed to ioremap() BOOTCS\n");
0223         iounmap(nettel_mmcrp);
0224         return(-EIO);
0225     }
0226     simple_map_init(&nettel_amd_map);
0227
0228     if ((amd_mtd = do_map_probe("jedec_probe", &nettel_amd_map))) {
0229         printk(KERN_NOTICE "SNAPGEAR: AMD flash device size = %dK\n",
0230             (int)(amd_mtd->size>>10));
0231
0232         amd_mtd->owner = THIS_MODULE;
0233
0234         /* The high BIOS partition is only present for 2MB units */
0235         num_amd_partitions = NUM_AMD_PARTITIONS;
0236         if (amd_mtd->size < AMD_WINDOW_MAXSIZE)
0237             num_amd_partitions--;
0238         /* Don't add the partition until after the primary INTEL's */
0239
0240 #ifdef CONFIG_MTD_CFI_INTELEXT
0241         /*
0242          *  Map the Intel flash into memory after the AMD
0243          *  It has to start on a multiple of maxsize.
0244          */
0245         maxsize = SC520_PAR_TO_SIZE(orig_romcs1par);
0246         if (maxsize < (32 * 1024 * 1024))
0247             maxsize = (32 * 1024 * 1024);
0248         intel0addr = amdaddr + maxsize;
0249 #endif
0250     } else {
0251 #ifdef CONFIG_MTD_CFI_INTELEXT
0252         /* INTEL boot FLASH */
0253         intelboot++;
0254
0255         if (!orig_romcs1par) {
0256             intel0cs = SC520_PAR_BOOTCS;
0257             intel0par = (volatile unsigned long *)
0258                 (nettel_mmcrp + 0xc4);
0259             intel1cs = SC520_PAR_ROMCS1;
0260             intel1par = (volatile unsigned long *)
0261                 (nettel_mmcrp + 0xc0);
0262
0263             intel0addr = SC520_PAR_TO_ADDR(orig_bootcspar);
0264             maxsize = SC520_PAR_TO_SIZE(orig_bootcspar);
0265         } else {
0266             /* Kernel base is on ROMCS1, not BOOTCS */
0267             intel0cs = SC520_PAR_ROMCS1;
0268             intel0par = (volatile unsigned long *)
0269                 (nettel_mmcrp + 0xc0);
0270             intel1cs = SC520_PAR_BOOTCS;
0271             intel1par = (volatile unsigned long *)
0272                 (nettel_mmcrp + 0xc4);
0273
0274             intel0addr = SC520_PAR_TO_ADDR(orig_romcs1par);
0275             maxsize = SC520_PAR_TO_SIZE(orig_romcs1par);
0276         }
0277
0278         /* Destroy useless AMD MTD mapping */
0279         amd_mtd = NULL;
0280         iounmap(nettel_amd_map.virt);
0281         nettel_amd_map.virt = NULL;
0282 #else
0283         /* Only AMD flash supported */
0284         rc = -ENXIO;
0285         goto out_unmap2;
0286 #endif
0287     }
0288
0289 #ifdef CONFIG_MTD_CFI_INTELEXT
0290     /*
0291      *  We have determined the INTEL FLASH configuration, so lets
0292      *  go ahead and probe for them now.
0293      */
0294
0295     /* Set PAR to the maximum size */
0296     if (maxsize < (32 * 1024 * 1024))
0297         maxsize = (32 * 1024 * 1024);
0298     *intel0par = SC520_PAR(intel0cs, intel0addr, maxsize);
0299
0300     /* Turn other PAR off so the first probe doesn't find it */
0301     *intel1par = 0;
0302
0303     /* Probe for the size of the first Intel flash */
0304     nettel_intel_map.size = maxsize;
0305     nettel_intel_map.phys = intel0addr;
0306     nettel_intel_map.virt = ioremap(intel0addr, maxsize);
0307     if (!nettel_intel_map.virt) {
0308         printk("SNAPGEAR: failed to ioremap() ROMCS1\n");
0309         rc = -EIO;
0310         goto out_unmap2;
0311     }
0312     simple_map_init(&nettel_intel_map);
0313
0314     intel_mtd = do_map_probe("cfi_probe", &nettel_intel_map);
0315     if (!intel_mtd) {
0316         rc = -ENXIO;
0317         goto out_unmap1;
0318     }
0319
0320     /* Set PAR to the detected size */
0321     intel0size = intel_mtd->size;
0322     *intel0par = SC520_PAR(intel0cs, intel0addr, intel0size);
0323
0324     /*
0325      *  Map second Intel FLASH right after first. Set its size to the
0326      *  same maxsize used for the first Intel FLASH.
0327      */
0328     intel1addr = intel0addr + intel0size;
0329     *intel1par = SC520_PAR(intel1cs, intel1addr, maxsize);
0330     __asm__ ("wbinvd");
0331
0332     maxsize += intel0size;
0333
0334     /* Delete the old map and probe again to do both chips */
0335     map_destroy(intel_mtd);
0336     intel_mtd = NULL;
0337     iounmap(nettel_intel_map.virt);
0338
0339     nettel_intel_map.size = maxsize;
0340     nettel_intel_map.virt = ioremap(intel0addr, maxsize);
0341     if (!nettel_intel_map.virt) {
0342         printk("SNAPGEAR: failed to ioremap() ROMCS1/2\n");
0343         rc = -EIO;
0344         goto out_unmap2;
0345     }
0346
0347     intel_mtd = do_map_probe("cfi_probe", &nettel_intel_map);
0348     if (! intel_mtd) {
0349         rc = -ENXIO;
0350         goto out_unmap1;
0351     }
0352
0353     intel1size = intel_mtd->size - intel0size;
0354     if (intel1size > 0) {
0355         *intel1par = SC520_PAR(intel1cs, intel1addr, intel1size);
0356         __asm__ ("wbinvd");
0357     } else {
0358         *intel1par = 0;
0359     }
0360
0361     printk(KERN_NOTICE "SNAPGEAR: Intel flash device size = %lldKiB\n",
0362            (unsigned long long)(intel_mtd->size >> 10));
0363
0364     intel_mtd->owner = THIS_MODULE;
0365
0366     num_intel_partitions = ARRAY_SIZE(nettel_intel_partitions);
0367
0368     if (intelboot) {
0369         /*
0370          *  Adjust offset and size of last boot partition.
0371          *  Must allow for BIOS region at end of FLASH.
0372          */
0373         nettel_intel_partitions[1].size = (intel0size + intel1size) -
0374             (1024*1024 + intel_mtd->erasesize);
0375         nettel_intel_partitions[3].size = intel0size + intel1size;
0376         nettel_intel_partitions[4].offset =
0377             (intel0size + intel1size) - intel_mtd->erasesize;
0378         nettel_intel_partitions[4].size = intel_mtd->erasesize;
0379         nettel_intel_partitions[5].offset =
0380             nettel_intel_partitions[4].offset;
0381         nettel_intel_partitions[5].size =
0382             nettel_intel_partitions[4].size;
0383     } else {
0384         /* No BIOS regions when AMD boot */
0385         num_intel_partitions -= 2;
0386     }
0387     rc = mtd_device_register(intel_mtd, nettel_intel_partitions,
0388                  num_intel_partitions);
0389     if (rc)
0390         goto out_map_destroy;
0391 #endif
0392
0393     if (amd_mtd) {
0394         rc = mtd_device_register(amd_mtd, nettel_amd_partitions,
0395                      num_amd_partitions);
0396         if (rc)
0397             goto out_mtd_unreg;
0398     }
0399
0400 #ifdef CONFIG_MTD_CFI_INTELEXT
0401     register_reboot_notifier(&nettel_notifier_block);
0402 #endif
0403
0404     return rc;
0405
0406 out_mtd_unreg:
0407 #ifdef CONFIG_MTD_CFI_INTELEXT
0408     mtd_device_unregister(intel_mtd);
0409 out_map_destroy:
0410     map_destroy(intel_mtd);
0411 out_unmap1:
0412     iounmap(nettel_intel_map.virt);
0413 #endif
0414
0415 out_unmap2:
0416     iounmap(nettel_mmcrp);
0417     iounmap(nettel_amd_map.virt);
0418
0419     return rc;
0420 }
0421
0422 /****************************************************************************/
0423
0424 static void __exit nettel_cleanup(void)
0425 {
0426 #ifdef CONFIG_MTD_CFI_INTELEXT
0427     unregister_reboot_notifier(&nettel_notifier_block);
0428 #endif
0429     if (amd_mtd) {
0430         mtd_device_unregister(amd_mtd);
0431         map_destroy(amd_mtd);
0432     }
0433     if (nettel_mmcrp) {
0434         iounmap(nettel_mmcrp);
0435         nettel_mmcrp = NULL;
0436     }
0437     if (nettel_amd_map.virt) {
0438         iounmap(nettel_amd_map.virt);
0439         nettel_amd_map.virt = NULL;
0440     }
0441 #ifdef CONFIG_MTD_CFI_INTELEXT
0442     if (intel_mtd) {
0443         mtd_device_unregister(intel_mtd);
0444         map_destroy(intel_mtd);
0445     }
0446     if (nettel_intel_map.virt) {
0447         iounmap(nettel_intel_map.virt);
0448         nettel_intel_map.virt = NULL;
0449     }
0450 #endif
0451 }
0452
0453 /****************************************************************************/
0454
0455 module_init(nettel_init);
0456 module_exit(nettel_cleanup);
0457
0458 MODULE_LICENSE("GPL");
0459 MODULE_AUTHOR("Greg Ungerer <gerg@snapgear.com>");
0460 MODULE_DESCRIPTION("SnapGear/SecureEdge FLASH support");
0461
0462 /****************************************************************************/