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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  WM8505/WM8650 SD/MMC Host Controller
0004  *
0005  *  Copyright (C) 2010 Tony Prisk
0006  *  Copyright (C) 2008 WonderMedia Technologies, Inc.
0007  */
0008 
0009 #include <linux/init.h>
0010 #include <linux/module.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/ioport.h>
0013 #include <linux/errno.h>
0014 #include <linux/dma-mapping.h>
0015 #include <linux/delay.h>
0016 #include <linux/io.h>
0017 #include <linux/irq.h>
0018 #include <linux/clk.h>
0019 #include <linux/interrupt.h>
0020 
0021 #include <linux/of.h>
0022 #include <linux/of_address.h>
0023 #include <linux/of_irq.h>
0024 #include <linux/of_device.h>
0025 
0026 #include <linux/mmc/host.h>
0027 #include <linux/mmc/mmc.h>
0028 #include <linux/mmc/sd.h>
0029 
0030 #include <asm/byteorder.h>
0031 
0032 
0033 #define DRIVER_NAME "wmt-sdhc"
0034 
0035 
0036 /* MMC/SD controller registers */
0037 #define SDMMC_CTLR          0x00
0038 #define SDMMC_CMD           0x01
0039 #define SDMMC_RSPTYPE           0x02
0040 #define SDMMC_ARG           0x04
0041 #define SDMMC_BUSMODE           0x08
0042 #define SDMMC_BLKLEN            0x0C
0043 #define SDMMC_BLKCNT            0x0E
0044 #define SDMMC_RSP           0x10
0045 #define SDMMC_CBCR          0x20
0046 #define SDMMC_INTMASK0          0x24
0047 #define SDMMC_INTMASK1          0x25
0048 #define SDMMC_STS0          0x28
0049 #define SDMMC_STS1          0x29
0050 #define SDMMC_STS2          0x2A
0051 #define SDMMC_STS3          0x2B
0052 #define SDMMC_RSPTIMEOUT        0x2C
0053 #define SDMMC_CLK           0x30    /* VT8500 only */
0054 #define SDMMC_EXTCTRL           0x34
0055 #define SDMMC_SBLKLEN           0x38
0056 #define SDMMC_DMATIMEOUT        0x3C
0057 
0058 
0059 /* SDMMC_CTLR bit fields */
0060 #define CTLR_CMD_START          0x01
0061 #define CTLR_CMD_WRITE          0x04
0062 #define CTLR_FIFO_RESET         0x08
0063 
0064 /* SDMMC_BUSMODE bit fields */
0065 #define BM_SPI_MODE         0x01
0066 #define BM_FOURBIT_MODE         0x02
0067 #define BM_EIGHTBIT_MODE        0x04
0068 #define BM_SD_OFF           0x10
0069 #define BM_SPI_CS           0x20
0070 #define BM_SD_POWER         0x40
0071 #define BM_SOFT_RESET           0x80
0072 
0073 /* SDMMC_BLKLEN bit fields */
0074 #define BLKL_CRCERR_ABORT       0x0800
0075 #define BLKL_CD_POL_HIGH        0x1000
0076 #define BLKL_GPI_CD         0x2000
0077 #define BLKL_DATA3_CD           0x4000
0078 #define BLKL_INT_ENABLE         0x8000
0079 
0080 /* SDMMC_INTMASK0 bit fields */
0081 #define INT0_MBLK_TRAN_DONE_INT_EN  0x10
0082 #define INT0_BLK_TRAN_DONE_INT_EN   0x20
0083 #define INT0_CD_INT_EN          0x40
0084 #define INT0_DI_INT_EN          0x80
0085 
0086 /* SDMMC_INTMASK1 bit fields */
0087 #define INT1_CMD_RES_TRAN_DONE_INT_EN   0x02
0088 #define INT1_CMD_RES_TOUT_INT_EN    0x04
0089 #define INT1_MBLK_AUTO_STOP_INT_EN  0x08
0090 #define INT1_DATA_TOUT_INT_EN       0x10
0091 #define INT1_RESCRC_ERR_INT_EN      0x20
0092 #define INT1_RCRC_ERR_INT_EN        0x40
0093 #define INT1_WCRC_ERR_INT_EN        0x80
0094 
0095 /* SDMMC_STS0 bit fields */
0096 #define STS0_WRITE_PROTECT      0x02
0097 #define STS0_CD_DATA3           0x04
0098 #define STS0_CD_GPI         0x08
0099 #define STS0_MBLK_DONE          0x10
0100 #define STS0_BLK_DONE           0x20
0101 #define STS0_CARD_DETECT        0x40
0102 #define STS0_DEVICE_INS         0x80
0103 
0104 /* SDMMC_STS1 bit fields */
0105 #define STS1_SDIO_INT           0x01
0106 #define STS1_CMDRSP_DONE        0x02
0107 #define STS1_RSP_TIMEOUT        0x04
0108 #define STS1_AUTOSTOP_DONE      0x08
0109 #define STS1_DATA_TIMEOUT       0x10
0110 #define STS1_RSP_CRC_ERR        0x20
0111 #define STS1_RCRC_ERR           0x40
0112 #define STS1_WCRC_ERR           0x80
0113 
0114 /* SDMMC_STS2 bit fields */
0115 #define STS2_CMD_RES_BUSY       0x10
0116 #define STS2_DATARSP_BUSY       0x20
0117 #define STS2_DIS_FORCECLK       0x80
0118 
0119 /* SDMMC_EXTCTRL bit fields */
0120 #define EXT_EIGHTBIT            0x04
0121 
0122 /* MMC/SD DMA Controller Registers */
0123 #define SDDMA_GCR           0x100
0124 #define SDDMA_IER           0x104
0125 #define SDDMA_ISR           0x108
0126 #define SDDMA_DESPR         0x10C
0127 #define SDDMA_RBR           0x110
0128 #define SDDMA_DAR           0x114
0129 #define SDDMA_BAR           0x118
0130 #define SDDMA_CPR           0x11C
0131 #define SDDMA_CCR           0x120
0132 
0133 
0134 /* SDDMA_GCR bit fields */
0135 #define DMA_GCR_DMA_EN          0x00000001
0136 #define DMA_GCR_SOFT_RESET      0x00000100
0137 
0138 /* SDDMA_IER bit fields */
0139 #define DMA_IER_INT_EN          0x00000001
0140 
0141 /* SDDMA_ISR bit fields */
0142 #define DMA_ISR_INT_STS         0x00000001
0143 
0144 /* SDDMA_RBR bit fields */
0145 #define DMA_RBR_FORMAT          0x40000000
0146 #define DMA_RBR_END         0x80000000
0147 
0148 /* SDDMA_CCR bit fields */
0149 #define DMA_CCR_RUN         0x00000080
0150 #define DMA_CCR_IF_TO_PERIPHERAL    0x00000000
0151 #define DMA_CCR_PERIPHERAL_TO_IF    0x00400000
0152 
0153 /* SDDMA_CCR event status */
0154 #define DMA_CCR_EVT_NO_STATUS       0x00000000
0155 #define DMA_CCR_EVT_UNDERRUN        0x00000001
0156 #define DMA_CCR_EVT_OVERRUN     0x00000002
0157 #define DMA_CCR_EVT_DESP_READ       0x00000003
0158 #define DMA_CCR_EVT_DATA_RW     0x00000004
0159 #define DMA_CCR_EVT_EARLY_END       0x00000005
0160 #define DMA_CCR_EVT_SUCCESS     0x0000000F
0161 
0162 #define PDMA_READ           0x00
0163 #define PDMA_WRITE          0x01
0164 
0165 #define WMT_SD_POWER_OFF        0
0166 #define WMT_SD_POWER_ON         1
0167 
0168 struct wmt_dma_descriptor {
0169     u32 flags;
0170     u32 data_buffer_addr;
0171     u32 branch_addr;
0172     u32 reserved1;
0173 };
0174 
0175 struct wmt_mci_caps {
0176     unsigned int    f_min;
0177     unsigned int    f_max;
0178     u32     ocr_avail;
0179     u32     caps;
0180     u32     max_seg_size;
0181     u32     max_segs;
0182     u32     max_blk_size;
0183 };
0184 
0185 struct wmt_mci_priv {
0186     struct mmc_host *mmc;
0187     void __iomem *sdmmc_base;
0188 
0189     int irq_regular;
0190     int irq_dma;
0191 
0192     void *dma_desc_buffer;
0193     dma_addr_t dma_desc_device_addr;
0194 
0195     struct completion cmdcomp;
0196     struct completion datacomp;
0197 
0198     struct completion *comp_cmd;
0199     struct completion *comp_dma;
0200 
0201     struct mmc_request *req;
0202     struct mmc_command *cmd;
0203 
0204     struct clk *clk_sdmmc;
0205     struct device *dev;
0206 
0207     u8 power_inverted;
0208     u8 cd_inverted;
0209 };
0210 
0211 static void wmt_set_sd_power(struct wmt_mci_priv *priv, int enable)
0212 {
0213     u32 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
0214 
0215     if (enable ^ priv->power_inverted)
0216         reg_tmp &= ~BM_SD_OFF;
0217     else
0218         reg_tmp |= BM_SD_OFF;
0219 
0220     writeb(reg_tmp, priv->sdmmc_base + SDMMC_BUSMODE);
0221 }
0222 
0223 static void wmt_mci_read_response(struct mmc_host *mmc)
0224 {
0225     struct wmt_mci_priv *priv;
0226     int idx1, idx2;
0227     u8 tmp_resp;
0228     u32 response;
0229 
0230     priv = mmc_priv(mmc);
0231 
0232     for (idx1 = 0; idx1 < 4; idx1++) {
0233         response = 0;
0234         for (idx2 = 0; idx2 < 4; idx2++) {
0235             if ((idx1 == 3) && (idx2 == 3))
0236                 tmp_resp = readb(priv->sdmmc_base + SDMMC_RSP);
0237             else
0238                 tmp_resp = readb(priv->sdmmc_base + SDMMC_RSP +
0239                          (idx1*4) + idx2 + 1);
0240             response |= (tmp_resp << (idx2 * 8));
0241         }
0242         priv->cmd->resp[idx1] = cpu_to_be32(response);
0243     }
0244 }
0245 
0246 static void wmt_mci_start_command(struct wmt_mci_priv *priv)
0247 {
0248     u32 reg_tmp;
0249 
0250     reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
0251     writeb(reg_tmp | CTLR_CMD_START, priv->sdmmc_base + SDMMC_CTLR);
0252 }
0253 
0254 static int wmt_mci_send_command(struct mmc_host *mmc, u8 command, u8 cmdtype,
0255                 u32 arg, u8 rsptype)
0256 {
0257     struct wmt_mci_priv *priv;
0258     u32 reg_tmp;
0259 
0260     priv = mmc_priv(mmc);
0261 
0262     /* write command, arg, resptype registers */
0263     writeb(command, priv->sdmmc_base + SDMMC_CMD);
0264     writel(arg, priv->sdmmc_base + SDMMC_ARG);
0265     writeb(rsptype, priv->sdmmc_base + SDMMC_RSPTYPE);
0266 
0267     /* reset response FIFO */
0268     reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
0269     writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR);
0270 
0271     /* ensure clock enabled - VT3465 */
0272     wmt_set_sd_power(priv, WMT_SD_POWER_ON);
0273 
0274     /* clear status bits */
0275     writeb(0xFF, priv->sdmmc_base + SDMMC_STS0);
0276     writeb(0xFF, priv->sdmmc_base + SDMMC_STS1);
0277     writeb(0xFF, priv->sdmmc_base + SDMMC_STS2);
0278     writeb(0xFF, priv->sdmmc_base + SDMMC_STS3);
0279 
0280     /* set command type */
0281     reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
0282     writeb((reg_tmp & 0x0F) | (cmdtype << 4),
0283            priv->sdmmc_base + SDMMC_CTLR);
0284 
0285     return 0;
0286 }
0287 
0288 static void wmt_mci_disable_dma(struct wmt_mci_priv *priv)
0289 {
0290     writel(DMA_ISR_INT_STS, priv->sdmmc_base + SDDMA_ISR);
0291     writel(0, priv->sdmmc_base + SDDMA_IER);
0292 }
0293 
0294 static void wmt_complete_data_request(struct wmt_mci_priv *priv)
0295 {
0296     struct mmc_request *req;
0297     req = priv->req;
0298 
0299     req->data->bytes_xfered = req->data->blksz * req->data->blocks;
0300 
0301     /* unmap the DMA pages used for write data */
0302     if (req->data->flags & MMC_DATA_WRITE)
0303         dma_unmap_sg(mmc_dev(priv->mmc), req->data->sg,
0304                  req->data->sg_len, DMA_TO_DEVICE);
0305     else
0306         dma_unmap_sg(mmc_dev(priv->mmc), req->data->sg,
0307                  req->data->sg_len, DMA_FROM_DEVICE);
0308 
0309     /* Check if the DMA ISR returned a data error */
0310     if ((req->cmd->error) || (req->data->error))
0311         mmc_request_done(priv->mmc, req);
0312     else {
0313         wmt_mci_read_response(priv->mmc);
0314         if (!req->data->stop) {
0315             /* single-block read/write requests end here */
0316             mmc_request_done(priv->mmc, req);
0317         } else {
0318             /*
0319              * we change the priv->cmd variable so the response is
0320              * stored in the stop struct rather than the original
0321              * calling command struct
0322              */
0323             priv->comp_cmd = &priv->cmdcomp;
0324             init_completion(priv->comp_cmd);
0325             priv->cmd = req->data->stop;
0326             wmt_mci_send_command(priv->mmc, req->data->stop->opcode,
0327                          7, req->data->stop->arg, 9);
0328             wmt_mci_start_command(priv);
0329         }
0330     }
0331 }
0332 
0333 static irqreturn_t wmt_mci_dma_isr(int irq_num, void *data)
0334 {
0335     struct wmt_mci_priv *priv;
0336 
0337     int status;
0338 
0339     priv = (struct wmt_mci_priv *)data;
0340 
0341     status = readl(priv->sdmmc_base + SDDMA_CCR) & 0x0F;
0342 
0343     if (status != DMA_CCR_EVT_SUCCESS) {
0344         dev_err(priv->dev, "DMA Error: Status = %d\n", status);
0345         priv->req->data->error = -ETIMEDOUT;
0346         complete(priv->comp_dma);
0347         return IRQ_HANDLED;
0348     }
0349 
0350     priv->req->data->error = 0;
0351 
0352     wmt_mci_disable_dma(priv);
0353 
0354     complete(priv->comp_dma);
0355 
0356     if (priv->comp_cmd) {
0357         if (completion_done(priv->comp_cmd)) {
0358             /*
0359              * if the command (regular) interrupt has already
0360              * completed, finish off the request otherwise we wait
0361              * for the command interrupt and finish from there.
0362              */
0363             wmt_complete_data_request(priv);
0364         }
0365     }
0366 
0367     return IRQ_HANDLED;
0368 }
0369 
0370 static irqreturn_t wmt_mci_regular_isr(int irq_num, void *data)
0371 {
0372     struct wmt_mci_priv *priv;
0373     u32 status0;
0374     u32 status1;
0375     u32 status2;
0376     u32 reg_tmp;
0377     int cmd_done;
0378 
0379     priv = (struct wmt_mci_priv *)data;
0380     cmd_done = 0;
0381     status0 = readb(priv->sdmmc_base + SDMMC_STS0);
0382     status1 = readb(priv->sdmmc_base + SDMMC_STS1);
0383     status2 = readb(priv->sdmmc_base + SDMMC_STS2);
0384 
0385     /* Check for card insertion */
0386     reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0);
0387     if ((reg_tmp & INT0_DI_INT_EN) && (status0 & STS0_DEVICE_INS)) {
0388         mmc_detect_change(priv->mmc, 0);
0389         if (priv->cmd)
0390             priv->cmd->error = -ETIMEDOUT;
0391         if (priv->comp_cmd)
0392             complete(priv->comp_cmd);
0393         if (priv->comp_dma) {
0394             wmt_mci_disable_dma(priv);
0395             complete(priv->comp_dma);
0396         }
0397         writeb(STS0_DEVICE_INS, priv->sdmmc_base + SDMMC_STS0);
0398         return IRQ_HANDLED;
0399     }
0400 
0401     if ((!priv->req->data) ||
0402         ((priv->req->data->stop) && (priv->cmd == priv->req->data->stop))) {
0403         /* handle non-data & stop_transmission requests */
0404         if (status1 & STS1_CMDRSP_DONE) {
0405             priv->cmd->error = 0;
0406             cmd_done = 1;
0407         } else if ((status1 & STS1_RSP_TIMEOUT) ||
0408                (status1 & STS1_DATA_TIMEOUT)) {
0409             priv->cmd->error = -ETIMEDOUT;
0410             cmd_done = 1;
0411         }
0412 
0413         if (cmd_done) {
0414             priv->comp_cmd = NULL;
0415 
0416             if (!priv->cmd->error)
0417                 wmt_mci_read_response(priv->mmc);
0418 
0419             priv->cmd = NULL;
0420 
0421             mmc_request_done(priv->mmc, priv->req);
0422         }
0423     } else {
0424         /* handle data requests */
0425         if (status1 & STS1_CMDRSP_DONE) {
0426             if (priv->cmd)
0427                 priv->cmd->error = 0;
0428             if (priv->comp_cmd)
0429                 complete(priv->comp_cmd);
0430         }
0431 
0432         if ((status1 & STS1_RSP_TIMEOUT) ||
0433             (status1 & STS1_DATA_TIMEOUT)) {
0434             if (priv->cmd)
0435                 priv->cmd->error = -ETIMEDOUT;
0436             if (priv->comp_cmd)
0437                 complete(priv->comp_cmd);
0438             if (priv->comp_dma) {
0439                 wmt_mci_disable_dma(priv);
0440                 complete(priv->comp_dma);
0441             }
0442         }
0443 
0444         if (priv->comp_dma) {
0445             /*
0446              * If the dma interrupt has already completed, finish
0447              * off the request; otherwise we wait for the DMA
0448              * interrupt and finish from there.
0449              */
0450             if (completion_done(priv->comp_dma))
0451                 wmt_complete_data_request(priv);
0452         }
0453     }
0454 
0455     writeb(status0, priv->sdmmc_base + SDMMC_STS0);
0456     writeb(status1, priv->sdmmc_base + SDMMC_STS1);
0457     writeb(status2, priv->sdmmc_base + SDMMC_STS2);
0458 
0459     return IRQ_HANDLED;
0460 }
0461 
0462 static void wmt_reset_hardware(struct mmc_host *mmc)
0463 {
0464     struct wmt_mci_priv *priv;
0465     u32 reg_tmp;
0466 
0467     priv = mmc_priv(mmc);
0468 
0469     /* reset controller */
0470     reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
0471     writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE);
0472 
0473     /* reset response FIFO */
0474     reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
0475     writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR);
0476 
0477     /* enable GPI pin to detect card */
0478     writew(BLKL_INT_ENABLE | BLKL_GPI_CD, priv->sdmmc_base + SDMMC_BLKLEN);
0479 
0480     /* clear interrupt status */
0481     writeb(0xFF, priv->sdmmc_base + SDMMC_STS0);
0482     writeb(0xFF, priv->sdmmc_base + SDMMC_STS1);
0483 
0484     /* setup interrupts */
0485     writeb(INT0_CD_INT_EN | INT0_DI_INT_EN, priv->sdmmc_base +
0486            SDMMC_INTMASK0);
0487     writeb(INT1_DATA_TOUT_INT_EN | INT1_CMD_RES_TRAN_DONE_INT_EN |
0488            INT1_CMD_RES_TOUT_INT_EN, priv->sdmmc_base + SDMMC_INTMASK1);
0489 
0490     /* set the DMA timeout */
0491     writew(8191, priv->sdmmc_base + SDMMC_DMATIMEOUT);
0492 
0493     /* auto clock freezing enable */
0494     reg_tmp = readb(priv->sdmmc_base + SDMMC_STS2);
0495     writeb(reg_tmp | STS2_DIS_FORCECLK, priv->sdmmc_base + SDMMC_STS2);
0496 
0497     /* set a default clock speed of 400Khz */
0498     clk_set_rate(priv->clk_sdmmc, 400000);
0499 }
0500 
0501 static int wmt_dma_init(struct mmc_host *mmc)
0502 {
0503     struct wmt_mci_priv *priv;
0504 
0505     priv = mmc_priv(mmc);
0506 
0507     writel(DMA_GCR_SOFT_RESET, priv->sdmmc_base + SDDMA_GCR);
0508     writel(DMA_GCR_DMA_EN, priv->sdmmc_base + SDDMA_GCR);
0509     if ((readl(priv->sdmmc_base + SDDMA_GCR) & DMA_GCR_DMA_EN) != 0)
0510         return 0;
0511     else
0512         return 1;
0513 }
0514 
0515 static void wmt_dma_init_descriptor(struct wmt_dma_descriptor *desc,
0516         u16 req_count, u32 buffer_addr, u32 branch_addr, int end)
0517 {
0518     desc->flags = 0x40000000 | req_count;
0519     if (end)
0520         desc->flags |= 0x80000000;
0521     desc->data_buffer_addr = buffer_addr;
0522     desc->branch_addr = branch_addr;
0523 }
0524 
0525 static void wmt_dma_config(struct mmc_host *mmc, u32 descaddr, u8 dir)
0526 {
0527     struct wmt_mci_priv *priv;
0528     u32 reg_tmp;
0529 
0530     priv = mmc_priv(mmc);
0531 
0532     /* Enable DMA Interrupts */
0533     writel(DMA_IER_INT_EN, priv->sdmmc_base + SDDMA_IER);
0534 
0535     /* Write DMA Descriptor Pointer Register */
0536     writel(descaddr, priv->sdmmc_base + SDDMA_DESPR);
0537 
0538     writel(0x00, priv->sdmmc_base + SDDMA_CCR);
0539 
0540     if (dir == PDMA_WRITE) {
0541         reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
0542         writel(reg_tmp & DMA_CCR_IF_TO_PERIPHERAL, priv->sdmmc_base +
0543                SDDMA_CCR);
0544     } else {
0545         reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
0546         writel(reg_tmp | DMA_CCR_PERIPHERAL_TO_IF, priv->sdmmc_base +
0547                SDDMA_CCR);
0548     }
0549 }
0550 
0551 static void wmt_dma_start(struct wmt_mci_priv *priv)
0552 {
0553     u32 reg_tmp;
0554 
0555     reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
0556     writel(reg_tmp | DMA_CCR_RUN, priv->sdmmc_base + SDDMA_CCR);
0557 }
0558 
0559 static void wmt_mci_request(struct mmc_host *mmc, struct mmc_request *req)
0560 {
0561     struct wmt_mci_priv *priv;
0562     struct wmt_dma_descriptor *desc;
0563     u8 command;
0564     u8 cmdtype;
0565     u32 arg;
0566     u8 rsptype;
0567     u32 reg_tmp;
0568 
0569     struct scatterlist *sg;
0570     int i;
0571     int sg_cnt;
0572     int offset;
0573     u32 dma_address;
0574     int desc_cnt;
0575 
0576     priv = mmc_priv(mmc);
0577     priv->req = req;
0578 
0579     /*
0580      * Use the cmd variable to pass a pointer to the resp[] structure
0581      * This is required on multi-block requests to pass the pointer to the
0582      * stop command
0583      */
0584     priv->cmd = req->cmd;
0585 
0586     command = req->cmd->opcode;
0587     arg = req->cmd->arg;
0588     rsptype = mmc_resp_type(req->cmd);
0589     cmdtype = 0;
0590 
0591     /* rsptype=7 only valid for SPI commands - should be =2 for SD */
0592     if (rsptype == 7)
0593         rsptype = 2;
0594     /* rsptype=21 is R1B, convert for controller */
0595     if (rsptype == 21)
0596         rsptype = 9;
0597 
0598     if (!req->data) {
0599         wmt_mci_send_command(mmc, command, cmdtype, arg, rsptype);
0600         wmt_mci_start_command(priv);
0601         /* completion is now handled in the regular_isr() */
0602     }
0603     if (req->data) {
0604         priv->comp_cmd = &priv->cmdcomp;
0605         init_completion(priv->comp_cmd);
0606 
0607         wmt_dma_init(mmc);
0608 
0609         /* set controller data length */
0610         reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
0611         writew((reg_tmp & 0xF800) | (req->data->blksz - 1),
0612                priv->sdmmc_base + SDMMC_BLKLEN);
0613 
0614         /* set controller block count */
0615         writew(req->data->blocks, priv->sdmmc_base + SDMMC_BLKCNT);
0616 
0617         desc = (struct wmt_dma_descriptor *)priv->dma_desc_buffer;
0618 
0619         if (req->data->flags & MMC_DATA_WRITE) {
0620             sg_cnt = dma_map_sg(mmc_dev(mmc), req->data->sg,
0621                         req->data->sg_len, DMA_TO_DEVICE);
0622             cmdtype = 1;
0623             if (req->data->blocks > 1)
0624                 cmdtype = 3;
0625         } else {
0626             sg_cnt = dma_map_sg(mmc_dev(mmc), req->data->sg,
0627                         req->data->sg_len, DMA_FROM_DEVICE);
0628             cmdtype = 2;
0629             if (req->data->blocks > 1)
0630                 cmdtype = 4;
0631         }
0632 
0633         dma_address = priv->dma_desc_device_addr + 16;
0634         desc_cnt = 0;
0635 
0636         for_each_sg(req->data->sg, sg, sg_cnt, i) {
0637             offset = 0;
0638             while (offset < sg_dma_len(sg)) {
0639                 wmt_dma_init_descriptor(desc, req->data->blksz,
0640                         sg_dma_address(sg)+offset,
0641                         dma_address, 0);
0642                 desc++;
0643                 desc_cnt++;
0644                 offset += req->data->blksz;
0645                 dma_address += 16;
0646                 if (desc_cnt == req->data->blocks)
0647                     break;
0648             }
0649         }
0650         desc--;
0651         desc->flags |= 0x80000000;
0652 
0653         if (req->data->flags & MMC_DATA_WRITE)
0654             wmt_dma_config(mmc, priv->dma_desc_device_addr,
0655                        PDMA_WRITE);
0656         else
0657             wmt_dma_config(mmc, priv->dma_desc_device_addr,
0658                        PDMA_READ);
0659 
0660         wmt_mci_send_command(mmc, command, cmdtype, arg, rsptype);
0661 
0662         priv->comp_dma = &priv->datacomp;
0663         init_completion(priv->comp_dma);
0664 
0665         wmt_dma_start(priv);
0666         wmt_mci_start_command(priv);
0667     }
0668 }
0669 
0670 static void wmt_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
0671 {
0672     struct wmt_mci_priv *priv;
0673     u32 busmode, extctrl;
0674 
0675     priv = mmc_priv(mmc);
0676 
0677     if (ios->power_mode == MMC_POWER_UP) {
0678         wmt_reset_hardware(mmc);
0679 
0680         wmt_set_sd_power(priv, WMT_SD_POWER_ON);
0681     }
0682     if (ios->power_mode == MMC_POWER_OFF)
0683         wmt_set_sd_power(priv, WMT_SD_POWER_OFF);
0684 
0685     if (ios->clock != 0)
0686         clk_set_rate(priv->clk_sdmmc, ios->clock);
0687 
0688     busmode = readb(priv->sdmmc_base + SDMMC_BUSMODE);
0689     extctrl = readb(priv->sdmmc_base + SDMMC_EXTCTRL);
0690 
0691     busmode &= ~(BM_EIGHTBIT_MODE | BM_FOURBIT_MODE);
0692     extctrl &= ~EXT_EIGHTBIT;
0693 
0694     switch (ios->bus_width) {
0695     case MMC_BUS_WIDTH_8:
0696         busmode |= BM_EIGHTBIT_MODE;
0697         extctrl |= EXT_EIGHTBIT;
0698         break;
0699     case MMC_BUS_WIDTH_4:
0700         busmode |= BM_FOURBIT_MODE;
0701         break;
0702     case MMC_BUS_WIDTH_1:
0703         break;
0704     }
0705 
0706     writeb(busmode, priv->sdmmc_base + SDMMC_BUSMODE);
0707     writeb(extctrl, priv->sdmmc_base + SDMMC_EXTCTRL);
0708 }
0709 
0710 static int wmt_mci_get_ro(struct mmc_host *mmc)
0711 {
0712     struct wmt_mci_priv *priv = mmc_priv(mmc);
0713 
0714     return !(readb(priv->sdmmc_base + SDMMC_STS0) & STS0_WRITE_PROTECT);
0715 }
0716 
0717 static int wmt_mci_get_cd(struct mmc_host *mmc)
0718 {
0719     struct wmt_mci_priv *priv = mmc_priv(mmc);
0720     u32 cd = (readb(priv->sdmmc_base + SDMMC_STS0) & STS0_CD_GPI) >> 3;
0721 
0722     return !(cd ^ priv->cd_inverted);
0723 }
0724 
0725 static const struct mmc_host_ops wmt_mci_ops = {
0726     .request = wmt_mci_request,
0727     .set_ios = wmt_mci_set_ios,
0728     .get_ro = wmt_mci_get_ro,
0729     .get_cd = wmt_mci_get_cd,
0730 };
0731 
0732 /* Controller capabilities */
0733 static struct wmt_mci_caps wm8505_caps = {
0734     .f_min = 390425,
0735     .f_max = 50000000,
0736     .ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34,
0737     .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED |
0738         MMC_CAP_SD_HIGHSPEED,
0739     .max_seg_size = 65024,
0740     .max_segs = 128,
0741     .max_blk_size = 2048,
0742 };
0743 
0744 static const struct of_device_id wmt_mci_dt_ids[] = {
0745     { .compatible = "wm,wm8505-sdhc", .data = &wm8505_caps },
0746     { /* Sentinel */ },
0747 };
0748 
0749 static int wmt_mci_probe(struct platform_device *pdev)
0750 {
0751     struct mmc_host *mmc;
0752     struct wmt_mci_priv *priv;
0753     struct device_node *np = pdev->dev.of_node;
0754     const struct wmt_mci_caps *wmt_caps;
0755     int ret;
0756     int regular_irq, dma_irq;
0757 
0758     wmt_caps = of_device_get_match_data(&pdev->dev);
0759     if (!wmt_caps) {
0760         dev_err(&pdev->dev, "Controller capabilities data missing\n");
0761         return -EFAULT;
0762     }
0763 
0764     if (!np) {
0765         dev_err(&pdev->dev, "Missing SDMMC description in devicetree\n");
0766         return -EFAULT;
0767     }
0768 
0769     regular_irq = irq_of_parse_and_map(np, 0);
0770     dma_irq = irq_of_parse_and_map(np, 1);
0771 
0772     if (!regular_irq || !dma_irq) {
0773         dev_err(&pdev->dev, "Getting IRQs failed!\n");
0774         ret = -ENXIO;
0775         goto fail1;
0776     }
0777 
0778     mmc = mmc_alloc_host(sizeof(struct wmt_mci_priv), &pdev->dev);
0779     if (!mmc) {
0780         dev_err(&pdev->dev, "Failed to allocate mmc_host\n");
0781         ret = -ENOMEM;
0782         goto fail1;
0783     }
0784 
0785     mmc->ops = &wmt_mci_ops;
0786     mmc->f_min = wmt_caps->f_min;
0787     mmc->f_max = wmt_caps->f_max;
0788     mmc->ocr_avail = wmt_caps->ocr_avail;
0789     mmc->caps = wmt_caps->caps;
0790 
0791     mmc->max_seg_size = wmt_caps->max_seg_size;
0792     mmc->max_segs = wmt_caps->max_segs;
0793     mmc->max_blk_size = wmt_caps->max_blk_size;
0794 
0795     mmc->max_req_size = (16*512*mmc->max_segs);
0796     mmc->max_blk_count = mmc->max_req_size / 512;
0797 
0798     priv = mmc_priv(mmc);
0799     priv->mmc = mmc;
0800     priv->dev = &pdev->dev;
0801 
0802     priv->power_inverted = 0;
0803     priv->cd_inverted = 0;
0804 
0805     if (of_get_property(np, "sdon-inverted", NULL))
0806         priv->power_inverted = 1;
0807     if (of_get_property(np, "cd-inverted", NULL))
0808         priv->cd_inverted = 1;
0809 
0810     priv->sdmmc_base = of_iomap(np, 0);
0811     if (!priv->sdmmc_base) {
0812         dev_err(&pdev->dev, "Failed to map IO space\n");
0813         ret = -ENOMEM;
0814         goto fail2;
0815     }
0816 
0817     priv->irq_regular = regular_irq;
0818     priv->irq_dma = dma_irq;
0819 
0820     ret = request_irq(regular_irq, wmt_mci_regular_isr, 0, "sdmmc", priv);
0821     if (ret) {
0822         dev_err(&pdev->dev, "Register regular IRQ fail\n");
0823         goto fail3;
0824     }
0825 
0826     ret = request_irq(dma_irq, wmt_mci_dma_isr, 0, "sdmmc", priv);
0827     if (ret) {
0828         dev_err(&pdev->dev, "Register DMA IRQ fail\n");
0829         goto fail4;
0830     }
0831 
0832     /* alloc some DMA buffers for descriptors/transfers */
0833     priv->dma_desc_buffer = dma_alloc_coherent(&pdev->dev,
0834                            mmc->max_blk_count * 16,
0835                            &priv->dma_desc_device_addr,
0836                            GFP_KERNEL);
0837     if (!priv->dma_desc_buffer) {
0838         dev_err(&pdev->dev, "DMA alloc fail\n");
0839         ret = -EPERM;
0840         goto fail5;
0841     }
0842 
0843     platform_set_drvdata(pdev, mmc);
0844 
0845     priv->clk_sdmmc = of_clk_get(np, 0);
0846     if (IS_ERR(priv->clk_sdmmc)) {
0847         dev_err(&pdev->dev, "Error getting clock\n");
0848         ret = PTR_ERR(priv->clk_sdmmc);
0849         goto fail5;
0850     }
0851 
0852     ret = clk_prepare_enable(priv->clk_sdmmc);
0853     if (ret)
0854         goto fail6;
0855 
0856     /* configure the controller to a known 'ready' state */
0857     wmt_reset_hardware(mmc);
0858 
0859     mmc_add_host(mmc);
0860 
0861     dev_info(&pdev->dev, "WMT SDHC Controller initialized\n");
0862 
0863     return 0;
0864 fail6:
0865     clk_put(priv->clk_sdmmc);
0866 fail5:
0867     free_irq(dma_irq, priv);
0868 fail4:
0869     free_irq(regular_irq, priv);
0870 fail3:
0871     iounmap(priv->sdmmc_base);
0872 fail2:
0873     mmc_free_host(mmc);
0874 fail1:
0875     return ret;
0876 }
0877 
0878 static int wmt_mci_remove(struct platform_device *pdev)
0879 {
0880     struct mmc_host *mmc;
0881     struct wmt_mci_priv *priv;
0882     struct resource *res;
0883     u32 reg_tmp;
0884 
0885     mmc = platform_get_drvdata(pdev);
0886     priv = mmc_priv(mmc);
0887 
0888     /* reset SD controller */
0889     reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
0890     writel(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE);
0891     reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
0892     writew(reg_tmp & ~(0xA000), priv->sdmmc_base + SDMMC_BLKLEN);
0893     writeb(0xFF, priv->sdmmc_base + SDMMC_STS0);
0894     writeb(0xFF, priv->sdmmc_base + SDMMC_STS1);
0895 
0896     /* release the dma buffers */
0897     dma_free_coherent(&pdev->dev, priv->mmc->max_blk_count * 16,
0898               priv->dma_desc_buffer, priv->dma_desc_device_addr);
0899 
0900     mmc_remove_host(mmc);
0901 
0902     free_irq(priv->irq_regular, priv);
0903     free_irq(priv->irq_dma, priv);
0904 
0905     iounmap(priv->sdmmc_base);
0906 
0907     clk_disable_unprepare(priv->clk_sdmmc);
0908     clk_put(priv->clk_sdmmc);
0909 
0910     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0911     release_mem_region(res->start, resource_size(res));
0912 
0913     mmc_free_host(mmc);
0914 
0915     dev_info(&pdev->dev, "WMT MCI device removed\n");
0916 
0917     return 0;
0918 }
0919 
0920 #ifdef CONFIG_PM
0921 static int wmt_mci_suspend(struct device *dev)
0922 {
0923     u32 reg_tmp;
0924     struct mmc_host *mmc = dev_get_drvdata(dev);
0925     struct wmt_mci_priv *priv;
0926 
0927     if (!mmc)
0928         return 0;
0929 
0930     priv = mmc_priv(mmc);
0931     reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
0932     writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base +
0933            SDMMC_BUSMODE);
0934 
0935     reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
0936     writew(reg_tmp & 0x5FFF, priv->sdmmc_base + SDMMC_BLKLEN);
0937 
0938     writeb(0xFF, priv->sdmmc_base + SDMMC_STS0);
0939     writeb(0xFF, priv->sdmmc_base + SDMMC_STS1);
0940 
0941     clk_disable(priv->clk_sdmmc);
0942     return 0;
0943 }
0944 
0945 static int wmt_mci_resume(struct device *dev)
0946 {
0947     u32 reg_tmp;
0948     struct mmc_host *mmc = dev_get_drvdata(dev);
0949     struct wmt_mci_priv *priv;
0950 
0951     if (mmc) {
0952         priv = mmc_priv(mmc);
0953         clk_enable(priv->clk_sdmmc);
0954 
0955         reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
0956         writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base +
0957                SDMMC_BUSMODE);
0958 
0959         reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
0960         writew(reg_tmp | (BLKL_GPI_CD | BLKL_INT_ENABLE),
0961                priv->sdmmc_base + SDMMC_BLKLEN);
0962 
0963         reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0);
0964         writeb(reg_tmp | INT0_DI_INT_EN, priv->sdmmc_base +
0965                SDMMC_INTMASK0);
0966 
0967     }
0968 
0969     return 0;
0970 }
0971 
0972 static const struct dev_pm_ops wmt_mci_pm = {
0973     .suspend        = wmt_mci_suspend,
0974     .resume         = wmt_mci_resume,
0975 };
0976 
0977 #define wmt_mci_pm_ops (&wmt_mci_pm)
0978 
0979 #else   /* !CONFIG_PM */
0980 
0981 #define wmt_mci_pm_ops NULL
0982 
0983 #endif
0984 
0985 static struct platform_driver wmt_mci_driver = {
0986     .probe = wmt_mci_probe,
0987     .remove = wmt_mci_remove,
0988     .driver = {
0989         .name = DRIVER_NAME,
0990         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0991         .pm = wmt_mci_pm_ops,
0992         .of_match_table = wmt_mci_dt_ids,
0993     },
0994 };
0995 
0996 module_platform_driver(wmt_mci_driver);
0997 
0998 MODULE_DESCRIPTION("Wondermedia MMC/SD Driver");
0999 MODULE_AUTHOR("Tony Prisk");
1000 MODULE_LICENSE("GPL v2");
1001 MODULE_DEVICE_TABLE(of, wmt_mci_dt_ids);
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