mmc/host/wbsd.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  linux/drivers/mmc/host/wbsd.h - Winbond W83L51xD SD/MMC driver
0004  *
0005  *  Copyright (C) 2004-2007 Pierre Ossman, All Rights Reserved.
0006  */
0007
0008 #define LOCK_CODE       0xAA
0009
0010 #define WBSD_CONF_SWRST     0x02
0011 #define WBSD_CONF_DEVICE    0x07
0012 #define WBSD_CONF_ID_HI     0x20
0013 #define WBSD_CONF_ID_LO     0x21
0014 #define WBSD_CONF_POWER     0x22
0015 #define WBSD_CONF_PME       0x23
0016 #define WBSD_CONF_PMES      0x24
0017
0018 #define WBSD_CONF_ENABLE    0x30
0019 #define WBSD_CONF_PORT_HI   0x60
0020 #define WBSD_CONF_PORT_LO   0x61
0021 #define WBSD_CONF_IRQ       0x70
0022 #define WBSD_CONF_DRQ       0x74
0023
0024 #define WBSD_CONF_PINS      0xF0
0025
0026 #define DEVICE_SD       0x03
0027
0028 #define WBSD_PINS_DAT3_HI   0x20
0029 #define WBSD_PINS_DAT3_OUT  0x10
0030 #define WBSD_PINS_GP11_HI   0x04
0031 #define WBSD_PINS_DETECT_GP11   0x02
0032 #define WBSD_PINS_DETECT_DAT3   0x01
0033
0034 #define WBSD_CMDR       0x00
0035 #define WBSD_DFR        0x01
0036 #define WBSD_EIR        0x02
0037 #define WBSD_ISR        0x03
0038 #define WBSD_FSR        0x04
0039 #define WBSD_IDXR       0x05
0040 #define WBSD_DATAR      0x06
0041 #define WBSD_CSR        0x07
0042
0043 #define WBSD_EINT_CARD      0x40
0044 #define WBSD_EINT_FIFO_THRE 0x20
0045 #define WBSD_EINT_CRC       0x10
0046 #define WBSD_EINT_TIMEOUT   0x08
0047 #define WBSD_EINT_PROGEND   0x04
0048 #define WBSD_EINT_BUSYEND   0x02
0049 #define WBSD_EINT_TC        0x01
0050
0051 #define WBSD_INT_PENDING    0x80
0052 #define WBSD_INT_CARD       0x40
0053 #define WBSD_INT_FIFO_THRE  0x20
0054 #define WBSD_INT_CRC        0x10
0055 #define WBSD_INT_TIMEOUT    0x08
0056 #define WBSD_INT_PROGEND    0x04
0057 #define WBSD_INT_BUSYEND    0x02
0058 #define WBSD_INT_TC     0x01
0059
0060 #define WBSD_FIFO_EMPTY     0x80
0061 #define WBSD_FIFO_FULL      0x40
0062 #define WBSD_FIFO_EMTHRE    0x20
0063 #define WBSD_FIFO_FUTHRE    0x10
0064 #define WBSD_FIFO_SZMASK    0x0F
0065
0066 #define WBSD_MSLED      0x20
0067 #define WBSD_POWER_N        0x10
0068 #define WBSD_WRPT       0x04
0069 #define WBSD_CARDPRESENT    0x01
0070
0071 #define WBSD_IDX_CLK        0x01
0072 #define WBSD_IDX_PBSMSB     0x02
0073 #define WBSD_IDX_TAAC       0x03
0074 #define WBSD_IDX_NSAC       0x04
0075 #define WBSD_IDX_PBSLSB     0x05
0076 #define WBSD_IDX_SETUP      0x06
0077 #define WBSD_IDX_DMA        0x07
0078 #define WBSD_IDX_FIFOEN     0x08
0079 #define WBSD_IDX_STATUS     0x10
0080 #define WBSD_IDX_RSPLEN     0x1E
0081 #define WBSD_IDX_RESP0      0x1F
0082 #define WBSD_IDX_RESP1      0x20
0083 #define WBSD_IDX_RESP2      0x21
0084 #define WBSD_IDX_RESP3      0x22
0085 #define WBSD_IDX_RESP4      0x23
0086 #define WBSD_IDX_RESP5      0x24
0087 #define WBSD_IDX_RESP6      0x25
0088 #define WBSD_IDX_RESP7      0x26
0089 #define WBSD_IDX_RESP8      0x27
0090 #define WBSD_IDX_RESP9      0x28
0091 #define WBSD_IDX_RESP10     0x29
0092 #define WBSD_IDX_RESP11     0x2A
0093 #define WBSD_IDX_RESP12     0x2B
0094 #define WBSD_IDX_RESP13     0x2C
0095 #define WBSD_IDX_RESP14     0x2D
0096 #define WBSD_IDX_RESP15     0x2E
0097 #define WBSD_IDX_RESP16     0x2F
0098 #define WBSD_IDX_CRCSTATUS  0x30
0099 #define WBSD_IDX_ISR        0x3F
0100
0101 #define WBSD_CLK_375K       0x00
0102 #define WBSD_CLK_12M        0x01
0103 #define WBSD_CLK_16M        0x02
0104 #define WBSD_CLK_24M        0x03
0105
0106 #define WBSD_DATA_WIDTH     0x01
0107
0108 #define WBSD_DAT3_H     0x08
0109 #define WBSD_FIFO_RESET     0x04
0110 #define WBSD_SOFT_RESET     0x02
0111 #define WBSD_INC_INDEX      0x01
0112
0113 #define WBSD_DMA_SINGLE     0x02
0114 #define WBSD_DMA_ENABLE     0x01
0115
0116 #define WBSD_FIFOEN_EMPTY   0x20
0117 #define WBSD_FIFOEN_FULL    0x10
0118 #define WBSD_FIFO_THREMASK  0x0F
0119
0120 #define WBSD_BLOCK_READ     0x80
0121 #define WBSD_BLOCK_WRITE    0x40
0122 #define WBSD_BUSY       0x20
0123 #define WBSD_CARDTRAFFIC    0x04
0124 #define WBSD_SENDCMD        0x02
0125 #define WBSD_RECVRES        0x01
0126
0127 #define WBSD_RSP_SHORT      0x00
0128 #define WBSD_RSP_LONG       0x01
0129
0130 #define WBSD_CRC_MASK       0x1F
0131 #define WBSD_CRC_OK     0x05 /* S010E (00101) */
0132 #define WBSD_CRC_FAIL       0x0B /* S101E (01011) */
0133
0134 #define WBSD_DMA_SIZE       65536
0135
0136 struct wbsd_host
0137 {
0138     struct mmc_host*    mmc;        /* MMC structure */
0139
0140     spinlock_t      lock;       /* Mutex */
0141
0142     int         flags;      /* Driver states */
0143
0144 #define WBSD_FCARD_PRESENT  (1<<0)      /* Card is present */
0145 #define WBSD_FIGNORE_DETECT (1<<1)      /* Ignore card detection */
0146
0147     struct mmc_request* mrq;        /* Current request */
0148
0149     u8          isr;        /* Accumulated ISR */
0150
0151     struct scatterlist* cur_sg;     /* Current SG entry */
0152     unsigned int        num_sg;     /* Number of entries left */
0153
0154     unsigned int        offset;     /* Offset into current entry */
0155     unsigned int        remain;     /* Data left in curren entry */
0156
0157     char*           dma_buffer; /* ISA DMA buffer */
0158     dma_addr_t      dma_addr;   /* Physical address for same */
0159
0160     int         firsterr;   /* See fifo functions */
0161
0162     u8          clk;        /* Current clock speed */
0163     unsigned char       bus_width;  /* Current bus width */
0164
0165     int         config;     /* Config port */
0166     u8          unlock_code;    /* Code to unlock config */
0167
0168     int         chip_id;    /* ID of controller */
0169
0170     int         base;       /* I/O port base */
0171     int         irq;        /* Interrupt */
0172     int         dma;        /* DMA channel */
0173
0174     struct tasklet_struct   card_tasklet;   /* Tasklet structures */
0175     struct tasklet_struct   fifo_tasklet;
0176     struct tasklet_struct   crc_tasklet;
0177     struct tasklet_struct   timeout_tasklet;
0178     struct tasklet_struct   finish_tasklet;
0179
0180     struct timer_list   ignore_timer;   /* Ignore detection timer */
0181 };