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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver
0004  *  Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved.
0005  */
0006 
0007 #include <linux/pci.h>
0008 #include <linux/module.h>
0009 #include <linux/dma-mapping.h>
0010 #include <linux/highmem.h>
0011 #include <linux/delay.h>
0012 #include <linux/interrupt.h>
0013 
0014 #include <linux/mmc/host.h>
0015 
0016 #define DRV_NAME    "via_sdmmc"
0017 
0018 #define PCI_DEVICE_ID_VIA_9530  0x9530
0019 
0020 #define VIA_CRDR_SDC_OFF    0x200
0021 #define VIA_CRDR_DDMA_OFF   0x400
0022 #define VIA_CRDR_PCICTRL_OFF    0x600
0023 
0024 #define VIA_CRDR_MIN_CLOCK  375000
0025 #define VIA_CRDR_MAX_CLOCK  48000000
0026 
0027 /*
0028  * PCI registers
0029  */
0030 
0031 #define VIA_CRDR_PCI_WORK_MODE  0x40
0032 #define VIA_CRDR_PCI_DBG_MODE   0x41
0033 
0034 /*
0035  * SDC MMIO Registers
0036  */
0037 
0038 #define VIA_CRDR_SDCTRL         0x0
0039 #define VIA_CRDR_SDCTRL_START       0x01
0040 #define VIA_CRDR_SDCTRL_WRITE       0x04
0041 #define VIA_CRDR_SDCTRL_SINGLE_WR   0x10
0042 #define VIA_CRDR_SDCTRL_SINGLE_RD   0x20
0043 #define VIA_CRDR_SDCTRL_MULTI_WR    0x30
0044 #define VIA_CRDR_SDCTRL_MULTI_RD    0x40
0045 #define VIA_CRDR_SDCTRL_STOP        0x70
0046 
0047 #define VIA_CRDR_SDCTRL_RSP_NONE    0x0
0048 #define VIA_CRDR_SDCTRL_RSP_R1      0x10000
0049 #define VIA_CRDR_SDCTRL_RSP_R2      0x20000
0050 #define VIA_CRDR_SDCTRL_RSP_R3      0x30000
0051 #define VIA_CRDR_SDCTRL_RSP_R1B     0x90000
0052 
0053 #define VIA_CRDR_SDCARG     0x4
0054 
0055 #define VIA_CRDR_SDBUSMODE  0x8
0056 #define VIA_CRDR_SDMODE_4BIT    0x02
0057 #define VIA_CRDR_SDMODE_CLK_ON  0x40
0058 
0059 #define VIA_CRDR_SDBLKLEN   0xc
0060 /*
0061  * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048.
0062  * Bit 11 - Bit 13 : Reserved.
0063  * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design.
0064  * INTEN : Enable SD host interrupt.
0065  * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536.
0066  */
0067 #define VIA_CRDR_SDBLKLEN_GPIDET    0x2000
0068 #define VIA_CRDR_SDBLKLEN_INTEN     0x8000
0069 #define VIA_CRDR_MAX_BLOCK_COUNT    65536
0070 #define VIA_CRDR_MAX_BLOCK_LENGTH   2048
0071 
0072 #define VIA_CRDR_SDRESP0    0x10
0073 #define VIA_CRDR_SDRESP1    0x14
0074 #define VIA_CRDR_SDRESP2    0x18
0075 #define VIA_CRDR_SDRESP3    0x1c
0076 
0077 #define VIA_CRDR_SDCURBLKCNT    0x20
0078 
0079 #define VIA_CRDR_SDINTMASK  0x24
0080 /*
0081  * MBDIE : Multiple Blocks transfer Done Interrupt Enable
0082  * BDDIE : Block Data transfer Done Interrupt Enable
0083  * CIRIE : Card Insertion or Removal Interrupt Enable
0084  * CRDIE : Command-Response transfer Done Interrupt Enable
0085  * CRTOIE : Command-Response response TimeOut Interrupt Enable
0086  * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable
0087  * DTIE : Data access Timeout Interrupt Enable
0088  * SCIE : reSponse CRC error Interrupt Enable
0089  * RCIE : Read data CRC error Interrupt Enable
0090  * WCIE : Write data CRC error Interrupt Enable
0091  */
0092 #define VIA_CRDR_SDINTMASK_MBDIE    0x10
0093 #define VIA_CRDR_SDINTMASK_BDDIE    0x20
0094 #define VIA_CRDR_SDINTMASK_CIRIE    0x80
0095 #define VIA_CRDR_SDINTMASK_CRDIE    0x200
0096 #define VIA_CRDR_SDINTMASK_CRTOIE   0x400
0097 #define VIA_CRDR_SDINTMASK_ASCRDIE  0x800
0098 #define VIA_CRDR_SDINTMASK_DTIE     0x1000
0099 #define VIA_CRDR_SDINTMASK_SCIE     0x2000
0100 #define VIA_CRDR_SDINTMASK_RCIE     0x4000
0101 #define VIA_CRDR_SDINTMASK_WCIE     0x8000
0102 
0103 #define VIA_CRDR_SDACTIVE_INTMASK \
0104     (VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \
0105     | VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \
0106     | VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \
0107     | VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE)
0108 
0109 #define VIA_CRDR_SDSTATUS   0x28
0110 /*
0111  * CECC : Reserved
0112  * WP : SD card Write Protect status
0113  * SLOTD : Reserved
0114  * SLOTG : SD SLOT status(Gpi pin status)
0115  * MBD : Multiple Blocks transfer Done interrupt status
0116  * BDD : Block Data transfer Done interrupt status
0117  * CD : Reserved
0118  * CIR : Card Insertion or Removal interrupt detected on GPI pin
0119  * IO : Reserved
0120  * CRD : Command-Response transfer Done interrupt status
0121  * CRTO : Command-Response response TimeOut interrupt status
0122  * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status
0123  * DT : Data access Timeout interrupt status
0124  * SC : reSponse CRC error interrupt status
0125  * RC : Read data CRC error interrupt status
0126  * WC : Write data CRC error interrupt status
0127  */
0128 #define VIA_CRDR_SDSTS_CECC     0x01
0129 #define VIA_CRDR_SDSTS_WP       0x02
0130 #define VIA_CRDR_SDSTS_SLOTD        0x04
0131 #define VIA_CRDR_SDSTS_SLOTG        0x08
0132 #define VIA_CRDR_SDSTS_MBD      0x10
0133 #define VIA_CRDR_SDSTS_BDD      0x20
0134 #define VIA_CRDR_SDSTS_CD       0x40
0135 #define VIA_CRDR_SDSTS_CIR      0x80
0136 #define VIA_CRDR_SDSTS_IO       0x100
0137 #define VIA_CRDR_SDSTS_CRD      0x200
0138 #define VIA_CRDR_SDSTS_CRTO     0x400
0139 #define VIA_CRDR_SDSTS_ASCRDIE      0x800
0140 #define VIA_CRDR_SDSTS_DT       0x1000
0141 #define VIA_CRDR_SDSTS_SC       0x2000
0142 #define VIA_CRDR_SDSTS_RC       0x4000
0143 #define VIA_CRDR_SDSTS_WC       0x8000
0144 
0145 #define VIA_CRDR_SDSTS_IGN_MASK\
0146     (VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO)
0147 #define VIA_CRDR_SDSTS_INT_MASK \
0148     (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \
0149     | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \
0150     | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
0151     | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
0152 #define VIA_CRDR_SDSTS_W1C_MASK \
0153     (VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \
0154     | VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \
0155     | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
0156     | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
0157 #define  VIA_CRDR_SDSTS_CMD_MASK \
0158     (VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC)
0159 #define  VIA_CRDR_SDSTS_DATA_MASK\
0160     (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \
0161     | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
0162 
0163 #define VIA_CRDR_SDSTATUS2  0x2a
0164 /*
0165  * CFE : Enable SD host automatic Clock FReezing
0166  */
0167 #define VIA_CRDR_SDSTS_CFE      0x80
0168 
0169 #define VIA_CRDR_SDRSPTMO   0x2C
0170 
0171 #define VIA_CRDR_SDCLKSEL   0x30
0172 
0173 #define VIA_CRDR_SDEXTCTRL  0x34
0174 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD  0x01
0175 #define VIS_CRDR_SDEXTCTRL_SHIFT_9  0x02
0176 #define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04
0177 #define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08
0178 #define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10
0179 #define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20
0180 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40
0181 #define VIA_CRDR_SDEXTCTRL_HISPD    0x80
0182 /* 0x38-0xFF reserved */
0183 
0184 /*
0185  * Data DMA Control Registers
0186  */
0187 
0188 #define VIA_CRDR_DMABASEADD 0x0
0189 #define VIA_CRDR_DMACOUNTER 0x4
0190 
0191 #define VIA_CRDR_DMACTRL    0x8
0192 /*
0193  * DIR :Transaction Direction
0194  * 0 : From card to memory
0195  * 1 : From memory to card
0196  */
0197 #define VIA_CRDR_DMACTRL_DIR        0x100
0198 #define VIA_CRDR_DMACTRL_ENIRQ      0x10000
0199 #define VIA_CRDR_DMACTRL_SFTRST     0x1000000
0200 
0201 #define VIA_CRDR_DMASTS     0xc
0202 
0203 #define VIA_CRDR_DMASTART   0x10
0204 /*0x14-0xFF reserved*/
0205 
0206 /*
0207  * PCI Control Registers
0208  */
0209 
0210 /*0x0 - 0x1 reserved*/
0211 #define VIA_CRDR_PCICLKGATT 0x2
0212 /*
0213  * SFTRST :
0214  * 0 : Soft reset all the controller and it will be de-asserted automatically
0215  * 1 : Soft reset is de-asserted
0216  */
0217 #define VIA_CRDR_PCICLKGATT_SFTRST  0x01
0218 /*
0219  * 3V3 : Pad power select
0220  * 0 : 1.8V
0221  * 1 : 3.3V
0222  * NOTE : No mater what the actual value should be, this bit always
0223  * read as 0. This is a hardware bug.
0224  */
0225 #define VIA_CRDR_PCICLKGATT_3V3 0x10
0226 /*
0227  * PAD_PWRON : Pad Power on/off select
0228  * 0 : Power off
0229  * 1 : Power on
0230   * NOTE : No mater what the actual value should be, this bit always
0231  * read as 0. This is a hardware bug.
0232  */
0233 #define VIA_CRDR_PCICLKGATT_PAD_PWRON   0x20
0234 
0235 #define VIA_CRDR_PCISDCCLK  0x5
0236 
0237 #define VIA_CRDR_PCIDMACLK  0x7
0238 #define VIA_CRDR_PCIDMACLK_SDC      0x2
0239 
0240 #define VIA_CRDR_PCIINTCTRL 0x8
0241 #define VIA_CRDR_PCIINTCTRL_SDCIRQEN    0x04
0242 
0243 #define VIA_CRDR_PCIINTSTATUS   0x9
0244 #define VIA_CRDR_PCIINTSTATUS_SDC   0x04
0245 
0246 #define  VIA_CRDR_PCITMOCTRL    0xa
0247 #define VIA_CRDR_PCITMOCTRL_NO      0x0
0248 #define VIA_CRDR_PCITMOCTRL_32US    0x1
0249 #define VIA_CRDR_PCITMOCTRL_256US   0x2
0250 #define VIA_CRDR_PCITMOCTRL_1024US  0x3
0251 #define VIA_CRDR_PCITMOCTRL_256MS   0x4
0252 #define VIA_CRDR_PCITMOCTRL_512MS   0x5
0253 #define VIA_CRDR_PCITMOCTRL_1024MS  0x6
0254 
0255 /*0xB-0xFF reserved*/
0256 
0257 enum PCI_HOST_CLK_CONTROL {
0258     PCI_CLK_375K = 0x03,
0259     PCI_CLK_8M = 0x04,
0260     PCI_CLK_12M = 0x00,
0261     PCI_CLK_16M = 0x05,
0262     PCI_CLK_24M = 0x01,
0263     PCI_CLK_33M = 0x06,
0264     PCI_CLK_48M = 0x02
0265 };
0266 
0267 struct sdhcreg {
0268     u32 sdcontrol_reg;
0269     u32 sdcmdarg_reg;
0270     u32 sdbusmode_reg;
0271     u32 sdblklen_reg;
0272     u32 sdresp_reg[4];
0273     u32 sdcurblkcnt_reg;
0274     u32 sdintmask_reg;
0275     u32 sdstatus_reg;
0276     u32 sdrsptmo_reg;
0277     u32 sdclksel_reg;
0278     u32 sdextctrl_reg;
0279 };
0280 
0281 struct pcictrlreg {
0282     u8 reserve[2];
0283     u8 pciclkgat_reg;
0284     u8 pcinfcclk_reg;
0285     u8 pcimscclk_reg;
0286     u8 pcisdclk_reg;
0287     u8 pcicaclk_reg;
0288     u8 pcidmaclk_reg;
0289     u8 pciintctrl_reg;
0290     u8 pciintstatus_reg;
0291     u8 pcitmoctrl_reg;
0292     u8 Resv;
0293 };
0294 
0295 struct via_crdr_mmc_host {
0296     struct mmc_host *mmc;
0297     struct mmc_request *mrq;
0298     struct mmc_command *cmd;
0299     struct mmc_data *data;
0300 
0301     void __iomem *mmiobase;
0302     void __iomem *sdhc_mmiobase;
0303     void __iomem *ddma_mmiobase;
0304     void __iomem *pcictrl_mmiobase;
0305 
0306     struct pcictrlreg pm_pcictrl_reg;
0307     struct sdhcreg pm_sdhc_reg;
0308 
0309     struct work_struct carddet_work;
0310     struct tasklet_struct finish_tasklet;
0311 
0312     struct timer_list timer;
0313     spinlock_t lock;
0314     u8 power;
0315     int reject;
0316     unsigned int quirks;
0317 };
0318 
0319 /* some devices need a very long delay for power to stabilize */
0320 #define VIA_CRDR_QUIRK_300MS_PWRDELAY   0x0001
0321 
0322 #define VIA_CMD_TIMEOUT_MS      1000
0323 
0324 static const struct pci_device_id via_ids[] = {
0325     {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_9530,
0326       PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
0327     {0,}
0328 };
0329 
0330 MODULE_DEVICE_TABLE(pci, via_ids);
0331 
0332 static void via_print_sdchc(struct via_crdr_mmc_host *host)
0333 {
0334     void __iomem *addrbase = host->sdhc_mmiobase;
0335 
0336     pr_debug("SDC MMIO Registers:\n");
0337     pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n",
0338          readl(addrbase + VIA_CRDR_SDCTRL),
0339          readl(addrbase + VIA_CRDR_SDCARG),
0340          readl(addrbase + VIA_CRDR_SDBUSMODE));
0341     pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n",
0342          readl(addrbase + VIA_CRDR_SDBLKLEN),
0343          readl(addrbase + VIA_CRDR_SDCURBLKCNT),
0344          readl(addrbase + VIA_CRDR_SDINTMASK));
0345     pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n",
0346          readl(addrbase + VIA_CRDR_SDSTATUS),
0347          readl(addrbase + VIA_CRDR_SDCLKSEL),
0348          readl(addrbase + VIA_CRDR_SDEXTCTRL));
0349 }
0350 
0351 static void via_print_pcictrl(struct via_crdr_mmc_host *host)
0352 {
0353     void __iomem *addrbase = host->pcictrl_mmiobase;
0354 
0355     pr_debug("PCI Control Registers:\n");
0356     pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n",
0357          readb(addrbase + VIA_CRDR_PCICLKGATT),
0358          readb(addrbase + VIA_CRDR_PCISDCCLK),
0359          readb(addrbase + VIA_CRDR_PCIDMACLK));
0360     pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n",
0361          readb(addrbase + VIA_CRDR_PCIINTCTRL),
0362          readb(addrbase + VIA_CRDR_PCIINTSTATUS));
0363 }
0364 
0365 static void via_save_pcictrlreg(struct via_crdr_mmc_host *host)
0366 {
0367     struct pcictrlreg *pm_pcictrl_reg;
0368     void __iomem *addrbase;
0369 
0370     pm_pcictrl_reg = &(host->pm_pcictrl_reg);
0371     addrbase = host->pcictrl_mmiobase;
0372 
0373     pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT);
0374     pm_pcictrl_reg->pciclkgat_reg |=
0375         VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
0376     pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK);
0377     pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK);
0378     pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL);
0379     pm_pcictrl_reg->pciintstatus_reg =
0380         readb(addrbase + VIA_CRDR_PCIINTSTATUS);
0381     pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL);
0382 }
0383 
0384 static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host)
0385 {
0386     struct pcictrlreg *pm_pcictrl_reg;
0387     void __iomem *addrbase;
0388 
0389     pm_pcictrl_reg = &(host->pm_pcictrl_reg);
0390     addrbase = host->pcictrl_mmiobase;
0391 
0392     writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT);
0393     writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK);
0394     writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK);
0395     writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL);
0396     writeb(pm_pcictrl_reg->pciintstatus_reg,
0397         addrbase + VIA_CRDR_PCIINTSTATUS);
0398     writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL);
0399 }
0400 
0401 static void via_save_sdcreg(struct via_crdr_mmc_host *host)
0402 {
0403     struct sdhcreg *pm_sdhc_reg;
0404     void __iomem *addrbase;
0405 
0406     pm_sdhc_reg = &(host->pm_sdhc_reg);
0407     addrbase = host->sdhc_mmiobase;
0408 
0409     pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL);
0410     pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG);
0411     pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE);
0412     pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN);
0413     pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT);
0414     pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK);
0415     pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS);
0416     pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO);
0417     pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL);
0418     pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL);
0419 }
0420 
0421 static void via_restore_sdcreg(struct via_crdr_mmc_host *host)
0422 {
0423     struct sdhcreg *pm_sdhc_reg;
0424     void __iomem *addrbase;
0425 
0426     pm_sdhc_reg = &(host->pm_sdhc_reg);
0427     addrbase = host->sdhc_mmiobase;
0428 
0429     writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
0430     writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
0431     writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE);
0432     writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN);
0433     writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT);
0434     writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
0435     writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS);
0436     writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
0437     writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
0438     writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
0439 }
0440 
0441 static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost)
0442 {
0443     if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY)
0444         msleep(300);
0445     else
0446         msleep(3);
0447 }
0448 
0449 static void via_set_ddma(struct via_crdr_mmc_host *host,
0450              dma_addr_t dmaaddr, u32 count, int dir, int enirq)
0451 {
0452     void __iomem *addrbase;
0453     u32 ctrl_data = 0;
0454 
0455     if (enirq)
0456         ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ;
0457 
0458     if (dir)
0459         ctrl_data |= VIA_CRDR_DMACTRL_DIR;
0460 
0461     addrbase = host->ddma_mmiobase;
0462 
0463     writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD);
0464     writel(count, addrbase + VIA_CRDR_DMACOUNTER);
0465     writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL);
0466     writel(0x01, addrbase + VIA_CRDR_DMASTART);
0467 
0468     /* It seems that our DMA can not work normally with 375kHz clock */
0469     /* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */
0470     addrbase = host->pcictrl_mmiobase;
0471     if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) {
0472         dev_info(host->mmc->parent, "forcing card speed to 8MHz\n");
0473         writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK);
0474     }
0475 }
0476 
0477 static void via_sdc_preparedata(struct via_crdr_mmc_host *host,
0478                 struct mmc_data *data)
0479 {
0480     void __iomem *addrbase;
0481     u32 blk_reg;
0482     int count;
0483 
0484     WARN_ON(host->data);
0485 
0486     /* Sanity checks */
0487     BUG_ON(data->blksz > host->mmc->max_blk_size);
0488     BUG_ON(data->blocks > host->mmc->max_blk_count);
0489 
0490     host->data = data;
0491 
0492     count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
0493         ((data->flags & MMC_DATA_READ) ?
0494         DMA_FROM_DEVICE : DMA_TO_DEVICE));
0495     BUG_ON(count != 1);
0496 
0497     via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg),
0498         (data->flags & MMC_DATA_WRITE) ? 1 : 0, 1);
0499 
0500     addrbase = host->sdhc_mmiobase;
0501 
0502     blk_reg = data->blksz - 1;
0503     blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
0504     blk_reg |= (data->blocks) << 16;
0505 
0506     writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN);
0507 }
0508 
0509 static void via_sdc_get_response(struct via_crdr_mmc_host *host,
0510                  struct mmc_command *cmd)
0511 {
0512     void __iomem *addrbase = host->sdhc_mmiobase;
0513     u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0);
0514     u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1);
0515     u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2);
0516     u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3);
0517 
0518     if (cmd->flags & MMC_RSP_136) {
0519         cmd->resp[0] = ((u8) (dwdata1)) |
0520             (((u8) (dwdata0 >> 24)) << 8) |
0521             (((u8) (dwdata0 >> 16)) << 16) |
0522             (((u8) (dwdata0 >> 8)) << 24);
0523 
0524         cmd->resp[1] = ((u8) (dwdata2)) |
0525             (((u8) (dwdata1 >> 24)) << 8) |
0526             (((u8) (dwdata1 >> 16)) << 16) |
0527             (((u8) (dwdata1 >> 8)) << 24);
0528 
0529         cmd->resp[2] = ((u8) (dwdata3)) |
0530             (((u8) (dwdata2 >> 24)) << 8) |
0531             (((u8) (dwdata2 >> 16)) << 16) |
0532             (((u8) (dwdata2 >> 8)) << 24);
0533 
0534         cmd->resp[3] = 0xff |
0535             ((((u8) (dwdata3 >> 24))) << 8) |
0536             (((u8) (dwdata3 >> 16)) << 16) |
0537             (((u8) (dwdata3 >> 8)) << 24);
0538     } else {
0539         dwdata0 >>= 8;
0540         cmd->resp[0] = ((dwdata0 & 0xff) << 24) |
0541             (((dwdata0 >> 8) & 0xff) << 16) |
0542             (((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff);
0543 
0544         dwdata1 >>= 8;
0545         cmd->resp[1] = ((dwdata1 & 0xff) << 24) |
0546             (((dwdata1 >> 8) & 0xff) << 16) |
0547             (((dwdata1 >> 16) & 0xff) << 8);
0548     }
0549 }
0550 
0551 static void via_sdc_send_command(struct via_crdr_mmc_host *host,
0552                  struct mmc_command *cmd)
0553 {
0554     void __iomem *addrbase;
0555     struct mmc_data *data;
0556     unsigned int timeout_ms;
0557     u32 cmdctrl = 0;
0558 
0559     WARN_ON(host->cmd);
0560 
0561     data = cmd->data;
0562     host->cmd = cmd;
0563 
0564     timeout_ms = cmd->busy_timeout ? cmd->busy_timeout : VIA_CMD_TIMEOUT_MS;
0565     mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout_ms));
0566 
0567     /*Command index*/
0568     cmdctrl = cmd->opcode << 8;
0569 
0570     /*Response type*/
0571     switch (mmc_resp_type(cmd)) {
0572     case MMC_RSP_NONE:
0573         cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE;
0574         break;
0575     case MMC_RSP_R1:
0576         cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1;
0577         break;
0578     case MMC_RSP_R1B:
0579         cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B;
0580         break;
0581     case MMC_RSP_R2:
0582         cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2;
0583         break;
0584     case MMC_RSP_R3:
0585         cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3;
0586         break;
0587     default:
0588         pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc));
0589         break;
0590     }
0591 
0592     if (!(cmd->data))
0593         goto nodata;
0594 
0595     via_sdc_preparedata(host, data);
0596 
0597     /*Command control*/
0598     if (data->blocks > 1) {
0599         if (data->flags & MMC_DATA_WRITE) {
0600             cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
0601             cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR;
0602         } else {
0603             cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD;
0604         }
0605     } else {
0606         if (data->flags & MMC_DATA_WRITE) {
0607             cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
0608             cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR;
0609         } else {
0610             cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD;
0611         }
0612     }
0613 
0614 nodata:
0615     if (cmd == host->mrq->stop)
0616         cmdctrl |= VIA_CRDR_SDCTRL_STOP;
0617 
0618     cmdctrl |= VIA_CRDR_SDCTRL_START;
0619 
0620     addrbase = host->sdhc_mmiobase;
0621     writel(cmd->arg, addrbase + VIA_CRDR_SDCARG);
0622     writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL);
0623 }
0624 
0625 static void via_sdc_finish_data(struct via_crdr_mmc_host *host)
0626 {
0627     struct mmc_data *data;
0628 
0629     BUG_ON(!host->data);
0630 
0631     data = host->data;
0632     host->data = NULL;
0633 
0634     if (data->error)
0635         data->bytes_xfered = 0;
0636     else
0637         data->bytes_xfered = data->blocks * data->blksz;
0638 
0639     dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
0640         ((data->flags & MMC_DATA_READ) ?
0641         DMA_FROM_DEVICE : DMA_TO_DEVICE));
0642 
0643     if (data->stop)
0644         via_sdc_send_command(host, data->stop);
0645     else
0646         tasklet_schedule(&host->finish_tasklet);
0647 }
0648 
0649 static void via_sdc_finish_command(struct via_crdr_mmc_host *host)
0650 {
0651     via_sdc_get_response(host, host->cmd);
0652 
0653     host->cmd->error = 0;
0654 
0655     if (!host->cmd->data)
0656         tasklet_schedule(&host->finish_tasklet);
0657 
0658     host->cmd = NULL;
0659 }
0660 
0661 static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq)
0662 {
0663     void __iomem *addrbase;
0664     struct via_crdr_mmc_host *host;
0665     unsigned long flags;
0666     u16 status;
0667 
0668     host = mmc_priv(mmc);
0669 
0670     spin_lock_irqsave(&host->lock, flags);
0671 
0672     addrbase = host->pcictrl_mmiobase;
0673     writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
0674 
0675     status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
0676     status &= VIA_CRDR_SDSTS_W1C_MASK;
0677     writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
0678 
0679     WARN_ON(host->mrq != NULL);
0680     host->mrq = mrq;
0681 
0682     status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
0683     if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) {
0684         host->mrq->cmd->error = -ENOMEDIUM;
0685         tasklet_schedule(&host->finish_tasklet);
0686     } else {
0687         via_sdc_send_command(host, mrq->cmd);
0688     }
0689 
0690     spin_unlock_irqrestore(&host->lock, flags);
0691 }
0692 
0693 static void via_sdc_set_power(struct via_crdr_mmc_host *host,
0694                   unsigned short power, unsigned int on)
0695 {
0696     unsigned long flags;
0697     u8 gatt;
0698 
0699     spin_lock_irqsave(&host->lock, flags);
0700 
0701     host->power = (1 << power);
0702 
0703     gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
0704     if (host->power == MMC_VDD_165_195)
0705         gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
0706     else
0707         gatt |= VIA_CRDR_PCICLKGATT_3V3;
0708     if (on)
0709         gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON;
0710     else
0711         gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
0712     writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
0713 
0714     spin_unlock_irqrestore(&host->lock, flags);
0715 
0716     via_pwron_sleep(host);
0717 }
0718 
0719 static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
0720 {
0721     struct via_crdr_mmc_host *host;
0722     unsigned long flags;
0723     void __iomem *addrbase;
0724     u32 org_data, sdextctrl;
0725     u8 clock;
0726 
0727     host = mmc_priv(mmc);
0728 
0729     spin_lock_irqsave(&host->lock, flags);
0730 
0731     addrbase = host->sdhc_mmiobase;
0732     org_data = readl(addrbase + VIA_CRDR_SDBUSMODE);
0733     sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL);
0734 
0735     if (ios->bus_width == MMC_BUS_WIDTH_1)
0736         org_data &= ~VIA_CRDR_SDMODE_4BIT;
0737     else
0738         org_data |= VIA_CRDR_SDMODE_4BIT;
0739 
0740     if (ios->power_mode == MMC_POWER_OFF)
0741         org_data &= ~VIA_CRDR_SDMODE_CLK_ON;
0742     else
0743         org_data |= VIA_CRDR_SDMODE_CLK_ON;
0744 
0745     if (ios->timing == MMC_TIMING_SD_HS)
0746         sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD;
0747     else
0748         sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD;
0749 
0750     writel(org_data, addrbase + VIA_CRDR_SDBUSMODE);
0751     writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL);
0752 
0753     if (ios->clock >= 48000000)
0754         clock = PCI_CLK_48M;
0755     else if (ios->clock >= 33000000)
0756         clock = PCI_CLK_33M;
0757     else if (ios->clock >= 24000000)
0758         clock = PCI_CLK_24M;
0759     else if (ios->clock >= 16000000)
0760         clock = PCI_CLK_16M;
0761     else if (ios->clock >= 12000000)
0762         clock = PCI_CLK_12M;
0763     else if (ios->clock >=  8000000)
0764         clock = PCI_CLK_8M;
0765     else
0766         clock = PCI_CLK_375K;
0767 
0768     addrbase = host->pcictrl_mmiobase;
0769     if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock)
0770         writeb(clock, addrbase + VIA_CRDR_PCISDCCLK);
0771 
0772     spin_unlock_irqrestore(&host->lock, flags);
0773 
0774     if (ios->power_mode != MMC_POWER_OFF)
0775         via_sdc_set_power(host, ios->vdd, 1);
0776     else
0777         via_sdc_set_power(host, ios->vdd, 0);
0778 }
0779 
0780 static int via_sdc_get_ro(struct mmc_host *mmc)
0781 {
0782     struct via_crdr_mmc_host *host;
0783     unsigned long flags;
0784     u16 status;
0785 
0786     host = mmc_priv(mmc);
0787 
0788     spin_lock_irqsave(&host->lock, flags);
0789 
0790     status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
0791 
0792     spin_unlock_irqrestore(&host->lock, flags);
0793 
0794     return !(status & VIA_CRDR_SDSTS_WP);
0795 }
0796 
0797 static const struct mmc_host_ops via_sdc_ops = {
0798     .request = via_sdc_request,
0799     .set_ios = via_sdc_set_ios,
0800     .get_ro = via_sdc_get_ro,
0801 };
0802 
0803 static void via_reset_pcictrl(struct via_crdr_mmc_host *host)
0804 {
0805     unsigned long flags;
0806     u8 gatt;
0807 
0808     spin_lock_irqsave(&host->lock, flags);
0809 
0810     via_save_pcictrlreg(host);
0811     via_save_sdcreg(host);
0812 
0813     spin_unlock_irqrestore(&host->lock, flags);
0814 
0815     gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
0816     if (host->power == MMC_VDD_165_195)
0817         gatt &= VIA_CRDR_PCICLKGATT_3V3;
0818     else
0819         gatt |= VIA_CRDR_PCICLKGATT_3V3;
0820     writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
0821     via_pwron_sleep(host);
0822     gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
0823     writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
0824     msleep(3);
0825 
0826     spin_lock_irqsave(&host->lock, flags);
0827 
0828     via_restore_pcictrlreg(host);
0829     via_restore_sdcreg(host);
0830 
0831     spin_unlock_irqrestore(&host->lock, flags);
0832 }
0833 
0834 static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask)
0835 {
0836     BUG_ON(intmask == 0);
0837 
0838     if (!host->cmd) {
0839         pr_err("%s: Got command interrupt 0x%x even "
0840                "though no command operation was in progress.\n",
0841                mmc_hostname(host->mmc), intmask);
0842         return;
0843     }
0844 
0845     if (intmask & VIA_CRDR_SDSTS_CRTO)
0846         host->cmd->error = -ETIMEDOUT;
0847     else if (intmask & VIA_CRDR_SDSTS_SC)
0848         host->cmd->error = -EILSEQ;
0849 
0850     if (host->cmd->error)
0851         tasklet_schedule(&host->finish_tasklet);
0852     else if (intmask & VIA_CRDR_SDSTS_CRD)
0853         via_sdc_finish_command(host);
0854 }
0855 
0856 static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask)
0857 {
0858     BUG_ON(intmask == 0);
0859 
0860     if (!host->data)
0861         return;
0862 
0863     if (intmask & VIA_CRDR_SDSTS_DT)
0864         host->data->error = -ETIMEDOUT;
0865     else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC))
0866         host->data->error = -EILSEQ;
0867 
0868     via_sdc_finish_data(host);
0869 }
0870 
0871 static irqreturn_t via_sdc_isr(int irq, void *dev_id)
0872 {
0873     struct via_crdr_mmc_host *sdhost = dev_id;
0874     void __iomem *addrbase;
0875     u8 pci_status;
0876     u16 sd_status;
0877     irqreturn_t result;
0878 
0879     if (!sdhost)
0880         return IRQ_NONE;
0881 
0882     spin_lock(&sdhost->lock);
0883 
0884     addrbase = sdhost->pcictrl_mmiobase;
0885     pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS);
0886     if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) {
0887         result = IRQ_NONE;
0888         goto out;
0889     }
0890 
0891     addrbase = sdhost->sdhc_mmiobase;
0892     sd_status = readw(addrbase + VIA_CRDR_SDSTATUS);
0893     sd_status &= VIA_CRDR_SDSTS_INT_MASK;
0894     sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK;
0895     if (!sd_status) {
0896         result = IRQ_NONE;
0897         goto out;
0898     }
0899 
0900     if (sd_status & VIA_CRDR_SDSTS_CIR) {
0901         writew(sd_status & VIA_CRDR_SDSTS_CIR,
0902             addrbase + VIA_CRDR_SDSTATUS);
0903 
0904         schedule_work(&sdhost->carddet_work);
0905     }
0906 
0907     sd_status &= ~VIA_CRDR_SDSTS_CIR;
0908     if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) {
0909         writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK,
0910             addrbase + VIA_CRDR_SDSTATUS);
0911         via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK);
0912     }
0913     if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) {
0914         writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK,
0915             addrbase + VIA_CRDR_SDSTATUS);
0916         via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK);
0917     }
0918 
0919     sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK);
0920     if (sd_status) {
0921         pr_err("%s: Unexpected interrupt 0x%x\n",
0922                mmc_hostname(sdhost->mmc), sd_status);
0923         writew(sd_status, addrbase + VIA_CRDR_SDSTATUS);
0924     }
0925 
0926     result = IRQ_HANDLED;
0927 
0928 out:
0929     spin_unlock(&sdhost->lock);
0930 
0931     return result;
0932 }
0933 
0934 static void via_sdc_timeout(struct timer_list *t)
0935 {
0936     struct via_crdr_mmc_host *sdhost;
0937     unsigned long flags;
0938 
0939     sdhost = from_timer(sdhost, t, timer);
0940 
0941     spin_lock_irqsave(&sdhost->lock, flags);
0942 
0943     if (sdhost->mrq) {
0944         pr_err("%s: Timeout waiting for hardware interrupt."
0945                "cmd:0x%x\n", mmc_hostname(sdhost->mmc),
0946                sdhost->mrq->cmd->opcode);
0947 
0948         if (sdhost->data) {
0949             writel(VIA_CRDR_DMACTRL_SFTRST,
0950                 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
0951             sdhost->data->error = -ETIMEDOUT;
0952             via_sdc_finish_data(sdhost);
0953         } else {
0954             if (sdhost->cmd)
0955                 sdhost->cmd->error = -ETIMEDOUT;
0956             else
0957                 sdhost->mrq->cmd->error = -ETIMEDOUT;
0958             tasklet_schedule(&sdhost->finish_tasklet);
0959         }
0960     }
0961 
0962     spin_unlock_irqrestore(&sdhost->lock, flags);
0963 }
0964 
0965 static void via_sdc_tasklet_finish(struct tasklet_struct *t)
0966 {
0967     struct via_crdr_mmc_host *host = from_tasklet(host, t, finish_tasklet);
0968     unsigned long flags;
0969     struct mmc_request *mrq;
0970 
0971     spin_lock_irqsave(&host->lock, flags);
0972 
0973     del_timer(&host->timer);
0974     mrq = host->mrq;
0975     host->mrq = NULL;
0976     host->cmd = NULL;
0977     host->data = NULL;
0978 
0979     spin_unlock_irqrestore(&host->lock, flags);
0980 
0981     mmc_request_done(host->mmc, mrq);
0982 }
0983 
0984 static void via_sdc_card_detect(struct work_struct *work)
0985 {
0986     struct via_crdr_mmc_host *host;
0987     void __iomem *addrbase;
0988     unsigned long flags;
0989     u16 status;
0990 
0991     host = container_of(work, struct via_crdr_mmc_host, carddet_work);
0992 
0993     addrbase = host->ddma_mmiobase;
0994     writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL);
0995 
0996     spin_lock_irqsave(&host->lock, flags);
0997 
0998     addrbase = host->pcictrl_mmiobase;
0999     writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
1000 
1001     addrbase = host->sdhc_mmiobase;
1002     status = readw(addrbase + VIA_CRDR_SDSTATUS);
1003     if (!(status & VIA_CRDR_SDSTS_SLOTG)) {
1004         if (host->mrq) {
1005             pr_err("%s: Card removed during transfer!\n",
1006                    mmc_hostname(host->mmc));
1007             host->mrq->cmd->error = -ENOMEDIUM;
1008             tasklet_schedule(&host->finish_tasklet);
1009         }
1010 
1011         spin_unlock_irqrestore(&host->lock, flags);
1012 
1013         via_reset_pcictrl(host);
1014 
1015         spin_lock_irqsave(&host->lock, flags);
1016     }
1017 
1018     spin_unlock_irqrestore(&host->lock, flags);
1019 
1020     via_print_pcictrl(host);
1021     via_print_sdchc(host);
1022 
1023     mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1024 }
1025 
1026 static void via_init_mmc_host(struct via_crdr_mmc_host *host)
1027 {
1028     struct mmc_host *mmc = host->mmc;
1029     void __iomem *addrbase;
1030     u32 lenreg;
1031     u32 status;
1032 
1033     timer_setup(&host->timer, via_sdc_timeout, 0);
1034 
1035     spin_lock_init(&host->lock);
1036 
1037     mmc->f_min = VIA_CRDR_MIN_CLOCK;
1038     mmc->f_max = VIA_CRDR_MAX_CLOCK;
1039     mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1040     mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED;
1041     mmc->ops = &via_sdc_ops;
1042 
1043     /*Hardware cannot do scatter lists*/
1044     mmc->max_segs = 1;
1045 
1046     mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH;
1047     mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT;
1048 
1049     mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
1050     mmc->max_req_size = mmc->max_seg_size;
1051 
1052     INIT_WORK(&host->carddet_work, via_sdc_card_detect);
1053 
1054     tasklet_setup(&host->finish_tasklet, via_sdc_tasklet_finish);
1055 
1056     addrbase = host->sdhc_mmiobase;
1057     writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1058     msleep(1);
1059 
1060     lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1061     writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1062 
1063     status = readw(addrbase + VIA_CRDR_SDSTATUS);
1064     status &= VIA_CRDR_SDSTS_W1C_MASK;
1065     writew(status, addrbase + VIA_CRDR_SDSTATUS);
1066 
1067     status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1068     status |= VIA_CRDR_SDSTS_CFE;
1069     writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1070 
1071     writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL);
1072 
1073     writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK);
1074     msleep(1);
1075 }
1076 
1077 static int via_sd_probe(struct pci_dev *pcidev,
1078                     const struct pci_device_id *id)
1079 {
1080     struct mmc_host *mmc;
1081     struct via_crdr_mmc_host *sdhost;
1082     u32 base, len;
1083     u8  gatt;
1084     int ret;
1085 
1086     pr_info(DRV_NAME
1087         ": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n",
1088         pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1089         (int)pcidev->revision);
1090 
1091     ret = pci_enable_device(pcidev);
1092     if (ret)
1093         return ret;
1094 
1095     ret = pci_request_regions(pcidev, DRV_NAME);
1096     if (ret)
1097         goto disable;
1098 
1099     pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0);
1100     pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0);
1101 
1102     mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev);
1103     if (!mmc) {
1104         ret = -ENOMEM;
1105         goto release;
1106     }
1107 
1108     sdhost = mmc_priv(mmc);
1109     sdhost->mmc = mmc;
1110     dev_set_drvdata(&pcidev->dev, sdhost);
1111 
1112     len = pci_resource_len(pcidev, 0);
1113     base = pci_resource_start(pcidev, 0);
1114     sdhost->mmiobase = ioremap(base, len);
1115     if (!sdhost->mmiobase) {
1116         ret = -ENOMEM;
1117         goto free_mmc_host;
1118     }
1119 
1120     sdhost->sdhc_mmiobase =
1121         sdhost->mmiobase + VIA_CRDR_SDC_OFF;
1122     sdhost->ddma_mmiobase =
1123         sdhost->mmiobase + VIA_CRDR_DDMA_OFF;
1124     sdhost->pcictrl_mmiobase =
1125         sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF;
1126 
1127     sdhost->power = MMC_VDD_165_195;
1128 
1129     gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
1130     writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1131     via_pwron_sleep(sdhost);
1132     gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1133     writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1134     msleep(3);
1135 
1136     via_init_mmc_host(sdhost);
1137 
1138     ret =
1139         request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME,
1140             sdhost);
1141     if (ret)
1142         goto unmap;
1143 
1144     writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN,
1145            sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1146     writeb(VIA_CRDR_PCITMOCTRL_1024MS,
1147            sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL);
1148 
1149     /* device-specific quirks */
1150     if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
1151         pcidev->subsystem_device == 0x3891)
1152         sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY;
1153 
1154     mmc_add_host(mmc);
1155 
1156     return 0;
1157 
1158 unmap:
1159     iounmap(sdhost->mmiobase);
1160 free_mmc_host:
1161     dev_set_drvdata(&pcidev->dev, NULL);
1162     mmc_free_host(mmc);
1163 release:
1164     pci_release_regions(pcidev);
1165 disable:
1166     pci_disable_device(pcidev);
1167 
1168     return ret;
1169 }
1170 
1171 static void via_sd_remove(struct pci_dev *pcidev)
1172 {
1173     struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev);
1174     unsigned long flags;
1175     u8 gatt;
1176 
1177     spin_lock_irqsave(&sdhost->lock, flags);
1178 
1179     /* Ensure we don't accept more commands from mmc layer */
1180     sdhost->reject = 1;
1181 
1182     /* Disable generating further interrupts */
1183     writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1184 
1185     if (sdhost->mrq) {
1186         pr_err("%s: Controller removed during "
1187             "transfer\n", mmc_hostname(sdhost->mmc));
1188 
1189         /* make sure all DMA is stopped */
1190         writel(VIA_CRDR_DMACTRL_SFTRST,
1191             sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
1192         sdhost->mrq->cmd->error = -ENOMEDIUM;
1193         if (sdhost->mrq->stop)
1194             sdhost->mrq->stop->error = -ENOMEDIUM;
1195         tasklet_schedule(&sdhost->finish_tasklet);
1196     }
1197     spin_unlock_irqrestore(&sdhost->lock, flags);
1198 
1199     mmc_remove_host(sdhost->mmc);
1200 
1201     free_irq(pcidev->irq, sdhost);
1202 
1203     del_timer_sync(&sdhost->timer);
1204 
1205     tasklet_kill(&sdhost->finish_tasklet);
1206 
1207     /* switch off power */
1208     gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1209     gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
1210     writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1211 
1212     iounmap(sdhost->mmiobase);
1213     dev_set_drvdata(&pcidev->dev, NULL);
1214     mmc_free_host(sdhost->mmc);
1215     pci_release_regions(pcidev);
1216     pci_disable_device(pcidev);
1217 
1218     pr_info(DRV_NAME
1219         ": VIA SDMMC controller at %s [%04x:%04x] has been removed\n",
1220         pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1221 }
1222 
1223 static void __maybe_unused via_init_sdc_pm(struct via_crdr_mmc_host *host)
1224 {
1225     struct sdhcreg *pm_sdhcreg;
1226     void __iomem *addrbase;
1227     u32 lenreg;
1228     u16 status;
1229 
1230     pm_sdhcreg = &(host->pm_sdhc_reg);
1231     addrbase = host->sdhc_mmiobase;
1232 
1233     writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1234 
1235     lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1236     writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1237 
1238     status = readw(addrbase + VIA_CRDR_SDSTATUS);
1239     status &= VIA_CRDR_SDSTS_W1C_MASK;
1240     writew(status, addrbase + VIA_CRDR_SDSTATUS);
1241 
1242     status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1243     status |= VIA_CRDR_SDSTS_CFE;
1244     writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1245 
1246     writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
1247     writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
1248     writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
1249     writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
1250     writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
1251     writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
1252 
1253     via_print_pcictrl(host);
1254     via_print_sdchc(host);
1255 }
1256 
1257 static int __maybe_unused via_sd_suspend(struct device *dev)
1258 {
1259     struct via_crdr_mmc_host *host;
1260     unsigned long flags;
1261 
1262     host = dev_get_drvdata(dev);
1263 
1264     spin_lock_irqsave(&host->lock, flags);
1265     via_save_pcictrlreg(host);
1266     via_save_sdcreg(host);
1267     spin_unlock_irqrestore(&host->lock, flags);
1268 
1269     device_wakeup_enable(dev);
1270 
1271     return 0;
1272 }
1273 
1274 static int __maybe_unused via_sd_resume(struct device *dev)
1275 {
1276     struct via_crdr_mmc_host *sdhost;
1277     u8 gatt;
1278 
1279     sdhost = dev_get_drvdata(dev);
1280 
1281     gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
1282     if (sdhost->power == MMC_VDD_165_195)
1283         gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
1284     else
1285         gatt |= VIA_CRDR_PCICLKGATT_3V3;
1286     writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1287     via_pwron_sleep(sdhost);
1288     gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1289     writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1290     msleep(3);
1291 
1292     msleep(100);
1293 
1294     via_restore_pcictrlreg(sdhost);
1295     via_init_sdc_pm(sdhost);
1296 
1297     return 0;
1298 }
1299 
1300 static SIMPLE_DEV_PM_OPS(via_sd_pm_ops, via_sd_suspend, via_sd_resume);
1301 
1302 static struct pci_driver via_sd_driver = {
1303     .name = DRV_NAME,
1304     .id_table = via_ids,
1305     .probe = via_sd_probe,
1306     .remove = via_sd_remove,
1307     .driver.pm = &via_sd_pm_ops,
1308 };
1309 
1310 module_pci_driver(via_sd_driver);
1311 
1312 MODULE_LICENSE("GPL");
1313 MODULE_AUTHOR("VIA Technologies Inc.");
1314 MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver");
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