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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (C) 2017-2018 Socionext Inc.
0004 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
0005 
0006 #include <linux/bitfield.h>
0007 #include <linux/bitops.h>
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/dma-mapping.h>
0011 #include <linux/mfd/tmio.h>
0012 #include <linux/mmc/host.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/of_device.h>
0016 #include <linux/pinctrl/consumer.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/reset.h>
0019 
0020 #include "tmio_mmc.h"
0021 
0022 #define   UNIPHIER_SD_CLK_CTL_DIV1024       BIT(16)
0023 #define   UNIPHIER_SD_CLK_CTL_DIV1      BIT(10)
0024 #define   UNIPHIER_SD_CLKCTL_OFFEN      BIT(9)  // auto SDCLK stop
0025 #define UNIPHIER_SD_CC_EXT_MODE     0x1b0
0026 #define   UNIPHIER_SD_CC_EXT_MODE_DMA       BIT(1)
0027 #define UNIPHIER_SD_HOST_MODE       0x1c8
0028 #define UNIPHIER_SD_VOLT        0x1e4
0029 #define   UNIPHIER_SD_VOLT_MASK         GENMASK(1, 0)
0030 #define   UNIPHIER_SD_VOLT_OFF          0
0031 #define   UNIPHIER_SD_VOLT_330          1   // 3.3V signal
0032 #define   UNIPHIER_SD_VOLT_180          2   // 1.8V signal
0033 #define UNIPHIER_SD_DMA_MODE        0x410
0034 #define   UNIPHIER_SD_DMA_MODE_DIR_MASK     GENMASK(17, 16)
0035 #define   UNIPHIER_SD_DMA_MODE_DIR_TO_DEV   0
0036 #define   UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV 1
0037 #define   UNIPHIER_SD_DMA_MODE_WIDTH_MASK   GENMASK(5, 4)
0038 #define   UNIPHIER_SD_DMA_MODE_WIDTH_8      0
0039 #define   UNIPHIER_SD_DMA_MODE_WIDTH_16     1
0040 #define   UNIPHIER_SD_DMA_MODE_WIDTH_32     2
0041 #define   UNIPHIER_SD_DMA_MODE_WIDTH_64     3
0042 #define   UNIPHIER_SD_DMA_MODE_ADDR_INC     BIT(0)  // 1: inc, 0: fixed
0043 #define UNIPHIER_SD_DMA_CTL     0x414
0044 #define   UNIPHIER_SD_DMA_CTL_START BIT(0)  // start DMA (auto cleared)
0045 #define UNIPHIER_SD_DMA_RST     0x418
0046 #define   UNIPHIER_SD_DMA_RST_CH1   BIT(9)
0047 #define   UNIPHIER_SD_DMA_RST_CH0   BIT(8)
0048 #define UNIPHIER_SD_DMA_ADDR_L      0x440
0049 #define UNIPHIER_SD_DMA_ADDR_H      0x444
0050 
0051 /*
0052  * IP is extended to support various features: built-in DMA engine,
0053  * 1/1024 divisor, etc.
0054  */
0055 #define UNIPHIER_SD_CAP_EXTENDED_IP     BIT(0)
0056 /* RX channel of the built-in DMA controller is broken (Pro5) */
0057 #define UNIPHIER_SD_CAP_BROKEN_DMA_RX       BIT(1)
0058 
0059 struct uniphier_sd_priv {
0060     struct tmio_mmc_data tmio_data;
0061     struct pinctrl *pinctrl;
0062     struct pinctrl_state *pinstate_uhs;
0063     struct clk *clk;
0064     struct reset_control *rst;
0065     struct reset_control *rst_br;
0066     struct reset_control *rst_hw;
0067     struct dma_chan *chan;
0068     enum dma_data_direction dma_dir;
0069     unsigned long clk_rate;
0070     unsigned long caps;
0071 };
0072 
0073 static void *uniphier_sd_priv(struct tmio_mmc_host *host)
0074 {
0075     return container_of(host->pdata, struct uniphier_sd_priv, tmio_data);
0076 }
0077 
0078 static void uniphier_sd_dma_endisable(struct tmio_mmc_host *host, int enable)
0079 {
0080     sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
0081 }
0082 
0083 /* external DMA engine */
0084 static void uniphier_sd_external_dma_issue(struct tasklet_struct *t)
0085 {
0086     struct tmio_mmc_host *host = from_tasklet(host, t, dma_issue);
0087     struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
0088 
0089     uniphier_sd_dma_endisable(host, 1);
0090     dma_async_issue_pending(priv->chan);
0091 }
0092 
0093 static void uniphier_sd_external_dma_callback(void *param,
0094                     const struct dmaengine_result *result)
0095 {
0096     struct tmio_mmc_host *host = param;
0097     struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
0098     unsigned long flags;
0099 
0100     dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
0101              priv->dma_dir);
0102 
0103     spin_lock_irqsave(&host->lock, flags);
0104 
0105     if (result->result == DMA_TRANS_NOERROR) {
0106         /*
0107          * When the external DMA engine is enabled, strangely enough,
0108          * the DATAEND flag can be asserted even if the DMA engine has
0109          * not been kicked yet.  Enable the TMIO_STAT_DATAEND irq only
0110          * after we make sure the DMA engine finishes the transfer,
0111          * hence, in this callback.
0112          */
0113         tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
0114     } else {
0115         host->data->error = -ETIMEDOUT;
0116         tmio_mmc_do_data_irq(host);
0117     }
0118 
0119     spin_unlock_irqrestore(&host->lock, flags);
0120 }
0121 
0122 static void uniphier_sd_external_dma_start(struct tmio_mmc_host *host,
0123                        struct mmc_data *data)
0124 {
0125     struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
0126     enum dma_transfer_direction dma_tx_dir;
0127     struct dma_async_tx_descriptor *desc;
0128     dma_cookie_t cookie;
0129     int sg_len;
0130 
0131     if (!priv->chan)
0132         goto force_pio;
0133 
0134     if (data->flags & MMC_DATA_READ) {
0135         priv->dma_dir = DMA_FROM_DEVICE;
0136         dma_tx_dir = DMA_DEV_TO_MEM;
0137     } else {
0138         priv->dma_dir = DMA_TO_DEVICE;
0139         dma_tx_dir = DMA_MEM_TO_DEV;
0140     }
0141 
0142     sg_len = dma_map_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
0143                 priv->dma_dir);
0144     if (sg_len == 0)
0145         goto force_pio;
0146 
0147     desc = dmaengine_prep_slave_sg(priv->chan, host->sg_ptr, sg_len,
0148                        dma_tx_dir, DMA_CTRL_ACK);
0149     if (!desc)
0150         goto unmap_sg;
0151 
0152     desc->callback_result = uniphier_sd_external_dma_callback;
0153     desc->callback_param = host;
0154 
0155     cookie = dmaengine_submit(desc);
0156     if (cookie < 0)
0157         goto unmap_sg;
0158 
0159     host->dma_on = true;
0160 
0161     return;
0162 
0163 unmap_sg:
0164     dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
0165              priv->dma_dir);
0166 force_pio:
0167     uniphier_sd_dma_endisable(host, 0);
0168 }
0169 
0170 static void uniphier_sd_external_dma_enable(struct tmio_mmc_host *host,
0171                         bool enable)
0172 {
0173 }
0174 
0175 static void uniphier_sd_external_dma_request(struct tmio_mmc_host *host,
0176                          struct tmio_mmc_data *pdata)
0177 {
0178     struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
0179     struct dma_chan *chan;
0180 
0181     chan = dma_request_chan(mmc_dev(host->mmc), "rx-tx");
0182     if (IS_ERR(chan)) {
0183         dev_warn(mmc_dev(host->mmc),
0184              "failed to request DMA channel. falling back to PIO\n");
0185         return; /* just use PIO even for -EPROBE_DEFER */
0186     }
0187 
0188     /* this driver uses a single channel for both RX an TX */
0189     priv->chan = chan;
0190     host->chan_rx = chan;
0191     host->chan_tx = chan;
0192 
0193     tasklet_setup(&host->dma_issue, uniphier_sd_external_dma_issue);
0194 }
0195 
0196 static void uniphier_sd_external_dma_release(struct tmio_mmc_host *host)
0197 {
0198     struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
0199 
0200     if (priv->chan)
0201         dma_release_channel(priv->chan);
0202 }
0203 
0204 static void uniphier_sd_external_dma_abort(struct tmio_mmc_host *host)
0205 {
0206     struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
0207 
0208     uniphier_sd_dma_endisable(host, 0);
0209 
0210     if (priv->chan)
0211         dmaengine_terminate_sync(priv->chan);
0212 }
0213 
0214 static void uniphier_sd_external_dma_dataend(struct tmio_mmc_host *host)
0215 {
0216     uniphier_sd_dma_endisable(host, 0);
0217 
0218     tmio_mmc_do_data_irq(host);
0219 }
0220 
0221 static const struct tmio_mmc_dma_ops uniphier_sd_external_dma_ops = {
0222     .start = uniphier_sd_external_dma_start,
0223     .enable = uniphier_sd_external_dma_enable,
0224     .request = uniphier_sd_external_dma_request,
0225     .release = uniphier_sd_external_dma_release,
0226     .abort = uniphier_sd_external_dma_abort,
0227     .dataend = uniphier_sd_external_dma_dataend,
0228 };
0229 
0230 static void uniphier_sd_internal_dma_issue(struct tasklet_struct *t)
0231 {
0232     struct tmio_mmc_host *host = from_tasklet(host, t, dma_issue);
0233     unsigned long flags;
0234 
0235     spin_lock_irqsave(&host->lock, flags);
0236     tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
0237     spin_unlock_irqrestore(&host->lock, flags);
0238 
0239     uniphier_sd_dma_endisable(host, 1);
0240     writel(UNIPHIER_SD_DMA_CTL_START, host->ctl + UNIPHIER_SD_DMA_CTL);
0241 }
0242 
0243 static void uniphier_sd_internal_dma_start(struct tmio_mmc_host *host,
0244                        struct mmc_data *data)
0245 {
0246     struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
0247     struct scatterlist *sg = host->sg_ptr;
0248     dma_addr_t dma_addr;
0249     unsigned int dma_mode_dir;
0250     u32 dma_mode;
0251     int sg_len;
0252 
0253     if ((data->flags & MMC_DATA_READ) && !host->chan_rx)
0254         goto force_pio;
0255 
0256     if (WARN_ON(host->sg_len != 1))
0257         goto force_pio;
0258 
0259     if (!IS_ALIGNED(sg->offset, 8))
0260         goto force_pio;
0261 
0262     if (data->flags & MMC_DATA_READ) {
0263         priv->dma_dir = DMA_FROM_DEVICE;
0264         dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV;
0265     } else {
0266         priv->dma_dir = DMA_TO_DEVICE;
0267         dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_TO_DEV;
0268     }
0269 
0270     sg_len = dma_map_sg(mmc_dev(host->mmc), sg, 1, priv->dma_dir);
0271     if (sg_len == 0)
0272         goto force_pio;
0273 
0274     dma_mode = FIELD_PREP(UNIPHIER_SD_DMA_MODE_DIR_MASK, dma_mode_dir);
0275     dma_mode |= FIELD_PREP(UNIPHIER_SD_DMA_MODE_WIDTH_MASK,
0276                    UNIPHIER_SD_DMA_MODE_WIDTH_64);
0277     dma_mode |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
0278 
0279     writel(dma_mode, host->ctl + UNIPHIER_SD_DMA_MODE);
0280 
0281     dma_addr = sg_dma_address(data->sg);
0282     writel(lower_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_L);
0283     writel(upper_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_H);
0284 
0285     host->dma_on = true;
0286 
0287     return;
0288 force_pio:
0289     uniphier_sd_dma_endisable(host, 0);
0290 }
0291 
0292 static void uniphier_sd_internal_dma_enable(struct tmio_mmc_host *host,
0293                         bool enable)
0294 {
0295 }
0296 
0297 static void uniphier_sd_internal_dma_request(struct tmio_mmc_host *host,
0298                          struct tmio_mmc_data *pdata)
0299 {
0300     struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
0301 
0302     /*
0303      * Due to a hardware bug, Pro5 cannot use DMA for RX.
0304      * We can still use DMA for TX, but PIO for RX.
0305      */
0306     if (!(priv->caps & UNIPHIER_SD_CAP_BROKEN_DMA_RX))
0307         host->chan_rx = (void *)0xdeadbeaf;
0308 
0309     host->chan_tx = (void *)0xdeadbeaf;
0310 
0311     tasklet_setup(&host->dma_issue, uniphier_sd_internal_dma_issue);
0312 }
0313 
0314 static void uniphier_sd_internal_dma_release(struct tmio_mmc_host *host)
0315 {
0316     /* Each value is set to zero to assume "disabling" each DMA */
0317     host->chan_rx = NULL;
0318     host->chan_tx = NULL;
0319 }
0320 
0321 static void uniphier_sd_internal_dma_abort(struct tmio_mmc_host *host)
0322 {
0323     u32 tmp;
0324 
0325     uniphier_sd_dma_endisable(host, 0);
0326 
0327     tmp = readl(host->ctl + UNIPHIER_SD_DMA_RST);
0328     tmp &= ~(UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0);
0329     writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST);
0330 
0331     tmp |= UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0;
0332     writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST);
0333 }
0334 
0335 static void uniphier_sd_internal_dma_dataend(struct tmio_mmc_host *host)
0336 {
0337     struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
0338 
0339     uniphier_sd_dma_endisable(host, 0);
0340     dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, 1, priv->dma_dir);
0341 
0342     tmio_mmc_do_data_irq(host);
0343 }
0344 
0345 static const struct tmio_mmc_dma_ops uniphier_sd_internal_dma_ops = {
0346     .start = uniphier_sd_internal_dma_start,
0347     .enable = uniphier_sd_internal_dma_enable,
0348     .request = uniphier_sd_internal_dma_request,
0349     .release = uniphier_sd_internal_dma_release,
0350     .abort = uniphier_sd_internal_dma_abort,
0351     .dataend = uniphier_sd_internal_dma_dataend,
0352 };
0353 
0354 static int uniphier_sd_clk_enable(struct tmio_mmc_host *host)
0355 {
0356     struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
0357     struct mmc_host *mmc = host->mmc;
0358     int ret;
0359 
0360     ret = clk_prepare_enable(priv->clk);
0361     if (ret)
0362         return ret;
0363 
0364     ret = clk_set_rate(priv->clk, ULONG_MAX);
0365     if (ret)
0366         goto disable_clk;
0367 
0368     priv->clk_rate = clk_get_rate(priv->clk);
0369 
0370     /* If max-frequency property is set, use it. */
0371     if (!mmc->f_max)
0372         mmc->f_max = priv->clk_rate;
0373 
0374     /*
0375      * 1/512 is the finest divisor in the original IP.  Newer versions
0376      * also supports 1/1024 divisor. (UniPhier-specific extension)
0377      */
0378     if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
0379         mmc->f_min = priv->clk_rate / 1024;
0380     else
0381         mmc->f_min = priv->clk_rate / 512;
0382 
0383     ret = reset_control_deassert(priv->rst);
0384     if (ret)
0385         goto disable_clk;
0386 
0387     ret = reset_control_deassert(priv->rst_br);
0388     if (ret)
0389         goto assert_rst;
0390 
0391     return 0;
0392 
0393 assert_rst:
0394     reset_control_assert(priv->rst);
0395 disable_clk:
0396     clk_disable_unprepare(priv->clk);
0397 
0398     return ret;
0399 }
0400 
0401 static void uniphier_sd_clk_disable(struct tmio_mmc_host *host)
0402 {
0403     struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
0404 
0405     reset_control_assert(priv->rst_br);
0406     reset_control_assert(priv->rst);
0407     clk_disable_unprepare(priv->clk);
0408 }
0409 
0410 static void uniphier_sd_hw_reset(struct mmc_host *mmc)
0411 {
0412     struct tmio_mmc_host *host = mmc_priv(mmc);
0413     struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
0414 
0415     reset_control_assert(priv->rst_hw);
0416     /* For eMMC, minimum is 1us but give it 9us for good measure */
0417     udelay(9);
0418     reset_control_deassert(priv->rst_hw);
0419     /* For eMMC, minimum is 200us but give it 300us for good measure */
0420     usleep_range(300, 1000);
0421 }
0422 
0423 static void uniphier_sd_set_clock(struct tmio_mmc_host *host,
0424                   unsigned int clock)
0425 {
0426     struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
0427     unsigned long divisor;
0428     u32 tmp;
0429 
0430     tmp = readl(host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
0431 
0432     /* stop the clock before changing its rate to avoid a glitch signal */
0433     tmp &= ~CLK_CTL_SCLKEN;
0434     writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
0435 
0436     if (clock == 0)
0437         return;
0438 
0439     tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1024;
0440     tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1;
0441     tmp &= ~CLK_CTL_DIV_MASK;
0442 
0443     divisor = priv->clk_rate / clock;
0444 
0445     /*
0446      * In the original IP, bit[7:0] represents the divisor.
0447      * bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2
0448      *
0449      * The IP does not define a way to achieve 1/1.  For UniPhier variants,
0450      * bit10 is used for 1/1.  Newer versions of UniPhier variants use
0451      * bit16 for 1/1024.
0452      */
0453     if (divisor <= 1)
0454         tmp |= UNIPHIER_SD_CLK_CTL_DIV1;
0455     else if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP && divisor > 512)
0456         tmp |= UNIPHIER_SD_CLK_CTL_DIV1024;
0457     else
0458         tmp |= roundup_pow_of_two(divisor) >> 2;
0459 
0460     writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
0461 
0462     tmp |= CLK_CTL_SCLKEN;
0463     writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
0464 }
0465 
0466 static void uniphier_sd_host_init(struct tmio_mmc_host *host)
0467 {
0468     struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
0469     u32 val;
0470 
0471     /*
0472      * Connected to 32bit AXI.
0473      * This register holds settings for SoC-specific internal bus
0474      * connection.  What is worse, the register spec was changed,
0475      * breaking the backward compatibility.  Write an appropriate
0476      * value depending on a flag associated with a compatible string.
0477      */
0478     if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
0479         val = 0x00000101;
0480     else
0481         val = 0x00000000;
0482 
0483     writel(val, host->ctl + UNIPHIER_SD_HOST_MODE);
0484 
0485     val = 0;
0486     /*
0487      * If supported, the controller can automatically
0488      * enable/disable the clock line to the card.
0489      */
0490     if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
0491         val |= UNIPHIER_SD_CLKCTL_OFFEN;
0492 
0493     writel(val, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
0494 }
0495 
0496 static int uniphier_sd_start_signal_voltage_switch(struct mmc_host *mmc,
0497                            struct mmc_ios *ios)
0498 {
0499     struct tmio_mmc_host *host = mmc_priv(mmc);
0500     struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
0501     struct pinctrl_state *pinstate = NULL;
0502     u32 val, tmp;
0503 
0504     switch (ios->signal_voltage) {
0505     case MMC_SIGNAL_VOLTAGE_330:
0506         val = UNIPHIER_SD_VOLT_330;
0507         break;
0508     case MMC_SIGNAL_VOLTAGE_180:
0509         val = UNIPHIER_SD_VOLT_180;
0510         pinstate = priv->pinstate_uhs;
0511         break;
0512     default:
0513         return -ENOTSUPP;
0514     }
0515 
0516     tmp = readl(host->ctl + UNIPHIER_SD_VOLT);
0517     tmp &= ~UNIPHIER_SD_VOLT_MASK;
0518     tmp |= FIELD_PREP(UNIPHIER_SD_VOLT_MASK, val);
0519     writel(tmp, host->ctl + UNIPHIER_SD_VOLT);
0520 
0521     if (pinstate)
0522         pinctrl_select_state(priv->pinctrl, pinstate);
0523     else
0524         pinctrl_select_default_state(mmc_dev(mmc));
0525 
0526     return 0;
0527 }
0528 
0529 static int uniphier_sd_uhs_init(struct tmio_mmc_host *host,
0530                 struct uniphier_sd_priv *priv)
0531 {
0532     priv->pinctrl = devm_pinctrl_get(mmc_dev(host->mmc));
0533     if (IS_ERR(priv->pinctrl))
0534         return PTR_ERR(priv->pinctrl);
0535 
0536     priv->pinstate_uhs = pinctrl_lookup_state(priv->pinctrl, "uhs");
0537     if (IS_ERR(priv->pinstate_uhs))
0538         return PTR_ERR(priv->pinstate_uhs);
0539 
0540     host->ops.start_signal_voltage_switch =
0541                     uniphier_sd_start_signal_voltage_switch;
0542 
0543     return 0;
0544 }
0545 
0546 static int uniphier_sd_probe(struct platform_device *pdev)
0547 {
0548     struct device *dev = &pdev->dev;
0549     struct uniphier_sd_priv *priv;
0550     struct tmio_mmc_data *tmio_data;
0551     struct tmio_mmc_host *host;
0552     int irq, ret;
0553 
0554     irq = platform_get_irq(pdev, 0);
0555     if (irq < 0)
0556         return irq;
0557 
0558     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0559     if (!priv)
0560         return -ENOMEM;
0561 
0562     priv->caps = (unsigned long)of_device_get_match_data(dev);
0563 
0564     priv->clk = devm_clk_get(dev, NULL);
0565     if (IS_ERR(priv->clk)) {
0566         dev_err(dev, "failed to get clock\n");
0567         return PTR_ERR(priv->clk);
0568     }
0569 
0570     priv->rst = devm_reset_control_get_shared(dev, "host");
0571     if (IS_ERR(priv->rst)) {
0572         dev_err(dev, "failed to get host reset\n");
0573         return PTR_ERR(priv->rst);
0574     }
0575 
0576     /* old version has one more reset */
0577     if (!(priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)) {
0578         priv->rst_br = devm_reset_control_get_shared(dev, "bridge");
0579         if (IS_ERR(priv->rst_br)) {
0580             dev_err(dev, "failed to get bridge reset\n");
0581             return PTR_ERR(priv->rst_br);
0582         }
0583     }
0584 
0585     tmio_data = &priv->tmio_data;
0586     tmio_data->flags |= TMIO_MMC_32BIT_DATA_PORT;
0587     tmio_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT;
0588 
0589     host = tmio_mmc_host_alloc(pdev, tmio_data);
0590     if (IS_ERR(host))
0591         return PTR_ERR(host);
0592 
0593     if (host->mmc->caps & MMC_CAP_HW_RESET) {
0594         priv->rst_hw = devm_reset_control_get_exclusive(dev, "hw");
0595         if (IS_ERR(priv->rst_hw)) {
0596             dev_err(dev, "failed to get hw reset\n");
0597             ret = PTR_ERR(priv->rst_hw);
0598             goto free_host;
0599         }
0600         host->ops.card_hw_reset = uniphier_sd_hw_reset;
0601     }
0602 
0603     if (host->mmc->caps & MMC_CAP_UHS) {
0604         ret = uniphier_sd_uhs_init(host, priv);
0605         if (ret) {
0606             dev_warn(dev,
0607                  "failed to setup UHS (error %d).  Disabling UHS.",
0608                  ret);
0609             host->mmc->caps &= ~MMC_CAP_UHS;
0610         }
0611     }
0612 
0613     if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
0614         host->dma_ops = &uniphier_sd_internal_dma_ops;
0615     else
0616         host->dma_ops = &uniphier_sd_external_dma_ops;
0617 
0618     host->bus_shift = 1;
0619     host->clk_enable = uniphier_sd_clk_enable;
0620     host->clk_disable = uniphier_sd_clk_disable;
0621     host->set_clock = uniphier_sd_set_clock;
0622 
0623     ret = uniphier_sd_clk_enable(host);
0624     if (ret)
0625         goto free_host;
0626 
0627     uniphier_sd_host_init(host);
0628 
0629     tmio_data->ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34;
0630     if (host->mmc->caps & MMC_CAP_UHS)
0631         tmio_data->ocr_mask |= MMC_VDD_165_195;
0632 
0633     tmio_data->max_segs = 1;
0634     tmio_data->max_blk_count = U16_MAX;
0635 
0636     ret = tmio_mmc_host_probe(host);
0637     if (ret)
0638         goto disable_clk;
0639 
0640     ret = devm_request_irq(dev, irq, tmio_mmc_irq, IRQF_SHARED,
0641                    dev_name(dev), host);
0642     if (ret)
0643         goto remove_host;
0644 
0645     return 0;
0646 
0647 remove_host:
0648     tmio_mmc_host_remove(host);
0649 disable_clk:
0650     uniphier_sd_clk_disable(host);
0651 free_host:
0652     tmio_mmc_host_free(host);
0653 
0654     return ret;
0655 }
0656 
0657 static int uniphier_sd_remove(struct platform_device *pdev)
0658 {
0659     struct tmio_mmc_host *host = platform_get_drvdata(pdev);
0660 
0661     tmio_mmc_host_remove(host);
0662     uniphier_sd_clk_disable(host);
0663     tmio_mmc_host_free(host);
0664 
0665     return 0;
0666 }
0667 
0668 static const struct of_device_id uniphier_sd_match[] = {
0669     {
0670         .compatible = "socionext,uniphier-sd-v2.91",
0671     },
0672     {
0673         .compatible = "socionext,uniphier-sd-v3.1",
0674         .data = (void *)(UNIPHIER_SD_CAP_EXTENDED_IP |
0675                  UNIPHIER_SD_CAP_BROKEN_DMA_RX),
0676     },
0677     {
0678         .compatible = "socionext,uniphier-sd-v3.1.1",
0679         .data = (void *)UNIPHIER_SD_CAP_EXTENDED_IP,
0680     },
0681     { /* sentinel */ }
0682 };
0683 MODULE_DEVICE_TABLE(of, uniphier_sd_match);
0684 
0685 static struct platform_driver uniphier_sd_driver = {
0686     .probe = uniphier_sd_probe,
0687     .remove = uniphier_sd_remove,
0688     .driver = {
0689         .name = "uniphier-sd",
0690         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0691         .of_match_table = uniphier_sd_match,
0692     },
0693 };
0694 module_platform_driver(uniphier_sd_driver);
0695 
0696 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
0697 MODULE_DESCRIPTION("UniPhier SD/eMMC host controller driver");
0698 MODULE_LICENSE("GPL v2");
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