mmc/host/toshsd.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  Toshiba PCI Secure Digital Host Controller Interface driver
0004  *
0005  *  Copyright (C) 2014 Ondrej Zary
0006  *  Copyright (C) 2007 Richard Betts, All Rights Reserved.
0007  *
0008  *      Based on asic3_mmc.c Copyright (c) 2005 SDG Systems, LLC
0009  */
0010
0011 #define HCLK    33000000    /* 33 MHz (PCI clock) */
0012
0013 #define SD_PCICFG_CLKSTOP   0x40    /* 0x1f = clock controller, 0 = stop */
0014 #define SD_PCICFG_GATEDCLK  0x41    /* Gated clock */
0015 #define SD_PCICFG_CLKMODE   0x42    /* Control clock of SD controller */
0016 #define SD_PCICFG_PINSTATUS 0x44    /* R/O: read status of SD pins */
0017 #define SD_PCICFG_POWER1    0x48
0018 #define SD_PCICFG_POWER2    0x49
0019 #define SD_PCICFG_POWER3    0x4a
0020 #define SD_PCICFG_CARDDETECT    0x4c
0021 #define SD_PCICFG_SLOTS     0x50    /* R/O: define support slot number */
0022 #define SD_PCICFG_EXTGATECLK1   0xf0    /* Could be used for gated clock */
0023 #define SD_PCICFG_EXTGATECLK2   0xf1    /* Could be used for gated clock */
0024 #define SD_PCICFG_EXTGATECLK3   0xf9    /* Bit 1: double buffer/single buffer */
0025 #define SD_PCICFG_SDLED_ENABLE1 0xfa
0026 #define SD_PCICFG_SDLED_ENABLE2 0xfe
0027
0028 #define SD_PCICFG_CLKMODE_DIV_DISABLE   BIT(0)
0029 #define SD_PCICFG_CLKSTOP_ENABLE_ALL    0x1f
0030 #define SD_PCICFG_LED_ENABLE1_START 0x12
0031 #define SD_PCICFG_LED_ENABLE2_START 0x80
0032
0033 #define SD_PCICFG_PWR1_33V  0x08    /* Set for 3.3 volts */
0034 #define SD_PCICFG_PWR1_OFF  0x00    /* Turn off power */
0035 #define SD_PCICFG_PWR2_AUTO 0x02
0036
0037 #define SD_CMD          0x00    /* also for SDIO */
0038 #define SD_ARG0         0x04    /* also for SDIO */
0039 #define SD_ARG1         0x06    /* also for SDIO */
0040 #define SD_STOPINTERNAL     0x08
0041 #define SD_BLOCKCOUNT       0x0a    /* also for SDIO */
0042 #define SD_RESPONSE0        0x0c    /* also for SDIO */
0043 #define SD_RESPONSE1        0x0e    /* also for SDIO */
0044 #define SD_RESPONSE2        0x10    /* also for SDIO */
0045 #define SD_RESPONSE3        0x12    /* also for SDIO */
0046 #define SD_RESPONSE4        0x14    /* also for SDIO */
0047 #define SD_RESPONSE5        0x16    /* also for SDIO */
0048 #define SD_RESPONSE6        0x18    /* also for SDIO */
0049 #define SD_RESPONSE7        0x1a    /* also for SDIO */
0050 #define SD_CARDSTATUS       0x1c    /* also for SDIO */
0051 #define SD_BUFFERCTRL       0x1e    /* also for SDIO */
0052 #define SD_INTMASKCARD      0x20    /* also for SDIO */
0053 #define SD_INTMASKBUFFER    0x22    /* also for SDIO */
0054 #define SD_CARDCLOCKCTRL    0x24
0055 #define SD_CARDXFERDATALEN  0x26    /* also for SDIO */
0056 #define SD_CARDOPTIONSETUP  0x28    /* also for SDIO */
0057 #define SD_ERRORSTATUS0     0x2c    /* also for SDIO */
0058 #define SD_ERRORSTATUS1     0x2e    /* also for SDIO */
0059 #define SD_DATAPORT     0x30    /* also for SDIO */
0060 #define SD_TRANSACTIONCTRL  0x34    /* also for SDIO */
0061 #define SD_SOFTWARERESET    0xe0    /* also for SDIO */
0062
0063 /* registers above marked "also for SDIO" and all SDIO registers below can be
0064  * accessed at SDIO_BASE + reg address */
0065 #define SDIO_BASE    0x100
0066
0067 #define SDIO_CARDPORTSEL    0x02
0068 #define SDIO_CARDINTCTRL    0x36
0069 #define SDIO_CLOCKNWAITCTRL 0x38
0070 #define SDIO_HOSTINFORMATION    0x3a
0071 #define SDIO_ERRORCTRL      0x3c
0072 #define SDIO_LEDCTRL        0x3e
0073
0074 #define SD_TRANSCTL_SET     BIT(8)
0075
0076 #define SD_CARDCLK_DIV_DISABLE  BIT(15)
0077 #define SD_CARDCLK_ENABLE_CLOCK BIT(8)
0078 #define SD_CARDCLK_CLK_DIV_512  BIT(7)
0079 #define SD_CARDCLK_CLK_DIV_256  BIT(6)
0080 #define SD_CARDCLK_CLK_DIV_128  BIT(5)
0081 #define SD_CARDCLK_CLK_DIV_64   BIT(4)
0082 #define SD_CARDCLK_CLK_DIV_32   BIT(3)
0083 #define SD_CARDCLK_CLK_DIV_16   BIT(2)
0084 #define SD_CARDCLK_CLK_DIV_8    BIT(1)
0085 #define SD_CARDCLK_CLK_DIV_4    BIT(0)
0086 #define SD_CARDCLK_CLK_DIV_2    0
0087
0088 #define SD_CARDOPT_REQUIRED     0x000e
0089 #define SD_CARDOPT_DATA_RESP_TIMEOUT(x) (((x) & 0x0f) << 4) /* 4 bits */
0090 #define SD_CARDOPT_C2_MODULE_ABSENT BIT(14)
0091 #define SD_CARDOPT_DATA_XFR_WIDTH_1 (1 << 15)
0092 #define SD_CARDOPT_DATA_XFR_WIDTH_4 (0 << 15)
0093
0094 #define SD_CMD_TYPE_CMD         (0 << 6)
0095 #define SD_CMD_TYPE_ACMD        (1 << 6)
0096 #define SD_CMD_TYPE_AUTHEN      (2 << 6)
0097 #define SD_CMD_RESP_TYPE_NONE       (3 << 8)
0098 #define SD_CMD_RESP_TYPE_EXT_R1     (4 << 8)
0099 #define SD_CMD_RESP_TYPE_EXT_R1B    (5 << 8)
0100 #define SD_CMD_RESP_TYPE_EXT_R2     (6 << 8)
0101 #define SD_CMD_RESP_TYPE_EXT_R3     (7 << 8)
0102 #define SD_CMD_RESP_TYPE_EXT_R6     (4 << 8)
0103 #define SD_CMD_RESP_TYPE_EXT_R7     (4 << 8)
0104 #define SD_CMD_DATA_PRESENT     BIT(11)
0105 #define SD_CMD_TRANSFER_READ        BIT(12)
0106 #define SD_CMD_MULTI_BLOCK      BIT(13)
0107 #define SD_CMD_SECURITY_CMD     BIT(14)
0108
0109 #define SD_STOPINT_ISSUE_CMD12      BIT(0)
0110 #define SD_STOPINT_AUTO_ISSUE_CMD12 BIT(8)
0111
0112 #define SD_CARD_RESP_END    BIT(0)
0113 #define SD_CARD_RW_END      BIT(2)
0114 #define SD_CARD_CARD_REMOVED_0  BIT(3)
0115 #define SD_CARD_CARD_INSERTED_0 BIT(4)
0116 #define SD_CARD_PRESENT_0   BIT(5)
0117 #define SD_CARD_UNK6        BIT(6)
0118 #define SD_CARD_WRITE_PROTECT   BIT(7)
0119 #define SD_CARD_CARD_REMOVED_3  BIT(8)
0120 #define SD_CARD_CARD_INSERTED_3 BIT(9)
0121 #define SD_CARD_PRESENT_3   BIT(10)
0122
0123 #define SD_BUF_CMD_INDEX_ERR    BIT(16)
0124 #define SD_BUF_CRC_ERR      BIT(17)
0125 #define SD_BUF_STOP_BIT_END_ERR BIT(18)
0126 #define SD_BUF_DATA_TIMEOUT BIT(19)
0127 #define SD_BUF_OVERFLOW     BIT(20)
0128 #define SD_BUF_UNDERFLOW    BIT(21)
0129 #define SD_BUF_CMD_TIMEOUT  BIT(22)
0130 #define SD_BUF_UNK7     BIT(23)
0131 #define SD_BUF_READ_ENABLE  BIT(24)
0132 #define SD_BUF_WRITE_ENABLE BIT(25)
0133 #define SD_BUF_ILLEGAL_FUNCTION BIT(29)
0134 #define SD_BUF_CMD_BUSY     BIT(30)
0135 #define SD_BUF_ILLEGAL_ACCESS   BIT(31)
0136
0137 #define SD_ERR0_RESP_CMD_ERR            BIT(0)
0138 #define SD_ERR0_RESP_NON_CMD12_END_BIT_ERR  BIT(2)
0139 #define SD_ERR0_RESP_CMD12_END_BIT_ERR      BIT(3)
0140 #define SD_ERR0_READ_DATA_END_BIT_ERR       BIT(4)
0141 #define SD_ERR0_WRITE_CRC_STATUS_END_BIT_ERR    BIT(5)
0142 #define SD_ERR0_RESP_NON_CMD12_CRC_ERR      BIT(8)
0143 #define SD_ERR0_RESP_CMD12_CRC_ERR      BIT(9)
0144 #define SD_ERR0_READ_DATA_CRC_ERR       BIT(10)
0145 #define SD_ERR0_WRITE_CMD_CRC_ERR       BIT(11)
0146
0147 #define SD_ERR1_NO_CMD_RESP     BIT(16)
0148 #define SD_ERR1_TIMEOUT_READ_DATA   BIT(20)
0149 #define SD_ERR1_TIMEOUT_CRS_STATUS  BIT(21)
0150 #define SD_ERR1_TIMEOUT_CRC_BUSY    BIT(22)
0151
0152 #define IRQ_DONT_CARE_BITS (SD_CARD_PRESENT_3 \
0153     | SD_CARD_WRITE_PROTECT \
0154     | SD_CARD_UNK6 \
0155     | SD_CARD_PRESENT_0 \
0156     | SD_BUF_UNK7 \
0157     | SD_BUF_CMD_BUSY)
0158
0159 struct toshsd_host {
0160     struct pci_dev *pdev;
0161     struct mmc_host *mmc;
0162
0163     spinlock_t lock;
0164
0165     struct mmc_request *mrq;/* Current request */
0166     struct mmc_command *cmd;/* Current command */
0167     struct mmc_data *data;  /* Current data request */
0168
0169     struct sg_mapping_iter sg_miter; /* for PIO */
0170
0171     void __iomem *ioaddr; /* mapped address */
0172 };