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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Toshiba PCI Secure Digital Host Controller Interface driver
0004  *
0005  *  Copyright (C) 2014 Ondrej Zary
0006  *  Copyright (C) 2007 Richard Betts, All Rights Reserved.
0007  *
0008  *  Based on asic3_mmc.c, copyright (c) 2005 SDG Systems, LLC and,
0009  *  sdhci.c, copyright (C) 2005-2006 Pierre Ossman
0010  */
0011 
0012 #include <linux/delay.h>
0013 #include <linux/device.h>
0014 #include <linux/module.h>
0015 #include <linux/pci.h>
0016 #include <linux/scatterlist.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/io.h>
0019 #include <linux/pm.h>
0020 #include <linux/pm_runtime.h>
0021 #include <linux/mmc/host.h>
0022 #include <linux/mmc/mmc.h>
0023 
0024 #include "toshsd.h"
0025 
0026 #define DRIVER_NAME "toshsd"
0027 
0028 static const struct pci_device_id pci_ids[] = {
0029     { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA, 0x0805) },
0030     { /* end: all zeroes */ },
0031 };
0032 
0033 MODULE_DEVICE_TABLE(pci, pci_ids);
0034 
0035 static void toshsd_init(struct toshsd_host *host)
0036 {
0037     /* enable clock */
0038     pci_write_config_byte(host->pdev, SD_PCICFG_CLKSTOP,
0039                     SD_PCICFG_CLKSTOP_ENABLE_ALL);
0040     pci_write_config_byte(host->pdev, SD_PCICFG_CARDDETECT, 2);
0041 
0042     /* reset */
0043     iowrite16(0, host->ioaddr + SD_SOFTWARERESET); /* assert */
0044     mdelay(2);
0045     iowrite16(1, host->ioaddr + SD_SOFTWARERESET); /* deassert */
0046     mdelay(2);
0047 
0048     /* Clear card registers */
0049     iowrite16(0, host->ioaddr + SD_CARDCLOCKCTRL);
0050     iowrite32(0, host->ioaddr + SD_CARDSTATUS);
0051     iowrite32(0, host->ioaddr + SD_ERRORSTATUS0);
0052     iowrite16(0, host->ioaddr + SD_STOPINTERNAL);
0053 
0054     /* SDIO clock? */
0055     iowrite16(0x100, host->ioaddr + SDIO_BASE + SDIO_CLOCKNWAITCTRL);
0056 
0057     /* enable LED */
0058     pci_write_config_byte(host->pdev, SD_PCICFG_SDLED_ENABLE1,
0059                     SD_PCICFG_LED_ENABLE1_START);
0060     pci_write_config_byte(host->pdev, SD_PCICFG_SDLED_ENABLE2,
0061                     SD_PCICFG_LED_ENABLE2_START);
0062 
0063     /* set interrupt masks */
0064     iowrite32(~(u32)(SD_CARD_RESP_END | SD_CARD_RW_END
0065             | SD_CARD_CARD_REMOVED_0 | SD_CARD_CARD_INSERTED_0
0066             | SD_BUF_READ_ENABLE | SD_BUF_WRITE_ENABLE
0067             | SD_BUF_CMD_TIMEOUT),
0068             host->ioaddr + SD_INTMASKCARD);
0069 
0070     iowrite16(0x1000, host->ioaddr + SD_TRANSACTIONCTRL);
0071 }
0072 
0073 /* Set MMC clock / power.
0074  * Note: This controller uses a simple divider scheme therefore it cannot run
0075  * SD/MMC cards at full speed (24/20MHz). HCLK (=33MHz PCI clock?) is too high
0076  * and the next slowest is 16MHz (div=2).
0077  */
0078 static void __toshsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
0079 {
0080     struct toshsd_host *host = mmc_priv(mmc);
0081 
0082     if (ios->clock) {
0083         u16 clk;
0084         int div = 1;
0085 
0086         while (ios->clock < HCLK / div)
0087             div *= 2;
0088 
0089         clk = div >> 2;
0090 
0091         if (div == 1) { /* disable the divider */
0092             pci_write_config_byte(host->pdev, SD_PCICFG_CLKMODE,
0093                           SD_PCICFG_CLKMODE_DIV_DISABLE);
0094             clk |= SD_CARDCLK_DIV_DISABLE;
0095         } else
0096             pci_write_config_byte(host->pdev, SD_PCICFG_CLKMODE, 0);
0097 
0098         clk |= SD_CARDCLK_ENABLE_CLOCK;
0099         iowrite16(clk, host->ioaddr + SD_CARDCLOCKCTRL);
0100 
0101         mdelay(10);
0102     } else
0103         iowrite16(0, host->ioaddr + SD_CARDCLOCKCTRL);
0104 
0105     switch (ios->power_mode) {
0106     case MMC_POWER_OFF:
0107         pci_write_config_byte(host->pdev, SD_PCICFG_POWER1,
0108                     SD_PCICFG_PWR1_OFF);
0109         mdelay(1);
0110         break;
0111     case MMC_POWER_UP:
0112         break;
0113     case MMC_POWER_ON:
0114         pci_write_config_byte(host->pdev, SD_PCICFG_POWER1,
0115                     SD_PCICFG_PWR1_33V);
0116         pci_write_config_byte(host->pdev, SD_PCICFG_POWER2,
0117                     SD_PCICFG_PWR2_AUTO);
0118         mdelay(20);
0119         break;
0120     }
0121 
0122     switch (ios->bus_width) {
0123     case MMC_BUS_WIDTH_1:
0124         iowrite16(SD_CARDOPT_REQUIRED | SD_CARDOPT_DATA_RESP_TIMEOUT(14)
0125                 | SD_CARDOPT_C2_MODULE_ABSENT
0126                 | SD_CARDOPT_DATA_XFR_WIDTH_1,
0127                 host->ioaddr + SD_CARDOPTIONSETUP);
0128         break;
0129     case MMC_BUS_WIDTH_4:
0130         iowrite16(SD_CARDOPT_REQUIRED | SD_CARDOPT_DATA_RESP_TIMEOUT(14)
0131                 | SD_CARDOPT_C2_MODULE_ABSENT
0132                 | SD_CARDOPT_DATA_XFR_WIDTH_4,
0133                 host->ioaddr + SD_CARDOPTIONSETUP);
0134         break;
0135     }
0136 }
0137 
0138 static void toshsd_set_led(struct toshsd_host *host, unsigned char state)
0139 {
0140     iowrite16(state, host->ioaddr + SDIO_BASE + SDIO_LEDCTRL);
0141 }
0142 
0143 static void toshsd_finish_request(struct toshsd_host *host)
0144 {
0145     struct mmc_request *mrq = host->mrq;
0146 
0147     /* Write something to end the command */
0148     host->mrq = NULL;
0149     host->cmd = NULL;
0150     host->data = NULL;
0151 
0152     toshsd_set_led(host, 0);
0153     mmc_request_done(host->mmc, mrq);
0154 }
0155 
0156 static irqreturn_t toshsd_thread_irq(int irq, void *dev_id)
0157 {
0158     struct toshsd_host *host = dev_id;
0159     struct mmc_data *data = host->data;
0160     struct sg_mapping_iter *sg_miter = &host->sg_miter;
0161     unsigned short *buf;
0162     int count;
0163     unsigned long flags;
0164 
0165     if (!data) {
0166         dev_warn(&host->pdev->dev, "Spurious Data IRQ\n");
0167         if (host->cmd) {
0168             host->cmd->error = -EIO;
0169             toshsd_finish_request(host);
0170         }
0171         return IRQ_NONE;
0172     }
0173     spin_lock_irqsave(&host->lock, flags);
0174 
0175     if (!sg_miter_next(sg_miter))
0176         goto done;
0177 
0178     buf = sg_miter->addr;
0179 
0180     /* Ensure we dont read more than one block. The chip will interrupt us
0181      * When the next block is available.
0182      */
0183     count = sg_miter->length;
0184     if (count > data->blksz)
0185         count = data->blksz;
0186 
0187     dev_dbg(&host->pdev->dev, "count: %08x, flags %08x\n", count,
0188         data->flags);
0189 
0190     /* Transfer the data */
0191     if (data->flags & MMC_DATA_READ)
0192         ioread32_rep(host->ioaddr + SD_DATAPORT, buf, count >> 2);
0193     else
0194         iowrite32_rep(host->ioaddr + SD_DATAPORT, buf, count >> 2);
0195 
0196     sg_miter->consumed = count;
0197     sg_miter_stop(sg_miter);
0198 
0199 done:
0200     spin_unlock_irqrestore(&host->lock, flags);
0201 
0202     return IRQ_HANDLED;
0203 }
0204 
0205 static void toshsd_cmd_irq(struct toshsd_host *host)
0206 {
0207     struct mmc_command *cmd = host->cmd;
0208     u8 *buf;
0209     u16 data;
0210 
0211     if (!host->cmd) {
0212         dev_warn(&host->pdev->dev, "Spurious CMD irq\n");
0213         return;
0214     }
0215     buf = (u8 *)cmd->resp;
0216     host->cmd = NULL;
0217 
0218     if (cmd->flags & MMC_RSP_PRESENT && cmd->flags & MMC_RSP_136) {
0219         /* R2 */
0220         buf[12] = 0xff;
0221         data = ioread16(host->ioaddr + SD_RESPONSE0);
0222         buf[13] = data & 0xff;
0223         buf[14] = data >> 8;
0224         data = ioread16(host->ioaddr + SD_RESPONSE1);
0225         buf[15] = data & 0xff;
0226         buf[8] = data >> 8;
0227         data = ioread16(host->ioaddr + SD_RESPONSE2);
0228         buf[9] = data & 0xff;
0229         buf[10] = data >> 8;
0230         data = ioread16(host->ioaddr + SD_RESPONSE3);
0231         buf[11] = data & 0xff;
0232         buf[4] = data >> 8;
0233         data = ioread16(host->ioaddr + SD_RESPONSE4);
0234         buf[5] = data & 0xff;
0235         buf[6] = data >> 8;
0236         data = ioread16(host->ioaddr + SD_RESPONSE5);
0237         buf[7] = data & 0xff;
0238         buf[0] = data >> 8;
0239         data = ioread16(host->ioaddr + SD_RESPONSE6);
0240         buf[1] = data & 0xff;
0241         buf[2] = data >> 8;
0242         data = ioread16(host->ioaddr + SD_RESPONSE7);
0243         buf[3] = data & 0xff;
0244     } else if (cmd->flags & MMC_RSP_PRESENT) {
0245         /* R1, R1B, R3, R6, R7 */
0246         data = ioread16(host->ioaddr + SD_RESPONSE0);
0247         buf[0] = data & 0xff;
0248         buf[1] = data >> 8;
0249         data = ioread16(host->ioaddr + SD_RESPONSE1);
0250         buf[2] = data & 0xff;
0251         buf[3] = data >> 8;
0252     }
0253 
0254     dev_dbg(&host->pdev->dev, "Command IRQ complete %d %d %x\n",
0255         cmd->opcode, cmd->error, cmd->flags);
0256 
0257     /* If there is data to handle we will
0258      * finish the request in the mmc_data_end_irq handler.*/
0259     if (host->data)
0260         return;
0261 
0262     toshsd_finish_request(host);
0263 }
0264 
0265 static void toshsd_data_end_irq(struct toshsd_host *host)
0266 {
0267     struct mmc_data *data = host->data;
0268 
0269     host->data = NULL;
0270 
0271     if (!data) {
0272         dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
0273         return;
0274     }
0275 
0276     if (data->error == 0)
0277         data->bytes_xfered = data->blocks * data->blksz;
0278     else
0279         data->bytes_xfered = 0;
0280 
0281     dev_dbg(&host->pdev->dev, "Completed data request xfr=%d\n",
0282         data->bytes_xfered);
0283 
0284     iowrite16(0, host->ioaddr + SD_STOPINTERNAL);
0285 
0286     toshsd_finish_request(host);
0287 }
0288 
0289 static irqreturn_t toshsd_irq(int irq, void *dev_id)
0290 {
0291     struct toshsd_host *host = dev_id;
0292     u32 int_reg, int_mask, int_status, detail;
0293     int error = 0, ret = IRQ_HANDLED;
0294 
0295     spin_lock(&host->lock);
0296     int_status = ioread32(host->ioaddr + SD_CARDSTATUS);
0297     int_mask = ioread32(host->ioaddr + SD_INTMASKCARD);
0298     int_reg = int_status & ~int_mask & ~IRQ_DONT_CARE_BITS;
0299 
0300     dev_dbg(&host->pdev->dev, "IRQ status:%x mask:%x\n",
0301         int_status, int_mask);
0302 
0303     /* nothing to do: it's not our IRQ */
0304     if (!int_reg) {
0305         ret = IRQ_NONE;
0306         goto irq_end;
0307     }
0308 
0309     if (int_reg & SD_BUF_CMD_TIMEOUT) {
0310         error = -ETIMEDOUT;
0311         dev_dbg(&host->pdev->dev, "Timeout\n");
0312     } else if (int_reg & SD_BUF_CRC_ERR) {
0313         error = -EILSEQ;
0314         dev_err(&host->pdev->dev, "BadCRC\n");
0315     } else if (int_reg & (SD_BUF_ILLEGAL_ACCESS
0316                 | SD_BUF_CMD_INDEX_ERR
0317                 | SD_BUF_STOP_BIT_END_ERR
0318                 | SD_BUF_OVERFLOW
0319                 | SD_BUF_UNDERFLOW
0320                 | SD_BUF_DATA_TIMEOUT)) {
0321         dev_err(&host->pdev->dev, "Buffer status error: { %s%s%s%s%s%s}\n",
0322             int_reg & SD_BUF_ILLEGAL_ACCESS ? "ILLEGAL_ACC " : "",
0323             int_reg & SD_BUF_CMD_INDEX_ERR ? "CMD_INDEX " : "",
0324             int_reg & SD_BUF_STOP_BIT_END_ERR ? "STOPBIT_END " : "",
0325             int_reg & SD_BUF_OVERFLOW ? "OVERFLOW " : "",
0326             int_reg & SD_BUF_UNDERFLOW ? "UNDERFLOW " : "",
0327             int_reg & SD_BUF_DATA_TIMEOUT ? "DATA_TIMEOUT " : "");
0328 
0329         detail = ioread32(host->ioaddr + SD_ERRORSTATUS0);
0330         dev_err(&host->pdev->dev, "detail error status { %s%s%s%s%s%s%s%s%s%s%s%s%s}\n",
0331             detail & SD_ERR0_RESP_CMD_ERR ? "RESP_CMD " : "",
0332             detail & SD_ERR0_RESP_NON_CMD12_END_BIT_ERR ? "RESP_END_BIT " : "",
0333             detail & SD_ERR0_RESP_CMD12_END_BIT_ERR ? "RESP_END_BIT " : "",
0334             detail & SD_ERR0_READ_DATA_END_BIT_ERR ? "READ_DATA_END_BIT " : "",
0335             detail & SD_ERR0_WRITE_CRC_STATUS_END_BIT_ERR ? "WRITE_CMD_END_BIT " : "",
0336             detail & SD_ERR0_RESP_NON_CMD12_CRC_ERR ? "RESP_CRC " : "",
0337             detail & SD_ERR0_RESP_CMD12_CRC_ERR ? "RESP_CRC " : "",
0338             detail & SD_ERR0_READ_DATA_CRC_ERR ? "READ_DATA_CRC " : "",
0339             detail & SD_ERR0_WRITE_CMD_CRC_ERR ? "WRITE_CMD_CRC " : "",
0340             detail & SD_ERR1_NO_CMD_RESP ? "NO_CMD_RESP " : "",
0341             detail & SD_ERR1_TIMEOUT_READ_DATA ? "READ_DATA_TIMEOUT " : "",
0342             detail & SD_ERR1_TIMEOUT_CRS_STATUS ? "CRS_STATUS_TIMEOUT " : "",
0343             detail & SD_ERR1_TIMEOUT_CRC_BUSY ? "CRC_BUSY_TIMEOUT " : "");
0344         error = -EIO;
0345     }
0346 
0347     if (error) {
0348         if (host->cmd)
0349             host->cmd->error = error;
0350 
0351         if (error == -ETIMEDOUT) {
0352             iowrite32(int_status &
0353                   ~(SD_BUF_CMD_TIMEOUT | SD_CARD_RESP_END),
0354                   host->ioaddr + SD_CARDSTATUS);
0355         } else {
0356             toshsd_init(host);
0357             __toshsd_set_ios(host->mmc, &host->mmc->ios);
0358             goto irq_end;
0359         }
0360     }
0361 
0362     /* Card insert/remove. The mmc controlling code is stateless. */
0363     if (int_reg & (SD_CARD_CARD_INSERTED_0 | SD_CARD_CARD_REMOVED_0)) {
0364         iowrite32(int_status &
0365               ~(SD_CARD_CARD_REMOVED_0 | SD_CARD_CARD_INSERTED_0),
0366               host->ioaddr + SD_CARDSTATUS);
0367 
0368         if (int_reg & SD_CARD_CARD_INSERTED_0)
0369             toshsd_init(host);
0370 
0371         mmc_detect_change(host->mmc, 1);
0372     }
0373 
0374     /* Data transfer */
0375     if (int_reg & (SD_BUF_READ_ENABLE | SD_BUF_WRITE_ENABLE)) {
0376         iowrite32(int_status &
0377               ~(SD_BUF_WRITE_ENABLE | SD_BUF_READ_ENABLE),
0378               host->ioaddr + SD_CARDSTATUS);
0379 
0380         ret = IRQ_WAKE_THREAD;
0381         goto irq_end;
0382     }
0383 
0384     /* Command completion */
0385     if (int_reg & SD_CARD_RESP_END) {
0386         iowrite32(int_status & ~(SD_CARD_RESP_END),
0387               host->ioaddr + SD_CARDSTATUS);
0388         toshsd_cmd_irq(host);
0389     }
0390 
0391     /* Data transfer completion */
0392     if (int_reg & SD_CARD_RW_END) {
0393         iowrite32(int_status & ~(SD_CARD_RW_END),
0394               host->ioaddr + SD_CARDSTATUS);
0395         toshsd_data_end_irq(host);
0396     }
0397 irq_end:
0398     spin_unlock(&host->lock);
0399     return ret;
0400 }
0401 
0402 static void toshsd_start_cmd(struct toshsd_host *host, struct mmc_command *cmd)
0403 {
0404     struct mmc_data *data = host->data;
0405     int c = cmd->opcode;
0406 
0407     dev_dbg(&host->pdev->dev, "Command opcode: %d\n", cmd->opcode);
0408 
0409     if (cmd->opcode == MMC_STOP_TRANSMISSION) {
0410         iowrite16(SD_STOPINT_ISSUE_CMD12,
0411               host->ioaddr + SD_STOPINTERNAL);
0412 
0413         cmd->resp[0] = cmd->opcode;
0414         cmd->resp[1] = 0;
0415         cmd->resp[2] = 0;
0416         cmd->resp[3] = 0;
0417 
0418         toshsd_finish_request(host);
0419         return;
0420     }
0421 
0422     switch (mmc_resp_type(cmd)) {
0423     case MMC_RSP_NONE:
0424         c |= SD_CMD_RESP_TYPE_NONE;
0425         break;
0426 
0427     case MMC_RSP_R1:
0428         c |= SD_CMD_RESP_TYPE_EXT_R1;
0429         break;
0430     case MMC_RSP_R1B:
0431         c |= SD_CMD_RESP_TYPE_EXT_R1B;
0432         break;
0433     case MMC_RSP_R2:
0434         c |= SD_CMD_RESP_TYPE_EXT_R2;
0435         break;
0436     case MMC_RSP_R3:
0437         c |= SD_CMD_RESP_TYPE_EXT_R3;
0438         break;
0439 
0440     default:
0441         dev_err(&host->pdev->dev, "Unknown response type %d\n",
0442             mmc_resp_type(cmd));
0443         break;
0444     }
0445 
0446     host->cmd = cmd;
0447 
0448     if (cmd->opcode == MMC_APP_CMD)
0449         c |= SD_CMD_TYPE_ACMD;
0450 
0451     if (cmd->opcode == MMC_GO_IDLE_STATE)
0452         c |= (3 << 8);  /* removed from ipaq-asic3.h for some reason */
0453 
0454     if (data) {
0455         c |= SD_CMD_DATA_PRESENT;
0456 
0457         if (data->blocks > 1) {
0458             iowrite16(SD_STOPINT_AUTO_ISSUE_CMD12,
0459                   host->ioaddr + SD_STOPINTERNAL);
0460             c |= SD_CMD_MULTI_BLOCK;
0461         }
0462 
0463         if (data->flags & MMC_DATA_READ)
0464             c |= SD_CMD_TRANSFER_READ;
0465 
0466         /* MMC_DATA_WRITE does not require a bit to be set */
0467     }
0468 
0469     /* Send the command */
0470     iowrite32(cmd->arg, host->ioaddr + SD_ARG0);
0471     iowrite16(c, host->ioaddr + SD_CMD);
0472 }
0473 
0474 static void toshsd_start_data(struct toshsd_host *host, struct mmc_data *data)
0475 {
0476     unsigned int flags = SG_MITER_ATOMIC;
0477 
0478     dev_dbg(&host->pdev->dev, "setup data transfer: blocksize %08x  nr_blocks %d, offset: %08x\n",
0479         data->blksz, data->blocks, data->sg->offset);
0480 
0481     host->data = data;
0482 
0483     if (data->flags & MMC_DATA_READ)
0484         flags |= SG_MITER_TO_SG;
0485     else
0486         flags |= SG_MITER_FROM_SG;
0487 
0488     sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
0489 
0490     /* Set transfer length and blocksize */
0491     iowrite16(data->blocks, host->ioaddr + SD_BLOCKCOUNT);
0492     iowrite16(data->blksz, host->ioaddr + SD_CARDXFERDATALEN);
0493 }
0494 
0495 /* Process requests from the MMC layer */
0496 static void toshsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
0497 {
0498     struct toshsd_host *host = mmc_priv(mmc);
0499     unsigned long flags;
0500 
0501     /* abort if card not present */
0502     if (!(ioread16(host->ioaddr + SD_CARDSTATUS) & SD_CARD_PRESENT_0)) {
0503         mrq->cmd->error = -ENOMEDIUM;
0504         mmc_request_done(mmc, mrq);
0505         return;
0506     }
0507 
0508     spin_lock_irqsave(&host->lock, flags);
0509 
0510     WARN_ON(host->mrq != NULL);
0511 
0512     host->mrq = mrq;
0513 
0514     if (mrq->data)
0515         toshsd_start_data(host, mrq->data);
0516 
0517     toshsd_set_led(host, 1);
0518 
0519     toshsd_start_cmd(host, mrq->cmd);
0520 
0521     spin_unlock_irqrestore(&host->lock, flags);
0522 }
0523 
0524 static void toshsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
0525 {
0526     struct toshsd_host *host = mmc_priv(mmc);
0527     unsigned long flags;
0528 
0529     spin_lock_irqsave(&host->lock, flags);
0530     __toshsd_set_ios(mmc, ios);
0531     spin_unlock_irqrestore(&host->lock, flags);
0532 }
0533 
0534 static int toshsd_get_ro(struct mmc_host *mmc)
0535 {
0536     struct toshsd_host *host = mmc_priv(mmc);
0537 
0538     /* active low */
0539     return !(ioread16(host->ioaddr + SD_CARDSTATUS) & SD_CARD_WRITE_PROTECT);
0540 }
0541 
0542 static int toshsd_get_cd(struct mmc_host *mmc)
0543 {
0544     struct toshsd_host *host = mmc_priv(mmc);
0545 
0546     return !!(ioread16(host->ioaddr + SD_CARDSTATUS) & SD_CARD_PRESENT_0);
0547 }
0548 
0549 static const struct mmc_host_ops toshsd_ops = {
0550     .request = toshsd_request,
0551     .set_ios = toshsd_set_ios,
0552     .get_ro = toshsd_get_ro,
0553     .get_cd = toshsd_get_cd,
0554 };
0555 
0556 
0557 static void toshsd_powerdown(struct toshsd_host *host)
0558 {
0559     /* mask all interrupts */
0560     iowrite32(0xffffffff, host->ioaddr + SD_INTMASKCARD);
0561     /* disable card clock */
0562     iowrite16(0x000, host->ioaddr + SDIO_BASE + SDIO_CLOCKNWAITCTRL);
0563     iowrite16(0, host->ioaddr + SD_CARDCLOCKCTRL);
0564     /* power down card */
0565     pci_write_config_byte(host->pdev, SD_PCICFG_POWER1, SD_PCICFG_PWR1_OFF);
0566     /* disable clock */
0567     pci_write_config_byte(host->pdev, SD_PCICFG_CLKSTOP, 0);
0568 }
0569 
0570 #ifdef CONFIG_PM_SLEEP
0571 static int toshsd_pm_suspend(struct device *dev)
0572 {
0573     struct pci_dev *pdev = to_pci_dev(dev);
0574     struct toshsd_host *host = pci_get_drvdata(pdev);
0575 
0576     toshsd_powerdown(host);
0577 
0578     pci_save_state(pdev);
0579     pci_enable_wake(pdev, PCI_D3hot, 0);
0580     pci_disable_device(pdev);
0581     pci_set_power_state(pdev, PCI_D3hot);
0582 
0583     return 0;
0584 }
0585 
0586 static int toshsd_pm_resume(struct device *dev)
0587 {
0588     struct pci_dev *pdev = to_pci_dev(dev);
0589     struct toshsd_host *host = pci_get_drvdata(pdev);
0590     int ret;
0591 
0592     pci_set_power_state(pdev, PCI_D0);
0593     pci_restore_state(pdev);
0594     ret = pci_enable_device(pdev);
0595     if (ret)
0596         return ret;
0597 
0598     toshsd_init(host);
0599 
0600     return 0;
0601 }
0602 #endif /* CONFIG_PM_SLEEP */
0603 
0604 static int toshsd_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
0605 {
0606     int ret;
0607     struct toshsd_host *host;
0608     struct mmc_host *mmc;
0609     resource_size_t base;
0610 
0611     ret = pci_enable_device(pdev);
0612     if (ret)
0613         return ret;
0614 
0615     mmc = mmc_alloc_host(sizeof(struct toshsd_host), &pdev->dev);
0616     if (!mmc) {
0617         ret = -ENOMEM;
0618         goto err;
0619     }
0620 
0621     host = mmc_priv(mmc);
0622     host->mmc = mmc;
0623 
0624     host->pdev = pdev;
0625     pci_set_drvdata(pdev, host);
0626 
0627     ret = pci_request_regions(pdev, DRIVER_NAME);
0628     if (ret)
0629         goto free;
0630 
0631     host->ioaddr = pci_iomap(pdev, 0, 0);
0632     if (!host->ioaddr) {
0633         ret = -ENOMEM;
0634         goto release;
0635     }
0636 
0637     /* Set MMC host parameters */
0638     mmc->ops = &toshsd_ops;
0639     mmc->caps = MMC_CAP_4_BIT_DATA;
0640     mmc->ocr_avail = MMC_VDD_32_33;
0641 
0642     mmc->f_min = HCLK / 512;
0643     mmc->f_max = HCLK;
0644 
0645     spin_lock_init(&host->lock);
0646 
0647     toshsd_init(host);
0648 
0649     ret = request_threaded_irq(pdev->irq, toshsd_irq, toshsd_thread_irq,
0650                    IRQF_SHARED, DRIVER_NAME, host);
0651     if (ret)
0652         goto unmap;
0653 
0654     mmc_add_host(mmc);
0655 
0656     base = pci_resource_start(pdev, 0);
0657     dev_dbg(&pdev->dev, "MMIO %pa, IRQ %d\n", &base, pdev->irq);
0658 
0659     pm_suspend_ignore_children(&pdev->dev, 1);
0660 
0661     return 0;
0662 
0663 unmap:
0664     pci_iounmap(pdev, host->ioaddr);
0665 release:
0666     pci_release_regions(pdev);
0667 free:
0668     mmc_free_host(mmc);
0669     pci_set_drvdata(pdev, NULL);
0670 err:
0671     pci_disable_device(pdev);
0672     return ret;
0673 }
0674 
0675 static void toshsd_remove(struct pci_dev *pdev)
0676 {
0677     struct toshsd_host *host = pci_get_drvdata(pdev);
0678 
0679     mmc_remove_host(host->mmc);
0680     toshsd_powerdown(host);
0681     free_irq(pdev->irq, host);
0682     pci_iounmap(pdev, host->ioaddr);
0683     pci_release_regions(pdev);
0684     mmc_free_host(host->mmc);
0685     pci_set_drvdata(pdev, NULL);
0686     pci_disable_device(pdev);
0687 }
0688 
0689 static const struct dev_pm_ops toshsd_pm_ops = {
0690     SET_SYSTEM_SLEEP_PM_OPS(toshsd_pm_suspend, toshsd_pm_resume)
0691 };
0692 
0693 static struct pci_driver toshsd_driver = {
0694     .name = DRIVER_NAME,
0695     .id_table = pci_ids,
0696     .probe = toshsd_probe,
0697     .remove = toshsd_remove,
0698     .driver.pm = &toshsd_pm_ops,
0699 };
0700 
0701 module_pci_driver(toshsd_driver);
0702 
0703 MODULE_AUTHOR("Ondrej Zary, Richard Betts");
0704 MODULE_DESCRIPTION("Toshiba PCI Secure Digital Host Controller Interface driver");
0705 MODULE_LICENSE("GPL");
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