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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for sunxi SD/MMC host controllers
0004  * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
0005  * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
0006  * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
0007  * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
0008  * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
0009  * (C) Copyright 2017 Sootech SA
0010  */
0011 
0012 #include <linux/clk.h>
0013 #include <linux/clk/sunxi-ng.h>
0014 #include <linux/delay.h>
0015 #include <linux/device.h>
0016 #include <linux/dma-mapping.h>
0017 #include <linux/err.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/io.h>
0020 #include <linux/kernel.h>
0021 #include <linux/mmc/card.h>
0022 #include <linux/mmc/core.h>
0023 #include <linux/mmc/host.h>
0024 #include <linux/mmc/mmc.h>
0025 #include <linux/mmc/sd.h>
0026 #include <linux/mmc/sdio.h>
0027 #include <linux/mmc/slot-gpio.h>
0028 #include <linux/module.h>
0029 #include <linux/mod_devicetable.h>
0030 #include <linux/of_address.h>
0031 #include <linux/of_platform.h>
0032 #include <linux/platform_device.h>
0033 #include <linux/pm_runtime.h>
0034 #include <linux/regulator/consumer.h>
0035 #include <linux/reset.h>
0036 #include <linux/scatterlist.h>
0037 #include <linux/slab.h>
0038 #include <linux/spinlock.h>
0039 
0040 /* register offset definitions */
0041 #define SDXC_REG_GCTRL  (0x00) /* SMC Global Control Register */
0042 #define SDXC_REG_CLKCR  (0x04) /* SMC Clock Control Register */
0043 #define SDXC_REG_TMOUT  (0x08) /* SMC Time Out Register */
0044 #define SDXC_REG_WIDTH  (0x0C) /* SMC Bus Width Register */
0045 #define SDXC_REG_BLKSZ  (0x10) /* SMC Block Size Register */
0046 #define SDXC_REG_BCNTR  (0x14) /* SMC Byte Count Register */
0047 #define SDXC_REG_CMDR   (0x18) /* SMC Command Register */
0048 #define SDXC_REG_CARG   (0x1C) /* SMC Argument Register */
0049 #define SDXC_REG_RESP0  (0x20) /* SMC Response Register 0 */
0050 #define SDXC_REG_RESP1  (0x24) /* SMC Response Register 1 */
0051 #define SDXC_REG_RESP2  (0x28) /* SMC Response Register 2 */
0052 #define SDXC_REG_RESP3  (0x2C) /* SMC Response Register 3 */
0053 #define SDXC_REG_IMASK  (0x30) /* SMC Interrupt Mask Register */
0054 #define SDXC_REG_MISTA  (0x34) /* SMC Masked Interrupt Status Register */
0055 #define SDXC_REG_RINTR  (0x38) /* SMC Raw Interrupt Status Register */
0056 #define SDXC_REG_STAS   (0x3C) /* SMC Status Register */
0057 #define SDXC_REG_FTRGL  (0x40) /* SMC FIFO Threshold Watermark Registe */
0058 #define SDXC_REG_FUNS   (0x44) /* SMC Function Select Register */
0059 #define SDXC_REG_CBCR   (0x48) /* SMC CIU Byte Count Register */
0060 #define SDXC_REG_BBCR   (0x4C) /* SMC BIU Byte Count Register */
0061 #define SDXC_REG_DBGC   (0x50) /* SMC Debug Enable Register */
0062 #define SDXC_REG_HWRST  (0x78) /* SMC Card Hardware Reset for Register */
0063 #define SDXC_REG_DMAC   (0x80) /* SMC IDMAC Control Register */
0064 #define SDXC_REG_DLBA   (0x84) /* SMC IDMAC Descriptor List Base Addre */
0065 #define SDXC_REG_IDST   (0x88) /* SMC IDMAC Status Register */
0066 #define SDXC_REG_IDIE   (0x8C) /* SMC IDMAC Interrupt Enable Register */
0067 #define SDXC_REG_CHDA   (0x90)
0068 #define SDXC_REG_CBDA   (0x94)
0069 
0070 /* New registers introduced in A64 */
0071 #define SDXC_REG_A12A       0x058 /* SMC Auto Command 12 Register */
0072 #define SDXC_REG_SD_NTSR    0x05C /* SMC New Timing Set Register */
0073 #define SDXC_REG_DRV_DL     0x140 /* Drive Delay Control Register */
0074 #define SDXC_REG_SAMP_DL_REG    0x144 /* SMC sample delay control */
0075 #define SDXC_REG_DS_DL_REG  0x148 /* SMC data strobe delay control */
0076 
0077 #define mmc_readl(host, reg) \
0078     readl((host)->reg_base + SDXC_##reg)
0079 #define mmc_writel(host, reg, value) \
0080     writel((value), (host)->reg_base + SDXC_##reg)
0081 
0082 /* global control register bits */
0083 #define SDXC_SOFT_RESET         BIT(0)
0084 #define SDXC_FIFO_RESET         BIT(1)
0085 #define SDXC_DMA_RESET          BIT(2)
0086 #define SDXC_INTERRUPT_ENABLE_BIT   BIT(4)
0087 #define SDXC_DMA_ENABLE_BIT     BIT(5)
0088 #define SDXC_DEBOUNCE_ENABLE_BIT    BIT(8)
0089 #define SDXC_POSEDGE_LATCH_DATA     BIT(9)
0090 #define SDXC_DDR_MODE           BIT(10)
0091 #define SDXC_MEMORY_ACCESS_DONE     BIT(29)
0092 #define SDXC_ACCESS_DONE_DIRECT     BIT(30)
0093 #define SDXC_ACCESS_BY_AHB      BIT(31)
0094 #define SDXC_ACCESS_BY_DMA      (0 << 31)
0095 #define SDXC_HARDWARE_RESET \
0096     (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
0097 
0098 /* clock control bits */
0099 #define SDXC_MASK_DATA0         BIT(31)
0100 #define SDXC_CARD_CLOCK_ON      BIT(16)
0101 #define SDXC_LOW_POWER_ON       BIT(17)
0102 
0103 /* bus width */
0104 #define SDXC_WIDTH1         0
0105 #define SDXC_WIDTH4         1
0106 #define SDXC_WIDTH8         2
0107 
0108 /* smc command bits */
0109 #define SDXC_RESP_EXPIRE        BIT(6)
0110 #define SDXC_LONG_RESPONSE      BIT(7)
0111 #define SDXC_CHECK_RESPONSE_CRC     BIT(8)
0112 #define SDXC_DATA_EXPIRE        BIT(9)
0113 #define SDXC_WRITE          BIT(10)
0114 #define SDXC_SEQUENCE_MODE      BIT(11)
0115 #define SDXC_SEND_AUTO_STOP     BIT(12)
0116 #define SDXC_WAIT_PRE_OVER      BIT(13)
0117 #define SDXC_STOP_ABORT_CMD     BIT(14)
0118 #define SDXC_SEND_INIT_SEQUENCE     BIT(15)
0119 #define SDXC_UPCLK_ONLY         BIT(21)
0120 #define SDXC_READ_CEATA_DEV     BIT(22)
0121 #define SDXC_CCS_EXPIRE         BIT(23)
0122 #define SDXC_ENABLE_BIT_BOOT        BIT(24)
0123 #define SDXC_ALT_BOOT_OPTIONS       BIT(25)
0124 #define SDXC_BOOT_ACK_EXPIRE        BIT(26)
0125 #define SDXC_BOOT_ABORT         BIT(27)
0126 #define SDXC_VOLTAGE_SWITCH         BIT(28)
0127 #define SDXC_USE_HOLD_REGISTER          BIT(29)
0128 #define SDXC_START          BIT(31)
0129 
0130 /* interrupt bits */
0131 #define SDXC_RESP_ERROR         BIT(1)
0132 #define SDXC_COMMAND_DONE       BIT(2)
0133 #define SDXC_DATA_OVER          BIT(3)
0134 #define SDXC_TX_DATA_REQUEST        BIT(4)
0135 #define SDXC_RX_DATA_REQUEST        BIT(5)
0136 #define SDXC_RESP_CRC_ERROR     BIT(6)
0137 #define SDXC_DATA_CRC_ERROR     BIT(7)
0138 #define SDXC_RESP_TIMEOUT       BIT(8)
0139 #define SDXC_DATA_TIMEOUT       BIT(9)
0140 #define SDXC_VOLTAGE_CHANGE_DONE    BIT(10)
0141 #define SDXC_FIFO_RUN_ERROR     BIT(11)
0142 #define SDXC_HARD_WARE_LOCKED       BIT(12)
0143 #define SDXC_START_BIT_ERROR        BIT(13)
0144 #define SDXC_AUTO_COMMAND_DONE      BIT(14)
0145 #define SDXC_END_BIT_ERROR      BIT(15)
0146 #define SDXC_SDIO_INTERRUPT     BIT(16)
0147 #define SDXC_CARD_INSERT        BIT(30)
0148 #define SDXC_CARD_REMOVE        BIT(31)
0149 #define SDXC_INTERRUPT_ERROR_BIT \
0150     (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
0151      SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
0152      SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
0153 #define SDXC_INTERRUPT_DONE_BIT \
0154     (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
0155      SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
0156 
0157 /* status */
0158 #define SDXC_RXWL_FLAG          BIT(0)
0159 #define SDXC_TXWL_FLAG          BIT(1)
0160 #define SDXC_FIFO_EMPTY         BIT(2)
0161 #define SDXC_FIFO_FULL          BIT(3)
0162 #define SDXC_CARD_PRESENT       BIT(8)
0163 #define SDXC_CARD_DATA_BUSY     BIT(9)
0164 #define SDXC_DATA_FSM_BUSY      BIT(10)
0165 #define SDXC_DMA_REQUEST        BIT(31)
0166 #define SDXC_FIFO_SIZE          16
0167 
0168 /* Function select */
0169 #define SDXC_CEATA_ON           (0xceaa << 16)
0170 #define SDXC_SEND_IRQ_RESPONSE      BIT(0)
0171 #define SDXC_SDIO_READ_WAIT     BIT(1)
0172 #define SDXC_ABORT_READ_DATA        BIT(2)
0173 #define SDXC_SEND_CCSD          BIT(8)
0174 #define SDXC_SEND_AUTO_STOPCCSD     BIT(9)
0175 #define SDXC_CEATA_DEV_IRQ_ENABLE   BIT(10)
0176 
0177 /* IDMA controller bus mod bit field */
0178 #define SDXC_IDMAC_SOFT_RESET       BIT(0)
0179 #define SDXC_IDMAC_FIX_BURST        BIT(1)
0180 #define SDXC_IDMAC_IDMA_ON      BIT(7)
0181 #define SDXC_IDMAC_REFETCH_DES      BIT(31)
0182 
0183 /* IDMA status bit field */
0184 #define SDXC_IDMAC_TRANSMIT_INTERRUPT       BIT(0)
0185 #define SDXC_IDMAC_RECEIVE_INTERRUPT        BIT(1)
0186 #define SDXC_IDMAC_FATAL_BUS_ERROR      BIT(2)
0187 #define SDXC_IDMAC_DESTINATION_INVALID      BIT(4)
0188 #define SDXC_IDMAC_CARD_ERROR_SUM       BIT(5)
0189 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM     BIT(8)
0190 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM   BIT(9)
0191 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT     BIT(10)
0192 #define SDXC_IDMAC_IDLE             (0 << 13)
0193 #define SDXC_IDMAC_SUSPEND          (1 << 13)
0194 #define SDXC_IDMAC_DESC_READ            (2 << 13)
0195 #define SDXC_IDMAC_DESC_CHECK           (3 << 13)
0196 #define SDXC_IDMAC_READ_REQUEST_WAIT        (4 << 13)
0197 #define SDXC_IDMAC_WRITE_REQUEST_WAIT       (5 << 13)
0198 #define SDXC_IDMAC_READ             (6 << 13)
0199 #define SDXC_IDMAC_WRITE            (7 << 13)
0200 #define SDXC_IDMAC_DESC_CLOSE           (8 << 13)
0201 
0202 /*
0203 * If the idma-des-size-bits of property is ie 13, bufsize bits are:
0204 *  Bits  0-12: buf1 size
0205 *  Bits 13-25: buf2 size
0206 *  Bits 26-31: not used
0207 * Since we only ever set buf1 size, we can simply store it directly.
0208 */
0209 #define SDXC_IDMAC_DES0_DIC BIT(1)  /* disable interrupt on completion */
0210 #define SDXC_IDMAC_DES0_LD  BIT(2)  /* last descriptor */
0211 #define SDXC_IDMAC_DES0_FD  BIT(3)  /* first descriptor */
0212 #define SDXC_IDMAC_DES0_CH  BIT(4)  /* chain mode */
0213 #define SDXC_IDMAC_DES0_ER  BIT(5)  /* end of ring */
0214 #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
0215 #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
0216 
0217 #define SDXC_CLK_400K       0
0218 #define SDXC_CLK_25M        1
0219 #define SDXC_CLK_50M        2
0220 #define SDXC_CLK_50M_DDR    3
0221 #define SDXC_CLK_50M_DDR_8BIT   4
0222 
0223 #define SDXC_2X_TIMING_MODE BIT(31)
0224 
0225 #define SDXC_CAL_START      BIT(15)
0226 #define SDXC_CAL_DONE       BIT(14)
0227 #define SDXC_CAL_DL_SHIFT   8
0228 #define SDXC_CAL_DL_SW_EN   BIT(7)
0229 #define SDXC_CAL_DL_SW_SHIFT    0
0230 #define SDXC_CAL_DL_MASK    0x3f
0231 
0232 #define SDXC_CAL_TIMEOUT    3   /* in seconds, 3s is enough*/
0233 
0234 struct sunxi_mmc_clk_delay {
0235     u32 output;
0236     u32 sample;
0237 };
0238 
0239 struct sunxi_idma_des {
0240     __le32 config;
0241     __le32 buf_size;
0242     __le32 buf_addr_ptr1;
0243     __le32 buf_addr_ptr2;
0244 };
0245 
0246 struct sunxi_mmc_cfg {
0247     u32 idma_des_size_bits;
0248     u32 idma_des_shift;
0249     const struct sunxi_mmc_clk_delay *clk_delays;
0250 
0251     /* does the IP block support autocalibration? */
0252     bool can_calibrate;
0253 
0254     /* Does DATA0 needs to be masked while the clock is updated */
0255     bool mask_data0;
0256 
0257     /*
0258      * hardware only supports new timing mode, either due to lack of
0259      * a mode switch in the clock controller, or the mmc controller
0260      * is permanently configured in the new timing mode, without the
0261      * NTSR mode switch.
0262      */
0263     bool needs_new_timings;
0264 
0265     /* clock hardware can switch between old and new timing modes */
0266     bool ccu_has_timings_switch;
0267 };
0268 
0269 struct sunxi_mmc_host {
0270     struct device *dev;
0271     struct mmc_host *mmc;
0272     struct reset_control *reset;
0273     const struct sunxi_mmc_cfg *cfg;
0274 
0275     /* IO mapping base */
0276     void __iomem    *reg_base;
0277 
0278     /* clock management */
0279     struct clk  *clk_ahb;
0280     struct clk  *clk_mmc;
0281     struct clk  *clk_sample;
0282     struct clk  *clk_output;
0283 
0284     /* irq */
0285     spinlock_t  lock;
0286     int     irq;
0287     u32     int_sum;
0288     u32     sdio_imask;
0289 
0290     /* dma */
0291     dma_addr_t  sg_dma;
0292     void        *sg_cpu;
0293     bool        wait_dma;
0294 
0295     struct mmc_request *mrq;
0296     struct mmc_request *manual_stop_mrq;
0297     int     ferror;
0298 
0299     /* vqmmc */
0300     bool        vqmmc_enabled;
0301 
0302     /* timings */
0303     bool        use_new_timings;
0304 };
0305 
0306 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
0307 {
0308     unsigned long expire = jiffies + msecs_to_jiffies(250);
0309     u32 rval;
0310 
0311     mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
0312     do {
0313         rval = mmc_readl(host, REG_GCTRL);
0314     } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
0315 
0316     if (rval & SDXC_HARDWARE_RESET) {
0317         dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
0318         return -EIO;
0319     }
0320 
0321     return 0;
0322 }
0323 
0324 static int sunxi_mmc_init_host(struct sunxi_mmc_host *host)
0325 {
0326     u32 rval;
0327 
0328     if (sunxi_mmc_reset_host(host))
0329         return -EIO;
0330 
0331     /*
0332      * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
0333      *
0334      * TODO: sun9i has a larger FIFO and supports higher trigger values
0335      */
0336     mmc_writel(host, REG_FTRGL, 0x20070008);
0337     /* Maximum timeout value */
0338     mmc_writel(host, REG_TMOUT, 0xffffffff);
0339     /* Unmask SDIO interrupt if needed */
0340     mmc_writel(host, REG_IMASK, host->sdio_imask);
0341     /* Clear all pending interrupts */
0342     mmc_writel(host, REG_RINTR, 0xffffffff);
0343     /* Debug register? undocumented */
0344     mmc_writel(host, REG_DBGC, 0xdeb);
0345     /* Enable CEATA support */
0346     mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
0347     /* Set DMA descriptor list base address */
0348     mmc_writel(host, REG_DLBA, host->sg_dma >> host->cfg->idma_des_shift);
0349 
0350     rval = mmc_readl(host, REG_GCTRL);
0351     rval |= SDXC_INTERRUPT_ENABLE_BIT;
0352     /* Undocumented, but found in Allwinner code */
0353     rval &= ~SDXC_ACCESS_DONE_DIRECT;
0354     mmc_writel(host, REG_GCTRL, rval);
0355 
0356     return 0;
0357 }
0358 
0359 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
0360                     struct mmc_data *data)
0361 {
0362     struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
0363     dma_addr_t next_desc = host->sg_dma;
0364     int i, max_len = (1 << host->cfg->idma_des_size_bits);
0365 
0366     for (i = 0; i < data->sg_len; i++) {
0367         pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
0368                          SDXC_IDMAC_DES0_OWN |
0369                          SDXC_IDMAC_DES0_DIC);
0370 
0371         if (data->sg[i].length == max_len)
0372             pdes[i].buf_size = 0; /* 0 == max_len */
0373         else
0374             pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
0375 
0376         next_desc += sizeof(struct sunxi_idma_des);
0377         pdes[i].buf_addr_ptr1 =
0378             cpu_to_le32(sg_dma_address(&data->sg[i]) >>
0379                     host->cfg->idma_des_shift);
0380         pdes[i].buf_addr_ptr2 =
0381             cpu_to_le32(next_desc >>
0382                     host->cfg->idma_des_shift);
0383     }
0384 
0385     pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
0386     pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD |
0387                       SDXC_IDMAC_DES0_ER);
0388     pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC);
0389     pdes[i - 1].buf_addr_ptr2 = 0;
0390 
0391     /*
0392      * Avoid the io-store starting the idmac hitting io-mem before the
0393      * descriptors hit the main-mem.
0394      */
0395     wmb();
0396 }
0397 
0398 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
0399                  struct mmc_data *data)
0400 {
0401     u32 i, dma_len;
0402     struct scatterlist *sg;
0403 
0404     dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
0405                  mmc_get_dma_dir(data));
0406     if (dma_len == 0) {
0407         dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
0408         return -ENOMEM;
0409     }
0410 
0411     for_each_sg(data->sg, sg, data->sg_len, i) {
0412         if (sg->offset & 3 || sg->length & 3) {
0413             dev_err(mmc_dev(host->mmc),
0414                 "unaligned scatterlist: os %x length %d\n",
0415                 sg->offset, sg->length);
0416             return -EINVAL;
0417         }
0418     }
0419 
0420     return 0;
0421 }
0422 
0423 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
0424                 struct mmc_data *data)
0425 {
0426     u32 rval;
0427 
0428     sunxi_mmc_init_idma_des(host, data);
0429 
0430     rval = mmc_readl(host, REG_GCTRL);
0431     rval |= SDXC_DMA_ENABLE_BIT;
0432     mmc_writel(host, REG_GCTRL, rval);
0433     rval |= SDXC_DMA_RESET;
0434     mmc_writel(host, REG_GCTRL, rval);
0435 
0436     mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
0437 
0438     if (!(data->flags & MMC_DATA_WRITE))
0439         mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
0440 
0441     mmc_writel(host, REG_DMAC,
0442            SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
0443 }
0444 
0445 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
0446                        struct mmc_request *req)
0447 {
0448     u32 arg, cmd_val, ri;
0449     unsigned long expire = jiffies + msecs_to_jiffies(1000);
0450 
0451     cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
0452           SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
0453 
0454     if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
0455         cmd_val |= SD_IO_RW_DIRECT;
0456         arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
0457               ((req->cmd->arg >> 28) & 0x7);
0458     } else {
0459         cmd_val |= MMC_STOP_TRANSMISSION;
0460         arg = 0;
0461     }
0462 
0463     mmc_writel(host, REG_CARG, arg);
0464     mmc_writel(host, REG_CMDR, cmd_val);
0465 
0466     do {
0467         ri = mmc_readl(host, REG_RINTR);
0468     } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
0469          time_before(jiffies, expire));
0470 
0471     if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
0472         dev_err(mmc_dev(host->mmc), "send stop command failed\n");
0473         if (req->stop)
0474             req->stop->resp[0] = -ETIMEDOUT;
0475     } else {
0476         if (req->stop)
0477             req->stop->resp[0] = mmc_readl(host, REG_RESP0);
0478     }
0479 
0480     mmc_writel(host, REG_RINTR, 0xffff);
0481 }
0482 
0483 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
0484 {
0485     struct mmc_command *cmd = host->mrq->cmd;
0486     struct mmc_data *data = host->mrq->data;
0487 
0488     /* For some cmds timeout is normal with sd/mmc cards */
0489     if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
0490         SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
0491                       cmd->opcode == SD_IO_RW_DIRECT))
0492         return;
0493 
0494     dev_dbg(mmc_dev(host->mmc),
0495         "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
0496         host->mmc->index, cmd->opcode,
0497         data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
0498         host->int_sum & SDXC_RESP_ERROR     ? " RE"     : "",
0499         host->int_sum & SDXC_RESP_CRC_ERROR  ? " RCE"    : "",
0500         host->int_sum & SDXC_DATA_CRC_ERROR  ? " DCE"    : "",
0501         host->int_sum & SDXC_RESP_TIMEOUT ? " RTO"    : "",
0502         host->int_sum & SDXC_DATA_TIMEOUT ? " DTO"    : "",
0503         host->int_sum & SDXC_FIFO_RUN_ERROR  ? " FE"     : "",
0504         host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL"     : "",
0505         host->int_sum & SDXC_START_BIT_ERROR ? " SBE"    : "",
0506         host->int_sum & SDXC_END_BIT_ERROR   ? " EBE"    : ""
0507         );
0508 }
0509 
0510 /* Called in interrupt context! */
0511 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
0512 {
0513     struct mmc_request *mrq = host->mrq;
0514     struct mmc_data *data = mrq->data;
0515     u32 rval;
0516 
0517     mmc_writel(host, REG_IMASK, host->sdio_imask);
0518     mmc_writel(host, REG_IDIE, 0);
0519 
0520     if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
0521         sunxi_mmc_dump_errinfo(host);
0522         mrq->cmd->error = -ETIMEDOUT;
0523 
0524         if (data) {
0525             data->error = -ETIMEDOUT;
0526             host->manual_stop_mrq = mrq;
0527         }
0528 
0529         if (mrq->stop)
0530             mrq->stop->error = -ETIMEDOUT;
0531     } else {
0532         if (mrq->cmd->flags & MMC_RSP_136) {
0533             mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
0534             mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
0535             mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
0536             mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
0537         } else {
0538             mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
0539         }
0540 
0541         if (data)
0542             data->bytes_xfered = data->blocks * data->blksz;
0543     }
0544 
0545     if (data) {
0546         mmc_writel(host, REG_IDST, 0x337);
0547         mmc_writel(host, REG_DMAC, 0);
0548         rval = mmc_readl(host, REG_GCTRL);
0549         rval |= SDXC_DMA_RESET;
0550         mmc_writel(host, REG_GCTRL, rval);
0551         rval &= ~SDXC_DMA_ENABLE_BIT;
0552         mmc_writel(host, REG_GCTRL, rval);
0553         rval |= SDXC_FIFO_RESET;
0554         mmc_writel(host, REG_GCTRL, rval);
0555         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
0556                  mmc_get_dma_dir(data));
0557     }
0558 
0559     mmc_writel(host, REG_RINTR, 0xffff);
0560 
0561     host->mrq = NULL;
0562     host->int_sum = 0;
0563     host->wait_dma = false;
0564 
0565     return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
0566 }
0567 
0568 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
0569 {
0570     struct sunxi_mmc_host *host = dev_id;
0571     struct mmc_request *mrq;
0572     u32 msk_int, idma_int;
0573     bool finalize = false;
0574     bool sdio_int = false;
0575     irqreturn_t ret = IRQ_HANDLED;
0576 
0577     spin_lock(&host->lock);
0578 
0579     idma_int  = mmc_readl(host, REG_IDST);
0580     msk_int   = mmc_readl(host, REG_MISTA);
0581 
0582     dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
0583         host->mrq, msk_int, idma_int);
0584 
0585     mrq = host->mrq;
0586     if (mrq) {
0587         if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
0588             host->wait_dma = false;
0589 
0590         host->int_sum |= msk_int;
0591 
0592         /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
0593         if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
0594                 !(host->int_sum & SDXC_COMMAND_DONE))
0595             mmc_writel(host, REG_IMASK,
0596                    host->sdio_imask | SDXC_COMMAND_DONE);
0597         /* Don't wait for dma on error */
0598         else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
0599             finalize = true;
0600         else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
0601                 !host->wait_dma)
0602             finalize = true;
0603     }
0604 
0605     if (msk_int & SDXC_SDIO_INTERRUPT)
0606         sdio_int = true;
0607 
0608     mmc_writel(host, REG_RINTR, msk_int);
0609     mmc_writel(host, REG_IDST, idma_int);
0610 
0611     if (finalize)
0612         ret = sunxi_mmc_finalize_request(host);
0613 
0614     spin_unlock(&host->lock);
0615 
0616     if (finalize && ret == IRQ_HANDLED)
0617         mmc_request_done(host->mmc, mrq);
0618 
0619     if (sdio_int)
0620         mmc_signal_sdio_irq(host->mmc);
0621 
0622     return ret;
0623 }
0624 
0625 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
0626 {
0627     struct sunxi_mmc_host *host = dev_id;
0628     struct mmc_request *mrq;
0629     unsigned long iflags;
0630 
0631     spin_lock_irqsave(&host->lock, iflags);
0632     mrq = host->manual_stop_mrq;
0633     spin_unlock_irqrestore(&host->lock, iflags);
0634 
0635     if (!mrq) {
0636         dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
0637         return IRQ_HANDLED;
0638     }
0639 
0640     dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
0641 
0642     /*
0643      * We will never have more than one outstanding request,
0644      * and we do not complete the request until after
0645      * we've cleared host->manual_stop_mrq so we do not need to
0646      * spin lock this function.
0647      * Additionally we have wait states within this function
0648      * so having it in a lock is a very bad idea.
0649      */
0650     sunxi_mmc_send_manual_stop(host, mrq);
0651 
0652     spin_lock_irqsave(&host->lock, iflags);
0653     host->manual_stop_mrq = NULL;
0654     spin_unlock_irqrestore(&host->lock, iflags);
0655 
0656     mmc_request_done(host->mmc, mrq);
0657 
0658     return IRQ_HANDLED;
0659 }
0660 
0661 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
0662 {
0663     unsigned long expire = jiffies + msecs_to_jiffies(750);
0664     u32 rval;
0665 
0666     dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n",
0667         oclk_en ? "en" : "dis");
0668 
0669     rval = mmc_readl(host, REG_CLKCR);
0670     rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
0671 
0672     if (oclk_en)
0673         rval |= SDXC_CARD_CLOCK_ON;
0674     if (host->cfg->mask_data0)
0675         rval |= SDXC_MASK_DATA0;
0676 
0677     mmc_writel(host, REG_CLKCR, rval);
0678 
0679     rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
0680     mmc_writel(host, REG_CMDR, rval);
0681 
0682     do {
0683         rval = mmc_readl(host, REG_CMDR);
0684     } while (time_before(jiffies, expire) && (rval & SDXC_START));
0685 
0686     /* clear irq status bits set by the command */
0687     mmc_writel(host, REG_RINTR,
0688            mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
0689 
0690     if (rval & SDXC_START) {
0691         dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
0692         return -EIO;
0693     }
0694 
0695     if (host->cfg->mask_data0) {
0696         rval = mmc_readl(host, REG_CLKCR);
0697         mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0);
0698     }
0699 
0700     return 0;
0701 }
0702 
0703 static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)
0704 {
0705     if (!host->cfg->can_calibrate)
0706         return 0;
0707 
0708     /*
0709      * FIXME:
0710      * This is not clear how the calibration is supposed to work
0711      * yet. The best rate have been obtained by simply setting the
0712      * delay to 0, as Allwinner does in its BSP.
0713      *
0714      * The only mode that doesn't have such a delay is HS400, that
0715      * is in itself a TODO.
0716      */
0717     writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off);
0718 
0719     return 0;
0720 }
0721 
0722 static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
0723                    struct mmc_ios *ios, u32 rate)
0724 {
0725     int index;
0726 
0727     /* clk controller delays not used under new timings mode */
0728     if (host->use_new_timings)
0729         return 0;
0730 
0731     /* some old controllers don't support delays */
0732     if (!host->cfg->clk_delays)
0733         return 0;
0734 
0735     /* determine delays */
0736     if (rate <= 400000) {
0737         index = SDXC_CLK_400K;
0738     } else if (rate <= 25000000) {
0739         index = SDXC_CLK_25M;
0740     } else if (rate <= 52000000) {
0741         if (ios->timing != MMC_TIMING_UHS_DDR50 &&
0742             ios->timing != MMC_TIMING_MMC_DDR52) {
0743             index = SDXC_CLK_50M;
0744         } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
0745             index = SDXC_CLK_50M_DDR_8BIT;
0746         } else {
0747             index = SDXC_CLK_50M_DDR;
0748         }
0749     } else {
0750         dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n");
0751         return -EINVAL;
0752     }
0753 
0754     clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
0755     clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
0756 
0757     return 0;
0758 }
0759 
0760 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
0761                   struct mmc_ios *ios)
0762 {
0763     struct mmc_host *mmc = host->mmc;
0764     long rate;
0765     u32 rval, clock = ios->clock, div = 1;
0766     int ret;
0767 
0768     ret = sunxi_mmc_oclk_onoff(host, 0);
0769     if (ret)
0770         return ret;
0771 
0772     /* Our clock is gated now */
0773     mmc->actual_clock = 0;
0774 
0775     if (!ios->clock)
0776         return 0;
0777 
0778     /*
0779      * Under the old timing mode, 8 bit DDR requires the module
0780      * clock to be double the card clock. Under the new timing
0781      * mode, all DDR modes require a doubled module clock.
0782      *
0783      * We currently only support the standard MMC DDR52 mode.
0784      * This block should be updated once support for other DDR
0785      * modes is added.
0786      */
0787     if (ios->timing == MMC_TIMING_MMC_DDR52 &&
0788         (host->use_new_timings ||
0789          ios->bus_width == MMC_BUS_WIDTH_8)) {
0790         div = 2;
0791         clock <<= 1;
0792     }
0793 
0794     if (host->use_new_timings && host->cfg->ccu_has_timings_switch) {
0795         ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
0796         if (ret) {
0797             dev_err(mmc_dev(mmc),
0798                 "error setting new timing mode\n");
0799             return ret;
0800         }
0801     }
0802 
0803     rate = clk_round_rate(host->clk_mmc, clock);
0804     if (rate < 0) {
0805         dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n",
0806             clock, rate);
0807         return rate;
0808     }
0809     dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",
0810         clock, rate);
0811 
0812     /* setting clock rate */
0813     ret = clk_set_rate(host->clk_mmc, rate);
0814     if (ret) {
0815         dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n",
0816             rate, ret);
0817         return ret;
0818     }
0819 
0820     /* set internal divider */
0821     rval = mmc_readl(host, REG_CLKCR);
0822     rval &= ~0xff;
0823     rval |= div - 1;
0824     mmc_writel(host, REG_CLKCR, rval);
0825 
0826     /* update card clock rate to account for internal divider */
0827     rate /= div;
0828 
0829     /*
0830      * Configure the controller to use the new timing mode if needed.
0831      * On controllers that only support the new timing mode, such as
0832      * the eMMC controller on the A64, this register does not exist,
0833      * and any writes to it are ignored.
0834      */
0835     if (host->use_new_timings) {
0836         /* Don't touch the delay bits */
0837         rval = mmc_readl(host, REG_SD_NTSR);
0838         rval |= SDXC_2X_TIMING_MODE;
0839         mmc_writel(host, REG_SD_NTSR, rval);
0840     }
0841 
0842     /* sunxi_mmc_clk_set_phase expects the actual card clock rate */
0843     ret = sunxi_mmc_clk_set_phase(host, ios, rate);
0844     if (ret)
0845         return ret;
0846 
0847     ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG);
0848     if (ret)
0849         return ret;
0850 
0851     /*
0852      * FIXME:
0853      *
0854      * In HS400 we'll also need to calibrate the data strobe
0855      * signal. This should only happen on the MMC2 controller (at
0856      * least on the A64).
0857      */
0858 
0859     ret = sunxi_mmc_oclk_onoff(host, 1);
0860     if (ret)
0861         return ret;
0862 
0863     /* And we just enabled our clock back */
0864     mmc->actual_clock = rate;
0865 
0866     return 0;
0867 }
0868 
0869 static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host,
0870                    unsigned char width)
0871 {
0872     switch (width) {
0873     case MMC_BUS_WIDTH_1:
0874         mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
0875         break;
0876     case MMC_BUS_WIDTH_4:
0877         mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
0878         break;
0879     case MMC_BUS_WIDTH_8:
0880         mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
0881         break;
0882     }
0883 }
0884 
0885 static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios)
0886 {
0887     u32 rval;
0888 
0889     /* set ddr mode */
0890     rval = mmc_readl(host, REG_GCTRL);
0891     if (ios->timing == MMC_TIMING_UHS_DDR50 ||
0892         ios->timing == MMC_TIMING_MMC_DDR52)
0893         rval |= SDXC_DDR_MODE;
0894     else
0895         rval &= ~SDXC_DDR_MODE;
0896     mmc_writel(host, REG_GCTRL, rval);
0897 
0898     host->ferror = sunxi_mmc_clk_set_rate(host, ios);
0899     /* Android code had a usleep_range(50000, 55000); here */
0900 }
0901 
0902 static void sunxi_mmc_card_power(struct sunxi_mmc_host *host,
0903                  struct mmc_ios *ios)
0904 {
0905     struct mmc_host *mmc = host->mmc;
0906 
0907     switch (ios->power_mode) {
0908     case MMC_POWER_UP:
0909         dev_dbg(mmc_dev(mmc), "Powering card up\n");
0910 
0911         if (!IS_ERR(mmc->supply.vmmc)) {
0912             host->ferror = mmc_regulator_set_ocr(mmc,
0913                                  mmc->supply.vmmc,
0914                                  ios->vdd);
0915             if (host->ferror)
0916                 return;
0917         }
0918 
0919         if (!IS_ERR(mmc->supply.vqmmc)) {
0920             host->ferror = regulator_enable(mmc->supply.vqmmc);
0921             if (host->ferror) {
0922                 dev_err(mmc_dev(mmc),
0923                     "failed to enable vqmmc\n");
0924                 return;
0925             }
0926             host->vqmmc_enabled = true;
0927         }
0928         break;
0929 
0930     case MMC_POWER_OFF:
0931         dev_dbg(mmc_dev(mmc), "Powering card off\n");
0932 
0933         if (!IS_ERR(mmc->supply.vmmc))
0934             mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
0935 
0936         if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
0937             regulator_disable(mmc->supply.vqmmc);
0938 
0939         host->vqmmc_enabled = false;
0940         break;
0941 
0942     default:
0943         dev_dbg(mmc_dev(mmc), "Ignoring unknown card power state\n");
0944         break;
0945     }
0946 }
0947 
0948 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
0949 {
0950     struct sunxi_mmc_host *host = mmc_priv(mmc);
0951 
0952     sunxi_mmc_card_power(host, ios);
0953     sunxi_mmc_set_bus_width(host, ios->bus_width);
0954     sunxi_mmc_set_clk(host, ios);
0955 }
0956 
0957 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
0958 {
0959     int ret;
0960 
0961     /* vqmmc regulator is available */
0962     if (!IS_ERR(mmc->supply.vqmmc)) {
0963         ret = mmc_regulator_set_vqmmc(mmc, ios);
0964         return ret < 0 ? ret : 0;
0965     }
0966 
0967     /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
0968     if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
0969         return 0;
0970 
0971     return -EINVAL;
0972 }
0973 
0974 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
0975 {
0976     struct sunxi_mmc_host *host = mmc_priv(mmc);
0977     unsigned long flags;
0978     u32 imask;
0979 
0980     if (enable)
0981         pm_runtime_get_noresume(host->dev);
0982 
0983     spin_lock_irqsave(&host->lock, flags);
0984 
0985     imask = mmc_readl(host, REG_IMASK);
0986     if (enable) {
0987         host->sdio_imask = SDXC_SDIO_INTERRUPT;
0988         imask |= SDXC_SDIO_INTERRUPT;
0989     } else {
0990         host->sdio_imask = 0;
0991         imask &= ~SDXC_SDIO_INTERRUPT;
0992     }
0993     mmc_writel(host, REG_IMASK, imask);
0994     spin_unlock_irqrestore(&host->lock, flags);
0995 
0996     if (!enable)
0997         pm_runtime_put_noidle(host->mmc->parent);
0998 }
0999 
1000 static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
1001 {
1002     struct sunxi_mmc_host *host = mmc_priv(mmc);
1003     mmc_writel(host, REG_HWRST, 0);
1004     udelay(10);
1005     mmc_writel(host, REG_HWRST, 1);
1006     udelay(300);
1007 }
1008 
1009 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
1010 {
1011     struct sunxi_mmc_host *host = mmc_priv(mmc);
1012     struct mmc_command *cmd = mrq->cmd;
1013     struct mmc_data *data = mrq->data;
1014     unsigned long iflags;
1015     u32 imask = SDXC_INTERRUPT_ERROR_BIT;
1016     u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
1017     bool wait_dma = host->wait_dma;
1018     int ret;
1019 
1020     /* Check for set_ios errors (should never happen) */
1021     if (host->ferror) {
1022         mrq->cmd->error = host->ferror;
1023         mmc_request_done(mmc, mrq);
1024         return;
1025     }
1026 
1027     if (data) {
1028         ret = sunxi_mmc_map_dma(host, data);
1029         if (ret < 0) {
1030             dev_err(mmc_dev(mmc), "map DMA failed\n");
1031             cmd->error = ret;
1032             data->error = ret;
1033             mmc_request_done(mmc, mrq);
1034             return;
1035         }
1036     }
1037 
1038     if (cmd->opcode == MMC_GO_IDLE_STATE) {
1039         cmd_val |= SDXC_SEND_INIT_SEQUENCE;
1040         imask |= SDXC_COMMAND_DONE;
1041     }
1042 
1043     if (cmd->flags & MMC_RSP_PRESENT) {
1044         cmd_val |= SDXC_RESP_EXPIRE;
1045         if (cmd->flags & MMC_RSP_136)
1046             cmd_val |= SDXC_LONG_RESPONSE;
1047         if (cmd->flags & MMC_RSP_CRC)
1048             cmd_val |= SDXC_CHECK_RESPONSE_CRC;
1049 
1050         if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
1051             cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
1052 
1053             if (cmd->data->stop) {
1054                 imask |= SDXC_AUTO_COMMAND_DONE;
1055                 cmd_val |= SDXC_SEND_AUTO_STOP;
1056             } else {
1057                 imask |= SDXC_DATA_OVER;
1058             }
1059 
1060             if (cmd->data->flags & MMC_DATA_WRITE)
1061                 cmd_val |= SDXC_WRITE;
1062             else
1063                 wait_dma = true;
1064         } else {
1065             imask |= SDXC_COMMAND_DONE;
1066         }
1067     } else {
1068         imask |= SDXC_COMMAND_DONE;
1069     }
1070 
1071     dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
1072         cmd_val & 0x3f, cmd_val, cmd->arg, imask,
1073         mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
1074 
1075     spin_lock_irqsave(&host->lock, iflags);
1076 
1077     if (host->mrq || host->manual_stop_mrq) {
1078         spin_unlock_irqrestore(&host->lock, iflags);
1079 
1080         if (data)
1081             dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
1082                      mmc_get_dma_dir(data));
1083 
1084         dev_err(mmc_dev(mmc), "request already pending\n");
1085         mrq->cmd->error = -EBUSY;
1086         mmc_request_done(mmc, mrq);
1087         return;
1088     }
1089 
1090     if (data) {
1091         mmc_writel(host, REG_BLKSZ, data->blksz);
1092         mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
1093         sunxi_mmc_start_dma(host, data);
1094     }
1095 
1096     host->mrq = mrq;
1097     host->wait_dma = wait_dma;
1098     mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
1099     mmc_writel(host, REG_CARG, cmd->arg);
1100     mmc_writel(host, REG_CMDR, cmd_val);
1101 
1102     spin_unlock_irqrestore(&host->lock, iflags);
1103 }
1104 
1105 static int sunxi_mmc_card_busy(struct mmc_host *mmc)
1106 {
1107     struct sunxi_mmc_host *host = mmc_priv(mmc);
1108 
1109     return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
1110 }
1111 
1112 static const struct mmc_host_ops sunxi_mmc_ops = {
1113     .request     = sunxi_mmc_request,
1114     .set_ios     = sunxi_mmc_set_ios,
1115     .get_ro      = mmc_gpio_get_ro,
1116     .get_cd      = mmc_gpio_get_cd,
1117     .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
1118     .start_signal_voltage_switch = sunxi_mmc_volt_switch,
1119     .card_hw_reset   = sunxi_mmc_hw_reset,
1120     .card_busy   = sunxi_mmc_card_busy,
1121 };
1122 
1123 static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
1124     [SDXC_CLK_400K]     = { .output = 180, .sample = 180 },
1125     [SDXC_CLK_25M]      = { .output = 180, .sample =  75 },
1126     [SDXC_CLK_50M]      = { .output =  90, .sample = 120 },
1127     [SDXC_CLK_50M_DDR]  = { .output =  60, .sample = 120 },
1128     /* Value from A83T "new timing mode". Works but might not be right. */
1129     [SDXC_CLK_50M_DDR_8BIT] = { .output =  90, .sample = 180 },
1130 };
1131 
1132 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
1133     [SDXC_CLK_400K]     = { .output = 180, .sample = 180 },
1134     [SDXC_CLK_25M]      = { .output = 180, .sample =  75 },
1135     [SDXC_CLK_50M]      = { .output = 150, .sample = 120 },
1136     [SDXC_CLK_50M_DDR]  = { .output =  54, .sample =  36 },
1137     [SDXC_CLK_50M_DDR_8BIT] = { .output =  72, .sample =  72 },
1138 };
1139 
1140 static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
1141     .idma_des_size_bits = 13,
1142     .clk_delays = NULL,
1143     .can_calibrate = false,
1144 };
1145 
1146 static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
1147     .idma_des_size_bits = 16,
1148     .clk_delays = NULL,
1149     .can_calibrate = false,
1150 };
1151 
1152 static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
1153     .idma_des_size_bits = 16,
1154     .clk_delays = sunxi_mmc_clk_delays,
1155     .can_calibrate = false,
1156 };
1157 
1158 static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = {
1159     .idma_des_size_bits = 16,
1160     .clk_delays = sunxi_mmc_clk_delays,
1161     .can_calibrate = false,
1162     .ccu_has_timings_switch = true,
1163 };
1164 
1165 static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
1166     .idma_des_size_bits = 16,
1167     .clk_delays = sun9i_mmc_clk_delays,
1168     .can_calibrate = false,
1169 };
1170 
1171 static const struct sunxi_mmc_cfg sun20i_d1_cfg = {
1172     .idma_des_size_bits = 13,
1173     .idma_des_shift = 2,
1174     .can_calibrate = true,
1175     .mask_data0 = true,
1176     .needs_new_timings = true,
1177 };
1178 
1179 static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
1180     .idma_des_size_bits = 16,
1181     .clk_delays = NULL,
1182     .can_calibrate = true,
1183     .mask_data0 = true,
1184     .needs_new_timings = true,
1185 };
1186 
1187 static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
1188     .idma_des_size_bits = 13,
1189     .clk_delays = NULL,
1190     .can_calibrate = true,
1191     .needs_new_timings = true,
1192 };
1193 
1194 static const struct sunxi_mmc_cfg sun50i_a100_cfg = {
1195     .idma_des_size_bits = 16,
1196     .idma_des_shift = 2,
1197     .clk_delays = NULL,
1198     .can_calibrate = true,
1199     .mask_data0 = true,
1200     .needs_new_timings = true,
1201 };
1202 
1203 static const struct sunxi_mmc_cfg sun50i_a100_emmc_cfg = {
1204     .idma_des_size_bits = 13,
1205     .idma_des_shift = 2,
1206     .clk_delays = NULL,
1207     .can_calibrate = true,
1208     .needs_new_timings = true,
1209 };
1210 
1211 static const struct of_device_id sunxi_mmc_of_match[] = {
1212     { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
1213     { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
1214     { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
1215     { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg },
1216     { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
1217     { .compatible = "allwinner,sun20i-d1-mmc", .data = &sun20i_d1_cfg },
1218     { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
1219     { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
1220     { .compatible = "allwinner,sun50i-a100-mmc", .data = &sun50i_a100_cfg },
1221     { .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg },
1222     { /* sentinel */ }
1223 };
1224 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
1225 
1226 static int sunxi_mmc_enable(struct sunxi_mmc_host *host)
1227 {
1228     int ret;
1229 
1230     if (!IS_ERR(host->reset)) {
1231         ret = reset_control_reset(host->reset);
1232         if (ret) {
1233             dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n",
1234                 ret);
1235             return ret;
1236         }
1237     }
1238 
1239     ret = clk_prepare_enable(host->clk_ahb);
1240     if (ret) {
1241         dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret);
1242         goto error_assert_reset;
1243     }
1244 
1245     ret = clk_prepare_enable(host->clk_mmc);
1246     if (ret) {
1247         dev_err(host->dev, "Enable mmc clk err %d\n", ret);
1248         goto error_disable_clk_ahb;
1249     }
1250 
1251     ret = clk_prepare_enable(host->clk_output);
1252     if (ret) {
1253         dev_err(host->dev, "Enable output clk err %d\n", ret);
1254         goto error_disable_clk_mmc;
1255     }
1256 
1257     ret = clk_prepare_enable(host->clk_sample);
1258     if (ret) {
1259         dev_err(host->dev, "Enable sample clk err %d\n", ret);
1260         goto error_disable_clk_output;
1261     }
1262 
1263     /*
1264      * Sometimes the controller asserts the irq on boot for some reason,
1265      * make sure the controller is in a sane state before enabling irqs.
1266      */
1267     ret = sunxi_mmc_reset_host(host);
1268     if (ret)
1269         goto error_disable_clk_sample;
1270 
1271     return 0;
1272 
1273 error_disable_clk_sample:
1274     clk_disable_unprepare(host->clk_sample);
1275 error_disable_clk_output:
1276     clk_disable_unprepare(host->clk_output);
1277 error_disable_clk_mmc:
1278     clk_disable_unprepare(host->clk_mmc);
1279 error_disable_clk_ahb:
1280     clk_disable_unprepare(host->clk_ahb);
1281 error_assert_reset:
1282     if (!IS_ERR(host->reset))
1283         reset_control_assert(host->reset);
1284     return ret;
1285 }
1286 
1287 static void sunxi_mmc_disable(struct sunxi_mmc_host *host)
1288 {
1289     sunxi_mmc_reset_host(host);
1290 
1291     clk_disable_unprepare(host->clk_sample);
1292     clk_disable_unprepare(host->clk_output);
1293     clk_disable_unprepare(host->clk_mmc);
1294     clk_disable_unprepare(host->clk_ahb);
1295 
1296     if (!IS_ERR(host->reset))
1297         reset_control_assert(host->reset);
1298 }
1299 
1300 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
1301                       struct platform_device *pdev)
1302 {
1303     int ret;
1304 
1305     host->cfg = of_device_get_match_data(&pdev->dev);
1306     if (!host->cfg)
1307         return -EINVAL;
1308 
1309     ret = mmc_regulator_get_supply(host->mmc);
1310     if (ret)
1311         return ret;
1312 
1313     host->reg_base = devm_platform_ioremap_resource(pdev, 0);
1314     if (IS_ERR(host->reg_base))
1315         return PTR_ERR(host->reg_base);
1316 
1317     host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1318     if (IS_ERR(host->clk_ahb)) {
1319         dev_err(&pdev->dev, "Could not get ahb clock\n");
1320         return PTR_ERR(host->clk_ahb);
1321     }
1322 
1323     host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
1324     if (IS_ERR(host->clk_mmc)) {
1325         dev_err(&pdev->dev, "Could not get mmc clock\n");
1326         return PTR_ERR(host->clk_mmc);
1327     }
1328 
1329     if (host->cfg->clk_delays) {
1330         host->clk_output = devm_clk_get(&pdev->dev, "output");
1331         if (IS_ERR(host->clk_output)) {
1332             dev_err(&pdev->dev, "Could not get output clock\n");
1333             return PTR_ERR(host->clk_output);
1334         }
1335 
1336         host->clk_sample = devm_clk_get(&pdev->dev, "sample");
1337         if (IS_ERR(host->clk_sample)) {
1338             dev_err(&pdev->dev, "Could not get sample clock\n");
1339             return PTR_ERR(host->clk_sample);
1340         }
1341     }
1342 
1343     host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1344                                 "ahb");
1345     if (PTR_ERR(host->reset) == -EPROBE_DEFER)
1346         return PTR_ERR(host->reset);
1347 
1348     ret = sunxi_mmc_enable(host);
1349     if (ret)
1350         return ret;
1351 
1352     host->irq = platform_get_irq(pdev, 0);
1353     if (host->irq <= 0) {
1354         ret = -EINVAL;
1355         goto error_disable_mmc;
1356     }
1357 
1358     return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1359             sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1360 
1361 error_disable_mmc:
1362     sunxi_mmc_disable(host);
1363     return ret;
1364 }
1365 
1366 static int sunxi_mmc_probe(struct platform_device *pdev)
1367 {
1368     struct sunxi_mmc_host *host;
1369     struct mmc_host *mmc;
1370     int ret;
1371 
1372     mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1373     if (!mmc) {
1374         dev_err(&pdev->dev, "mmc alloc host failed\n");
1375         return -ENOMEM;
1376     }
1377     platform_set_drvdata(pdev, mmc);
1378 
1379     host = mmc_priv(mmc);
1380     host->dev = &pdev->dev;
1381     host->mmc = mmc;
1382     spin_lock_init(&host->lock);
1383 
1384     ret = sunxi_mmc_resource_request(host, pdev);
1385     if (ret)
1386         goto error_free_host;
1387 
1388     host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1389                       &host->sg_dma, GFP_KERNEL);
1390     if (!host->sg_cpu) {
1391         dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1392         ret = -ENOMEM;
1393         goto error_free_host;
1394     }
1395 
1396     if (host->cfg->ccu_has_timings_switch) {
1397         /*
1398          * Supports both old and new timing modes.
1399          * Try setting the clk to new timing mode.
1400          */
1401         sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
1402 
1403         /* And check the result */
1404         ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc);
1405         if (ret < 0) {
1406             /*
1407              * For whatever reason we were not able to get
1408              * the current active mode. Default to old mode.
1409              */
1410             dev_warn(&pdev->dev, "MMC clk timing mode unknown\n");
1411             host->use_new_timings = false;
1412         } else {
1413             host->use_new_timings = !!ret;
1414         }
1415     } else if (host->cfg->needs_new_timings) {
1416         /* Supports new timing mode only */
1417         host->use_new_timings = true;
1418     }
1419 
1420     mmc->ops        = &sunxi_mmc_ops;
1421     mmc->max_blk_count  = 8192;
1422     mmc->max_blk_size   = 4096;
1423     mmc->max_segs       = PAGE_SIZE / sizeof(struct sunxi_idma_des);
1424     mmc->max_seg_size   = (1 << host->cfg->idma_des_size_bits);
1425     mmc->max_req_size   = mmc->max_seg_size * mmc->max_segs;
1426     /* 400kHz ~ 52MHz */
1427     mmc->f_min      =   400000;
1428     mmc->f_max      = 52000000;
1429     mmc->caps          |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1430                   MMC_CAP_SDIO_IRQ;
1431 
1432     /*
1433      * Some H5 devices do not have signal traces precise enough to
1434      * use HS DDR mode for their eMMC chips.
1435      *
1436      * We still enable HS DDR modes for all the other controller
1437      * variants that support them.
1438      */
1439     if ((host->cfg->clk_delays || host->use_new_timings) &&
1440         !of_device_is_compatible(pdev->dev.of_node,
1441                      "allwinner,sun50i-h5-emmc"))
1442         mmc->caps      |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1443 
1444     ret = mmc_of_parse(mmc);
1445     if (ret)
1446         goto error_free_dma;
1447 
1448     /*
1449      * If we don't support delay chains in the SoC, we can't use any
1450      * of the higher speed modes. Mask them out in case the device
1451      * tree specifies the properties for them, which gets added to
1452      * the caps by mmc_of_parse() above.
1453      */
1454     if (!(host->cfg->clk_delays || host->use_new_timings)) {
1455         mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR |
1456                    MMC_CAP_1_2V_DDR | MMC_CAP_UHS);
1457         mmc->caps2 &= ~MMC_CAP2_HS200;
1458     }
1459 
1460     /* TODO: This driver doesn't support HS400 mode yet */
1461     mmc->caps2 &= ~MMC_CAP2_HS400;
1462 
1463     ret = sunxi_mmc_init_host(host);
1464     if (ret)
1465         goto error_free_dma;
1466 
1467     pm_runtime_set_active(&pdev->dev);
1468     pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1469     pm_runtime_use_autosuspend(&pdev->dev);
1470     pm_runtime_enable(&pdev->dev);
1471 
1472     ret = mmc_add_host(mmc);
1473     if (ret)
1474         goto error_free_dma;
1475 
1476     dev_info(&pdev->dev, "initialized, max. request size: %u KB%s\n",
1477          mmc->max_req_size >> 10,
1478          host->use_new_timings ? ", uses new timings mode" : "");
1479 
1480     return 0;
1481 
1482 error_free_dma:
1483     dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1484 error_free_host:
1485     mmc_free_host(mmc);
1486     return ret;
1487 }
1488 
1489 static int sunxi_mmc_remove(struct platform_device *pdev)
1490 {
1491     struct mmc_host *mmc = platform_get_drvdata(pdev);
1492     struct sunxi_mmc_host *host = mmc_priv(mmc);
1493 
1494     mmc_remove_host(mmc);
1495     pm_runtime_force_suspend(&pdev->dev);
1496     disable_irq(host->irq);
1497     sunxi_mmc_disable(host);
1498     dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1499     mmc_free_host(mmc);
1500 
1501     return 0;
1502 }
1503 
1504 #ifdef CONFIG_PM
1505 static int sunxi_mmc_runtime_resume(struct device *dev)
1506 {
1507     struct mmc_host *mmc = dev_get_drvdata(dev);
1508     struct sunxi_mmc_host *host = mmc_priv(mmc);
1509     int ret;
1510 
1511     ret = sunxi_mmc_enable(host);
1512     if (ret)
1513         return ret;
1514 
1515     sunxi_mmc_init_host(host);
1516     sunxi_mmc_set_bus_width(host, mmc->ios.bus_width);
1517     sunxi_mmc_set_clk(host, &mmc->ios);
1518     enable_irq(host->irq);
1519 
1520     return 0;
1521 }
1522 
1523 static int sunxi_mmc_runtime_suspend(struct device *dev)
1524 {
1525     struct mmc_host *mmc = dev_get_drvdata(dev);
1526     struct sunxi_mmc_host *host = mmc_priv(mmc);
1527 
1528     /*
1529      * When clocks are off, it's possible receiving
1530      * fake interrupts, which will stall the system.
1531      * Disabling the irq  will prevent this.
1532      */
1533     disable_irq(host->irq);
1534     sunxi_mmc_reset_host(host);
1535     sunxi_mmc_disable(host);
1536 
1537     return 0;
1538 }
1539 #endif
1540 
1541 static const struct dev_pm_ops sunxi_mmc_pm_ops = {
1542     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1543                 pm_runtime_force_resume)
1544     SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend,
1545                sunxi_mmc_runtime_resume,
1546                NULL)
1547 };
1548 
1549 static struct platform_driver sunxi_mmc_driver = {
1550     .driver = {
1551         .name   = "sunxi-mmc",
1552         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1553         .of_match_table = sunxi_mmc_of_match,
1554         .pm = &sunxi_mmc_pm_ops,
1555     },
1556     .probe      = sunxi_mmc_probe,
1557     .remove     = sunxi_mmc_remove,
1558 };
1559 module_platform_driver(sunxi_mmc_driver);
1560 
1561 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1562 MODULE_LICENSE("GPL v2");
1563 MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>");
1564 MODULE_ALIAS("platform:sunxi-mmc");
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