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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  sdricoh_cs.c - driver for Ricoh Secure Digital Card Readers that can be
0004  *     found on some Ricoh RL5c476 II cardbus bridge
0005  *
0006  *  Copyright (C) 2006 - 2008 Sascha Sommer <saschasommer@freenet.de>
0007  */
0008 
0009 /*
0010 #define DEBUG
0011 #define VERBOSE_DEBUG
0012 */
0013 #include <linux/delay.h>
0014 #include <linux/highmem.h>
0015 #include <linux/module.h>
0016 #include <linux/pci.h>
0017 #include <linux/ioport.h>
0018 #include <linux/iopoll.h>
0019 #include <linux/scatterlist.h>
0020 
0021 #include <pcmcia/cistpl.h>
0022 #include <pcmcia/ds.h>
0023 #include <linux/io.h>
0024 
0025 #include <linux/mmc/host.h>
0026 #include <linux/mmc/mmc.h>
0027 
0028 #define DRIVER_NAME "sdricoh_cs"
0029 
0030 static unsigned int switchlocked;
0031 
0032 /* i/o region */
0033 #define SDRICOH_PCI_REGION 0
0034 #define SDRICOH_PCI_REGION_SIZE 0x1000
0035 
0036 /* registers */
0037 #define R104_VERSION     0x104
0038 #define R200_CMD         0x200
0039 #define R204_CMD_ARG     0x204
0040 #define R208_DATAIO      0x208
0041 #define R20C_RESP        0x20c
0042 #define R21C_STATUS      0x21c
0043 #define R2E0_INIT        0x2e0
0044 #define R2E4_STATUS_RESP 0x2e4
0045 #define R2F0_RESET       0x2f0
0046 #define R224_MODE        0x224
0047 #define R226_BLOCKSIZE   0x226
0048 #define R228_POWER       0x228
0049 #define R230_DATA        0x230
0050 
0051 /* flags for the R21C_STATUS register */
0052 #define STATUS_CMD_FINISHED      0x00000001
0053 #define STATUS_TRANSFER_FINISHED 0x00000004
0054 #define STATUS_CARD_INSERTED     0x00000020
0055 #define STATUS_CARD_LOCKED       0x00000080
0056 #define STATUS_CMD_TIMEOUT       0x00400000
0057 #define STATUS_READY_TO_READ     0x01000000
0058 #define STATUS_READY_TO_WRITE    0x02000000
0059 #define STATUS_BUSY              0x40000000
0060 
0061 /* timeouts */
0062 #define SDRICOH_CMD_TIMEOUT_US  1000000
0063 #define SDRICOH_DATA_TIMEOUT_US 1000000
0064 
0065 /* list of supported pcmcia devices */
0066 static const struct pcmcia_device_id pcmcia_ids[] = {
0067     /* vendor and device strings followed by their crc32 hashes */
0068     PCMCIA_DEVICE_PROD_ID12("RICOH", "Bay1Controller", 0xd9f522ed,
0069                 0xc3901202),
0070     PCMCIA_DEVICE_PROD_ID12("RICOH", "Bay Controller", 0xd9f522ed,
0071                 0xace80909),
0072     PCMCIA_DEVICE_NULL,
0073 };
0074 
0075 MODULE_DEVICE_TABLE(pcmcia, pcmcia_ids);
0076 
0077 /* mmc privdata */
0078 struct sdricoh_host {
0079     struct device *dev;
0080     struct mmc_host *mmc;   /* MMC structure */
0081     unsigned char __iomem *iobase;
0082     struct pci_dev *pci_dev;
0083     int app_cmd;
0084 };
0085 
0086 /***************** register i/o helper functions *****************************/
0087 
0088 static inline unsigned int sdricoh_readl(struct sdricoh_host *host,
0089                      unsigned int reg)
0090 {
0091     unsigned int value = readl(host->iobase + reg);
0092     dev_vdbg(host->dev, "rl %x 0x%x\n", reg, value);
0093     return value;
0094 }
0095 
0096 static inline void sdricoh_writel(struct sdricoh_host *host, unsigned int reg,
0097                   unsigned int value)
0098 {
0099     writel(value, host->iobase + reg);
0100     dev_vdbg(host->dev, "wl %x 0x%x\n", reg, value);
0101 
0102 }
0103 
0104 static inline unsigned int sdricoh_readw(struct sdricoh_host *host,
0105                      unsigned int reg)
0106 {
0107     unsigned int value = readw(host->iobase + reg);
0108     dev_vdbg(host->dev, "rb %x 0x%x\n", reg, value);
0109     return value;
0110 }
0111 
0112 static inline void sdricoh_writew(struct sdricoh_host *host, unsigned int reg,
0113                      unsigned short value)
0114 {
0115     writew(value, host->iobase + reg);
0116     dev_vdbg(host->dev, "ww %x 0x%x\n", reg, value);
0117 }
0118 
0119 static inline unsigned int sdricoh_readb(struct sdricoh_host *host,
0120                      unsigned int reg)
0121 {
0122     unsigned int value = readb(host->iobase + reg);
0123     dev_vdbg(host->dev, "rb %x 0x%x\n", reg, value);
0124     return value;
0125 }
0126 
0127 static bool sdricoh_status_ok(struct sdricoh_host *host, unsigned int status,
0128                   unsigned int wanted)
0129 {
0130     sdricoh_writel(host, R2E4_STATUS_RESP, status);
0131     return status & wanted;
0132 }
0133 
0134 static int sdricoh_query_status(struct sdricoh_host *host, unsigned int wanted)
0135 {
0136     int ret;
0137     unsigned int status = 0;
0138     struct device *dev = host->dev;
0139 
0140     ret = read_poll_timeout(sdricoh_readl, status,
0141                 sdricoh_status_ok(host, status, wanted),
0142                 32, SDRICOH_DATA_TIMEOUT_US, false,
0143                 host, R21C_STATUS);
0144     if (ret) {
0145         dev_err(dev, "query_status: timeout waiting for %x\n", wanted);
0146         return -ETIMEDOUT;
0147     }
0148 
0149     /* do not do this check in the loop as some commands fail otherwise */
0150     if (status & 0x7F0000) {
0151         dev_err(dev, "waiting for status bit %x failed\n", wanted);
0152         return -EINVAL;
0153     }
0154     return 0;
0155 
0156 }
0157 
0158 static int sdricoh_mmc_cmd(struct sdricoh_host *host, struct mmc_command *cmd)
0159 {
0160     unsigned int status, timeout_us;
0161     int ret;
0162     unsigned char opcode = cmd->opcode;
0163 
0164     /* reset status reg? */
0165     sdricoh_writel(host, R21C_STATUS, 0x18);
0166 
0167     /* MMC_APP_CMDs need some special handling */
0168     if (host->app_cmd) {
0169         opcode |= 64;
0170         host->app_cmd = 0;
0171     } else if (opcode == MMC_APP_CMD)
0172         host->app_cmd = 1;
0173 
0174     /* fill parameters */
0175     sdricoh_writel(host, R204_CMD_ARG, cmd->arg);
0176     sdricoh_writel(host, R200_CMD, (0x10000 << 8) | opcode);
0177 
0178     /* wait for command completion */
0179     if (!opcode)
0180         return 0;
0181 
0182     timeout_us = cmd->busy_timeout ? cmd->busy_timeout * 1000 :
0183         SDRICOH_CMD_TIMEOUT_US;
0184 
0185     ret = read_poll_timeout(sdricoh_readl, status,
0186             sdricoh_status_ok(host, status, STATUS_CMD_FINISHED),
0187             32, timeout_us, false,
0188             host, R21C_STATUS);
0189 
0190     /*
0191      * Don't check for timeout status in the loop, as it's not always reset
0192      * correctly.
0193      */
0194     if (ret || status & STATUS_CMD_TIMEOUT)
0195         return -ETIMEDOUT;
0196 
0197     return 0;
0198 }
0199 
0200 static int sdricoh_reset(struct sdricoh_host *host)
0201 {
0202     dev_dbg(host->dev, "reset\n");
0203     sdricoh_writel(host, R2F0_RESET, 0x10001);
0204     sdricoh_writel(host, R2E0_INIT, 0x10000);
0205     if (sdricoh_readl(host, R2E0_INIT) != 0x10000)
0206         return -EIO;
0207     sdricoh_writel(host, R2E0_INIT, 0x10007);
0208 
0209     sdricoh_writel(host, R224_MODE, 0x2000000);
0210     sdricoh_writel(host, R228_POWER, 0xe0);
0211 
0212 
0213     /* status register ? */
0214     sdricoh_writel(host, R21C_STATUS, 0x18);
0215 
0216     return 0;
0217 }
0218 
0219 static int sdricoh_blockio(struct sdricoh_host *host, int read,
0220                 u8 *buf, int len)
0221 {
0222     int size;
0223     u32 data = 0;
0224     /* wait until the data is available */
0225     if (read) {
0226         if (sdricoh_query_status(host, STATUS_READY_TO_READ))
0227             return -ETIMEDOUT;
0228         sdricoh_writel(host, R21C_STATUS, 0x18);
0229         /* read data */
0230         while (len) {
0231             data = sdricoh_readl(host, R230_DATA);
0232             size = min(len, 4);
0233             len -= size;
0234             while (size) {
0235                 *buf = data & 0xFF;
0236                 buf++;
0237                 data >>= 8;
0238                 size--;
0239             }
0240         }
0241     } else {
0242         if (sdricoh_query_status(host, STATUS_READY_TO_WRITE))
0243             return -ETIMEDOUT;
0244         sdricoh_writel(host, R21C_STATUS, 0x18);
0245         /* write data */
0246         while (len) {
0247             size = min(len, 4);
0248             len -= size;
0249             while (size) {
0250                 data >>= 8;
0251                 data |= (u32)*buf << 24;
0252                 buf++;
0253                 size--;
0254             }
0255             sdricoh_writel(host, R230_DATA, data);
0256         }
0257     }
0258 
0259     return 0;
0260 }
0261 
0262 static void sdricoh_request(struct mmc_host *mmc, struct mmc_request *mrq)
0263 {
0264     struct sdricoh_host *host = mmc_priv(mmc);
0265     struct mmc_command *cmd = mrq->cmd;
0266     struct mmc_data *data = cmd->data;
0267     struct device *dev = host->dev;
0268     int i;
0269 
0270     dev_dbg(dev, "=============================\n");
0271     dev_dbg(dev, "sdricoh_request opcode=%i\n", cmd->opcode);
0272 
0273     sdricoh_writel(host, R21C_STATUS, 0x18);
0274 
0275     /* read/write commands seem to require this */
0276     if (data) {
0277         sdricoh_writew(host, R226_BLOCKSIZE, data->blksz);
0278         sdricoh_writel(host, R208_DATAIO, 0);
0279     }
0280 
0281     cmd->error = sdricoh_mmc_cmd(host, cmd);
0282 
0283     /* read response buffer */
0284     if (cmd->flags & MMC_RSP_PRESENT) {
0285         if (cmd->flags & MMC_RSP_136) {
0286             /* CRC is stripped so we need to do some shifting. */
0287             for (i = 0; i < 4; i++) {
0288                 cmd->resp[i] =
0289                     sdricoh_readl(host,
0290                           R20C_RESP + (3 - i) * 4) << 8;
0291                 if (i != 3)
0292                     cmd->resp[i] |=
0293                         sdricoh_readb(host, R20C_RESP +
0294                               (3 - i) * 4 - 1);
0295             }
0296         } else
0297             cmd->resp[0] = sdricoh_readl(host, R20C_RESP);
0298     }
0299 
0300     /* transfer data */
0301     if (data && cmd->error == 0) {
0302         dev_dbg(dev, "transfer: blksz %i blocks %i sg_len %i "
0303             "sg length %i\n", data->blksz, data->blocks,
0304             data->sg_len, data->sg->length);
0305 
0306         /* enter data reading mode */
0307         sdricoh_writel(host, R21C_STATUS, 0x837f031e);
0308         for (i = 0; i < data->blocks; i++) {
0309             size_t len = data->blksz;
0310             u8 *buf;
0311             struct page *page;
0312             int result;
0313             page = sg_page(data->sg);
0314 
0315             buf = kmap(page) + data->sg->offset + (len * i);
0316             result =
0317                 sdricoh_blockio(host,
0318                     data->flags & MMC_DATA_READ, buf, len);
0319             kunmap(page);
0320             flush_dcache_page(page);
0321             if (result) {
0322                 dev_err(dev, "sdricoh_request: cmd %i "
0323                     "block transfer failed\n", cmd->opcode);
0324                 cmd->error = result;
0325                 break;
0326             } else
0327                 data->bytes_xfered += len;
0328         }
0329 
0330         sdricoh_writel(host, R208_DATAIO, 1);
0331 
0332         if (sdricoh_query_status(host, STATUS_TRANSFER_FINISHED)) {
0333             dev_err(dev, "sdricoh_request: transfer end error\n");
0334             cmd->error = -EINVAL;
0335         }
0336     }
0337     /* FIXME check busy flag */
0338 
0339     mmc_request_done(mmc, mrq);
0340     dev_dbg(dev, "=============================\n");
0341 }
0342 
0343 static void sdricoh_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
0344 {
0345     struct sdricoh_host *host = mmc_priv(mmc);
0346     dev_dbg(host->dev, "set_ios\n");
0347 
0348     if (ios->power_mode == MMC_POWER_ON) {
0349         sdricoh_writel(host, R228_POWER, 0xc0e0);
0350 
0351         if (ios->bus_width == MMC_BUS_WIDTH_4) {
0352             sdricoh_writel(host, R224_MODE, 0x2000300);
0353             sdricoh_writel(host, R228_POWER, 0x40e0);
0354         } else {
0355             sdricoh_writel(host, R224_MODE, 0x2000340);
0356         }
0357 
0358     } else if (ios->power_mode == MMC_POWER_UP) {
0359         sdricoh_writel(host, R224_MODE, 0x2000320);
0360         sdricoh_writel(host, R228_POWER, 0xe0);
0361     }
0362 }
0363 
0364 static int sdricoh_get_ro(struct mmc_host *mmc)
0365 {
0366     struct sdricoh_host *host = mmc_priv(mmc);
0367     unsigned int status;
0368 
0369     status = sdricoh_readl(host, R21C_STATUS);
0370     sdricoh_writel(host, R2E4_STATUS_RESP, status);
0371 
0372     /* some notebooks seem to have the locked flag switched */
0373     if (switchlocked)
0374         return !(status & STATUS_CARD_LOCKED);
0375 
0376     return (status & STATUS_CARD_LOCKED);
0377 }
0378 
0379 static const struct mmc_host_ops sdricoh_ops = {
0380     .request = sdricoh_request,
0381     .set_ios = sdricoh_set_ios,
0382     .get_ro = sdricoh_get_ro,
0383 };
0384 
0385 /* initialize the control and register it to the mmc framework */
0386 static int sdricoh_init_mmc(struct pci_dev *pci_dev,
0387                 struct pcmcia_device *pcmcia_dev)
0388 {
0389     int result;
0390     void __iomem *iobase;
0391     struct mmc_host *mmc;
0392     struct sdricoh_host *host;
0393     struct device *dev = &pcmcia_dev->dev;
0394     /* map iomem */
0395     if (pci_resource_len(pci_dev, SDRICOH_PCI_REGION) !=
0396         SDRICOH_PCI_REGION_SIZE) {
0397         dev_dbg(dev, "unexpected pci resource len\n");
0398         return -ENODEV;
0399     }
0400     iobase =
0401         pci_iomap(pci_dev, SDRICOH_PCI_REGION, SDRICOH_PCI_REGION_SIZE);
0402     if (!iobase) {
0403         dev_err(dev, "unable to map iobase\n");
0404         return -ENODEV;
0405     }
0406     /* check version? */
0407     if (readl(iobase + R104_VERSION) != 0x4000) {
0408         dev_dbg(dev, "no supported mmc controller found\n");
0409         result = -ENODEV;
0410         goto unmap_io;
0411     }
0412     /* allocate privdata */
0413     mmc = pcmcia_dev->priv =
0414         mmc_alloc_host(sizeof(struct sdricoh_host), &pcmcia_dev->dev);
0415     if (!mmc) {
0416         dev_err(dev, "mmc_alloc_host failed\n");
0417         result = -ENOMEM;
0418         goto unmap_io;
0419     }
0420     host = mmc_priv(mmc);
0421 
0422     host->iobase = iobase;
0423     host->dev = dev;
0424     host->pci_dev = pci_dev;
0425 
0426     mmc->ops = &sdricoh_ops;
0427 
0428     /* FIXME: frequency and voltage handling is done by the controller
0429      */
0430     mmc->f_min = 450000;
0431     mmc->f_max = 24000000;
0432     mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
0433     mmc->caps |= MMC_CAP_4_BIT_DATA;
0434 
0435     mmc->max_seg_size = 1024 * 512;
0436     mmc->max_blk_size = 512;
0437 
0438     /* reset the controller */
0439     if (sdricoh_reset(host)) {
0440         dev_dbg(dev, "could not reset\n");
0441         result = -EIO;
0442         goto free_host;
0443     }
0444 
0445     result = mmc_add_host(mmc);
0446 
0447     if (!result) {
0448         dev_dbg(dev, "mmc host registered\n");
0449         return 0;
0450     }
0451 free_host:
0452     mmc_free_host(mmc);
0453 unmap_io:
0454     pci_iounmap(pci_dev, iobase);
0455     return result;
0456 }
0457 
0458 /* search for supported mmc controllers */
0459 static int sdricoh_pcmcia_probe(struct pcmcia_device *pcmcia_dev)
0460 {
0461     struct pci_dev *pci_dev = NULL;
0462 
0463     dev_info(&pcmcia_dev->dev, "Searching MMC controller for pcmcia device"
0464         " %s %s ...\n", pcmcia_dev->prod_id[0], pcmcia_dev->prod_id[1]);
0465 
0466     /* search pci cardbus bridge that contains the mmc controller */
0467     /* the io region is already claimed by yenta_socket... */
0468     while ((pci_dev =
0469         pci_get_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476,
0470                    pci_dev))) {
0471         /* try to init the device */
0472         if (!sdricoh_init_mmc(pci_dev, pcmcia_dev)) {
0473             dev_info(&pcmcia_dev->dev, "MMC controller found\n");
0474             return 0;
0475         }
0476 
0477     }
0478     dev_err(&pcmcia_dev->dev, "No MMC controller was found.\n");
0479     return -ENODEV;
0480 }
0481 
0482 static void sdricoh_pcmcia_detach(struct pcmcia_device *link)
0483 {
0484     struct mmc_host *mmc = link->priv;
0485 
0486     dev_dbg(&link->dev, "detach\n");
0487 
0488     /* remove mmc host */
0489     if (mmc) {
0490         struct sdricoh_host *host = mmc_priv(mmc);
0491         mmc_remove_host(mmc);
0492         pci_iounmap(host->pci_dev, host->iobase);
0493         pci_dev_put(host->pci_dev);
0494         mmc_free_host(mmc);
0495     }
0496     pcmcia_disable_device(link);
0497 
0498 }
0499 
0500 #ifdef CONFIG_PM
0501 static int sdricoh_pcmcia_suspend(struct pcmcia_device *link)
0502 {
0503     dev_dbg(&link->dev, "suspend\n");
0504     return 0;
0505 }
0506 
0507 static int sdricoh_pcmcia_resume(struct pcmcia_device *link)
0508 {
0509     struct mmc_host *mmc = link->priv;
0510     dev_dbg(&link->dev, "resume\n");
0511     sdricoh_reset(mmc_priv(mmc));
0512     return 0;
0513 }
0514 #else
0515 #define sdricoh_pcmcia_suspend NULL
0516 #define sdricoh_pcmcia_resume NULL
0517 #endif
0518 
0519 static struct pcmcia_driver sdricoh_driver = {
0520     .name = DRIVER_NAME,
0521     .probe = sdricoh_pcmcia_probe,
0522     .remove = sdricoh_pcmcia_detach,
0523     .id_table = pcmcia_ids,
0524     .suspend = sdricoh_pcmcia_suspend,
0525     .resume = sdricoh_pcmcia_resume,
0526 };
0527 module_pcmcia_driver(sdricoh_driver);
0528 
0529 module_param(switchlocked, uint, 0444);
0530 
0531 MODULE_AUTHOR("Sascha Sommer <saschasommer@freenet.de>");
0532 MODULE_DESCRIPTION("Ricoh PCMCIA Secure Digital Interface driver");
0533 MODULE_LICENSE("GPL");
0534 
0535 MODULE_PARM_DESC(switchlocked, "Switch the cards locked status."
0536         "Use this when unlocked cards are shown readonly (default 0)");
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