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OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
0004  *              Vincent Yang <vincent.yang@tw.fujitsu.com>
0005  * Copyright (C) 2015 Linaro Ltd  Andy Green <andy.green@linaro.org>
0006  * Copyright (C) 2019 Socionext Inc.
0007  *
0008  */
0009 
0010 /* F_SDH30 extended Controller registers */
0011 #define F_SDH30_AHB_CONFIG      0x100
0012 #define  F_SDH30_AHB_BIGED      BIT(6)
0013 #define  F_SDH30_BUSLOCK_DMA    BIT(5)
0014 #define  F_SDH30_BUSLOCK_EN     BIT(4)
0015 #define  F_SDH30_SIN            BIT(3)
0016 #define  F_SDH30_AHB_INCR_16    BIT(2)
0017 #define  F_SDH30_AHB_INCR_8     BIT(1)
0018 #define  F_SDH30_AHB_INCR_4     BIT(0)
0019 
0020 #define F_SDH30_TUNING_SETTING  0x108
0021 #define  F_SDH30_CMD_CHK_DIS    BIT(16)
0022 
0023 #define F_SDH30_IO_CONTROL2     0x114
0024 #define  F_SDH30_CRES_O_DN      BIT(19)
0025 #define  F_SDH30_MSEL_O_1_8     BIT(18)
0026 
0027 #define F_SDH30_ESD_CONTROL     0x124
0028 #define  F_SDH30_EMMC_RST       BIT(1)
0029 #define  F_SDH30_CMD_DAT_DELAY  BIT(9)
0030 #define  F_SDH30_EMMC_HS200     BIT(24)
0031 
0032 #define F_SDH30_MIN_CLOCK       400000