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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
0004  *
0005  * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
0006  *
0007  */
0008 #include <linux/clk.h>
0009 #include <linux/iopoll.h>
0010 #include <linux/of.h>
0011 #include <linux/module.h>
0012 #include <linux/pm_runtime.h>
0013 #include <linux/property.h>
0014 #include <linux/regmap.h>
0015 #include <linux/sys_soc.h>
0016 
0017 #include "cqhci.h"
0018 #include "sdhci-pltfm.h"
0019 
0020 /* CTL_CFG Registers */
0021 #define CTL_CFG_2       0x14
0022 #define CTL_CFG_3       0x18
0023 
0024 #define SLOTTYPE_MASK       GENMASK(31, 30)
0025 #define SLOTTYPE_EMBEDDED   BIT(30)
0026 #define TUNINGFORSDR50_MASK BIT(13)
0027 
0028 /* PHY Registers */
0029 #define PHY_CTRL1   0x100
0030 #define PHY_CTRL2   0x104
0031 #define PHY_CTRL3   0x108
0032 #define PHY_CTRL4   0x10C
0033 #define PHY_CTRL5   0x110
0034 #define PHY_CTRL6   0x114
0035 #define PHY_STAT1   0x130
0036 #define PHY_STAT2   0x134
0037 
0038 #define IOMUX_ENABLE_SHIFT  31
0039 #define IOMUX_ENABLE_MASK   BIT(IOMUX_ENABLE_SHIFT)
0040 #define OTAPDLYENA_SHIFT    20
0041 #define OTAPDLYENA_MASK     BIT(OTAPDLYENA_SHIFT)
0042 #define OTAPDLYSEL_SHIFT    12
0043 #define OTAPDLYSEL_MASK     GENMASK(15, 12)
0044 #define STRBSEL_SHIFT       24
0045 #define STRBSEL_4BIT_MASK   GENMASK(27, 24)
0046 #define STRBSEL_8BIT_MASK   GENMASK(31, 24)
0047 #define SEL50_SHIFT     8
0048 #define SEL50_MASK      BIT(SEL50_SHIFT)
0049 #define SEL100_SHIFT        9
0050 #define SEL100_MASK     BIT(SEL100_SHIFT)
0051 #define FREQSEL_SHIFT       8
0052 #define FREQSEL_MASK        GENMASK(10, 8)
0053 #define CLKBUFSEL_SHIFT     0
0054 #define CLKBUFSEL_MASK      GENMASK(2, 0)
0055 #define DLL_TRIM_ICP_SHIFT  4
0056 #define DLL_TRIM_ICP_MASK   GENMASK(7, 4)
0057 #define DR_TY_SHIFT     20
0058 #define DR_TY_MASK      GENMASK(22, 20)
0059 #define ENDLL_SHIFT     1
0060 #define ENDLL_MASK      BIT(ENDLL_SHIFT)
0061 #define DLLRDY_SHIFT        0
0062 #define DLLRDY_MASK     BIT(DLLRDY_SHIFT)
0063 #define PDB_SHIFT       0
0064 #define PDB_MASK        BIT(PDB_SHIFT)
0065 #define CALDONE_SHIFT       1
0066 #define CALDONE_MASK        BIT(CALDONE_SHIFT)
0067 #define RETRIM_SHIFT        17
0068 #define RETRIM_MASK     BIT(RETRIM_SHIFT)
0069 #define SELDLYTXCLK_SHIFT   17
0070 #define SELDLYTXCLK_MASK    BIT(SELDLYTXCLK_SHIFT)
0071 #define SELDLYRXCLK_SHIFT   16
0072 #define SELDLYRXCLK_MASK    BIT(SELDLYRXCLK_SHIFT)
0073 #define ITAPDLYSEL_SHIFT    0
0074 #define ITAPDLYSEL_MASK     GENMASK(4, 0)
0075 #define ITAPDLYENA_SHIFT    8
0076 #define ITAPDLYENA_MASK     BIT(ITAPDLYENA_SHIFT)
0077 #define ITAPCHGWIN_SHIFT    9
0078 #define ITAPCHGWIN_MASK     BIT(ITAPCHGWIN_SHIFT)
0079 
0080 #define DRIVER_STRENGTH_50_OHM  0x0
0081 #define DRIVER_STRENGTH_33_OHM  0x1
0082 #define DRIVER_STRENGTH_66_OHM  0x2
0083 #define DRIVER_STRENGTH_100_OHM 0x3
0084 #define DRIVER_STRENGTH_40_OHM  0x4
0085 
0086 #define CLOCK_TOO_SLOW_HZ   50000000
0087 
0088 /* Command Queue Host Controller Interface Base address */
0089 #define SDHCI_AM654_CQE_BASE_ADDR 0x200
0090 
0091 static struct regmap_config sdhci_am654_regmap_config = {
0092     .reg_bits = 32,
0093     .val_bits = 32,
0094     .reg_stride = 4,
0095     .fast_io = true,
0096 };
0097 
0098 struct timing_data {
0099     const char *otap_binding;
0100     const char *itap_binding;
0101     u32 capability;
0102 };
0103 
0104 static const struct timing_data td[] = {
0105     [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
0106                    "ti,itap-del-sel-legacy",
0107                    0},
0108     [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
0109                    "ti,itap-del-sel-mmc-hs",
0110                    MMC_CAP_MMC_HIGHSPEED},
0111     [MMC_TIMING_SD_HS]  = {"ti,otap-del-sel-sd-hs",
0112                    "ti,itap-del-sel-sd-hs",
0113                    MMC_CAP_SD_HIGHSPEED},
0114     [MMC_TIMING_UHS_SDR12]  = {"ti,otap-del-sel-sdr12",
0115                    "ti,itap-del-sel-sdr12",
0116                    MMC_CAP_UHS_SDR12},
0117     [MMC_TIMING_UHS_SDR25]  = {"ti,otap-del-sel-sdr25",
0118                    "ti,itap-del-sel-sdr25",
0119                    MMC_CAP_UHS_SDR25},
0120     [MMC_TIMING_UHS_SDR50]  = {"ti,otap-del-sel-sdr50",
0121                    NULL,
0122                    MMC_CAP_UHS_SDR50},
0123     [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
0124                    NULL,
0125                    MMC_CAP_UHS_SDR104},
0126     [MMC_TIMING_UHS_DDR50]  = {"ti,otap-del-sel-ddr50",
0127                    NULL,
0128                    MMC_CAP_UHS_DDR50},
0129     [MMC_TIMING_MMC_DDR52]  = {"ti,otap-del-sel-ddr52",
0130                    "ti,itap-del-sel-ddr52",
0131                    MMC_CAP_DDR},
0132     [MMC_TIMING_MMC_HS200]  = {"ti,otap-del-sel-hs200",
0133                    NULL,
0134                    MMC_CAP2_HS200},
0135     [MMC_TIMING_MMC_HS400]  = {"ti,otap-del-sel-hs400",
0136                    NULL,
0137                    MMC_CAP2_HS400},
0138 };
0139 
0140 struct sdhci_am654_data {
0141     struct regmap *base;
0142     bool legacy_otapdly;
0143     int otap_del_sel[ARRAY_SIZE(td)];
0144     int itap_del_sel[ARRAY_SIZE(td)];
0145     int clkbuf_sel;
0146     int trm_icp;
0147     int drv_strength;
0148     int strb_sel;
0149     u32 flags;
0150     u32 quirks;
0151 
0152 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0)
0153 };
0154 
0155 struct sdhci_am654_driver_data {
0156     const struct sdhci_pltfm_data *pdata;
0157     u32 flags;
0158 #define IOMUX_PRESENT   (1 << 0)
0159 #define FREQSEL_2_BIT   (1 << 1)
0160 #define STRBSEL_4_BIT   (1 << 2)
0161 #define DLL_PRESENT (1 << 3)
0162 #define DLL_CALIB   (1 << 4)
0163 };
0164 
0165 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
0166 {
0167     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0168     struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
0169     int sel50, sel100, freqsel;
0170     u32 mask, val;
0171     int ret;
0172 
0173     /* Disable delay chain mode */
0174     regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
0175                SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
0176 
0177     if (sdhci_am654->flags & FREQSEL_2_BIT) {
0178         switch (clock) {
0179         case 200000000:
0180             sel50 = 0;
0181             sel100 = 0;
0182             break;
0183         case 100000000:
0184             sel50 = 0;
0185             sel100 = 1;
0186             break;
0187         default:
0188             sel50 = 1;
0189             sel100 = 0;
0190         }
0191 
0192         /* Configure PHY DLL frequency */
0193         mask = SEL50_MASK | SEL100_MASK;
0194         val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
0195         regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
0196 
0197     } else {
0198         switch (clock) {
0199         case 200000000:
0200             freqsel = 0x0;
0201             break;
0202         default:
0203             freqsel = 0x4;
0204         }
0205 
0206         regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
0207                    freqsel << FREQSEL_SHIFT);
0208     }
0209     /* Configure DLL TRIM */
0210     mask = DLL_TRIM_ICP_MASK;
0211     val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
0212 
0213     /* Configure DLL driver strength */
0214     mask |= DR_TY_MASK;
0215     val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
0216     regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
0217 
0218     /* Enable DLL */
0219     regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
0220                0x1 << ENDLL_SHIFT);
0221     /*
0222      * Poll for DLL ready. Use a one second timeout.
0223      * Works in all experiments done so far
0224      */
0225     ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
0226                        val & DLLRDY_MASK, 1000, 1000000);
0227     if (ret) {
0228         dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
0229         return;
0230     }
0231 }
0232 
0233 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654,
0234                       u32 itapdly)
0235 {
0236     /* Set ITAPCHGWIN before writing to ITAPDLY */
0237     regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
0238                1 << ITAPCHGWIN_SHIFT);
0239     regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
0240                itapdly << ITAPDLYSEL_SHIFT);
0241     regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
0242 }
0243 
0244 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654,
0245                       unsigned char timing)
0246 {
0247     u32 mask, val;
0248 
0249     regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
0250 
0251     val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
0252     mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
0253     regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
0254 
0255     sdhci_am654_write_itapdly(sdhci_am654,
0256                   sdhci_am654->itap_del_sel[timing]);
0257 }
0258 
0259 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
0260 {
0261     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0262     struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
0263     unsigned char timing = host->mmc->ios.timing;
0264     u32 otap_del_sel;
0265     u32 otap_del_ena;
0266     u32 mask, val;
0267 
0268     regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
0269 
0270     sdhci_set_clock(host, clock);
0271 
0272     /* Setup DLL Output TAP delay */
0273     if (sdhci_am654->legacy_otapdly)
0274         otap_del_sel = sdhci_am654->otap_del_sel[0];
0275     else
0276         otap_del_sel = sdhci_am654->otap_del_sel[timing];
0277 
0278     otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0;
0279 
0280     mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
0281     val = (otap_del_ena << OTAPDLYENA_SHIFT) |
0282           (otap_del_sel << OTAPDLYSEL_SHIFT);
0283 
0284     /* Write to STRBSEL for HS400 speed mode */
0285     if (timing == MMC_TIMING_MMC_HS400) {
0286         if (sdhci_am654->flags & STRBSEL_4_BIT)
0287             mask |= STRBSEL_4BIT_MASK;
0288         else
0289             mask |= STRBSEL_8BIT_MASK;
0290 
0291         val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
0292     }
0293 
0294     regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
0295 
0296     if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ)
0297         sdhci_am654_setup_dll(host, clock);
0298     else
0299         sdhci_am654_setup_delay_chain(sdhci_am654, timing);
0300 
0301     regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
0302                sdhci_am654->clkbuf_sel);
0303 }
0304 
0305 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
0306                        unsigned int clock)
0307 {
0308     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0309     struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
0310     unsigned char timing = host->mmc->ios.timing;
0311     u32 otap_del_sel;
0312     u32 mask, val;
0313 
0314     /* Setup DLL Output TAP delay */
0315     if (sdhci_am654->legacy_otapdly)
0316         otap_del_sel = sdhci_am654->otap_del_sel[0];
0317     else
0318         otap_del_sel = sdhci_am654->otap_del_sel[timing];
0319 
0320     mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
0321     val = (0x1 << OTAPDLYENA_SHIFT) |
0322           (otap_del_sel << OTAPDLYSEL_SHIFT);
0323     regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
0324 
0325     regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
0326                sdhci_am654->clkbuf_sel);
0327 
0328     sdhci_set_clock(host, clock);
0329 }
0330 
0331 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg)
0332 {
0333     writeb(val, host->ioaddr + reg);
0334     usleep_range(1000, 10000);
0335     return readb(host->ioaddr + reg);
0336 }
0337 
0338 #define MAX_POWER_ON_TIMEOUT    1500000 /* us */
0339 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
0340 {
0341     unsigned char timing = host->mmc->ios.timing;
0342     u8 pwr;
0343     int ret;
0344 
0345     if (reg == SDHCI_HOST_CONTROL) {
0346         switch (timing) {
0347         /*
0348          * According to the data manual, HISPD bit
0349          * should not be set in these speed modes.
0350          */
0351         case MMC_TIMING_SD_HS:
0352         case MMC_TIMING_MMC_HS:
0353         case MMC_TIMING_UHS_SDR12:
0354         case MMC_TIMING_UHS_SDR25:
0355             val &= ~SDHCI_CTRL_HISPD;
0356         }
0357     }
0358 
0359     writeb(val, host->ioaddr + reg);
0360     if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
0361         /*
0362          * Power on will not happen until the card detect debounce
0363          * timer expires. Wait at least 1.5 seconds for the power on
0364          * bit to be set
0365          */
0366         ret = read_poll_timeout(sdhci_am654_write_power_on, pwr,
0367                     pwr & SDHCI_POWER_ON, 0,
0368                     MAX_POWER_ON_TIMEOUT, false, host, val,
0369                     reg);
0370         if (ret)
0371             dev_warn(mmc_dev(host->mmc), "Power on failed\n");
0372     }
0373 }
0374 
0375 static void sdhci_am654_reset(struct sdhci_host *host, u8 mask)
0376 {
0377     u8 ctrl;
0378     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0379     struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
0380 
0381     sdhci_reset(host, mask);
0382 
0383     if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {
0384         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
0385         ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
0386         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
0387     }
0388 }
0389 
0390 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
0391 {
0392     struct sdhci_host *host = mmc_priv(mmc);
0393     int err = sdhci_execute_tuning(mmc, opcode);
0394 
0395     if (err)
0396         return err;
0397     /*
0398      * Tuning data remains in the buffer after tuning.
0399      * Do a command and data reset to get rid of it
0400      */
0401     sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
0402 
0403     return 0;
0404 }
0405 
0406 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
0407 {
0408     int cmd_error = 0;
0409     int data_error = 0;
0410 
0411     if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
0412         return intmask;
0413 
0414     cqhci_irq(host->mmc, intmask, cmd_error, data_error);
0415 
0416     return 0;
0417 }
0418 
0419 #define ITAP_MAX    32
0420 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
0421                            u32 opcode)
0422 {
0423     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0424     struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
0425     int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
0426     u32 itap;
0427 
0428     /* Enable ITAPDLY */
0429     regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
0430                1 << ITAPDLYENA_SHIFT);
0431 
0432     for (itap = 0; itap < ITAP_MAX; itap++) {
0433         sdhci_am654_write_itapdly(sdhci_am654, itap);
0434 
0435         cur_val = !mmc_send_tuning(host->mmc, opcode, NULL);
0436         if (cur_val && !prev_val)
0437             pass_window = itap;
0438 
0439         if (!cur_val)
0440             fail_len++;
0441 
0442         prev_val = cur_val;
0443     }
0444     /*
0445      * Having determined the length of the failing window and start of
0446      * the passing window calculate the length of the passing window and
0447      * set the final value halfway through it considering the range as a
0448      * circular buffer
0449      */
0450     pass_len = ITAP_MAX - fail_len;
0451     itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
0452     sdhci_am654_write_itapdly(sdhci_am654, itap);
0453 
0454     return 0;
0455 }
0456 
0457 static struct sdhci_ops sdhci_am654_ops = {
0458     .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
0459     .get_max_clock = sdhci_pltfm_clk_get_max_clock,
0460     .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
0461     .set_uhs_signaling = sdhci_set_uhs_signaling,
0462     .set_bus_width = sdhci_set_bus_width,
0463     .set_power = sdhci_set_power_and_bus_voltage,
0464     .set_clock = sdhci_am654_set_clock,
0465     .write_b = sdhci_am654_write_b,
0466     .irq = sdhci_am654_cqhci_irq,
0467     .reset = sdhci_reset,
0468 };
0469 
0470 static const struct sdhci_pltfm_data sdhci_am654_pdata = {
0471     .ops = &sdhci_am654_ops,
0472     .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
0473     .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
0474 };
0475 
0476 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = {
0477     .pdata = &sdhci_am654_pdata,
0478     .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT |
0479          DLL_CALIB,
0480 };
0481 
0482 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
0483     .pdata = &sdhci_am654_pdata,
0484     .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
0485 };
0486 
0487 static struct sdhci_ops sdhci_j721e_8bit_ops = {
0488     .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
0489     .get_max_clock = sdhci_pltfm_clk_get_max_clock,
0490     .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
0491     .set_uhs_signaling = sdhci_set_uhs_signaling,
0492     .set_bus_width = sdhci_set_bus_width,
0493     .set_power = sdhci_set_power_and_bus_voltage,
0494     .set_clock = sdhci_am654_set_clock,
0495     .write_b = sdhci_am654_write_b,
0496     .irq = sdhci_am654_cqhci_irq,
0497     .reset = sdhci_reset,
0498 };
0499 
0500 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
0501     .ops = &sdhci_j721e_8bit_ops,
0502     .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
0503     .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
0504 };
0505 
0506 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
0507     .pdata = &sdhci_j721e_8bit_pdata,
0508     .flags = DLL_PRESENT | DLL_CALIB,
0509 };
0510 
0511 static struct sdhci_ops sdhci_j721e_4bit_ops = {
0512     .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
0513     .get_max_clock = sdhci_pltfm_clk_get_max_clock,
0514     .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
0515     .set_uhs_signaling = sdhci_set_uhs_signaling,
0516     .set_bus_width = sdhci_set_bus_width,
0517     .set_power = sdhci_set_power_and_bus_voltage,
0518     .set_clock = sdhci_j721e_4bit_set_clock,
0519     .write_b = sdhci_am654_write_b,
0520     .irq = sdhci_am654_cqhci_irq,
0521     .reset = sdhci_am654_reset,
0522 };
0523 
0524 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
0525     .ops = &sdhci_j721e_4bit_ops,
0526     .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
0527     .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
0528 };
0529 
0530 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
0531     .pdata = &sdhci_j721e_4bit_pdata,
0532     .flags = IOMUX_PRESENT,
0533 };
0534 
0535 static const struct soc_device_attribute sdhci_am654_devices[] = {
0536     { .family = "AM65X",
0537       .revision = "SR1.0",
0538       .data = &sdhci_am654_sr1_drvdata
0539     },
0540     {/* sentinel */}
0541 };
0542 
0543 static void sdhci_am654_dumpregs(struct mmc_host *mmc)
0544 {
0545     sdhci_dumpregs(mmc_priv(mmc));
0546 }
0547 
0548 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
0549     .enable     = sdhci_cqe_enable,
0550     .disable    = sdhci_cqe_disable,
0551     .dumpregs   = sdhci_am654_dumpregs,
0552 };
0553 
0554 static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
0555 {
0556     struct cqhci_host *cq_host;
0557     int ret;
0558 
0559     cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host),
0560                    GFP_KERNEL);
0561     if (!cq_host)
0562         return -ENOMEM;
0563 
0564     cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
0565     cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
0566     cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
0567     cq_host->ops = &sdhci_am654_cqhci_ops;
0568 
0569     host->mmc->caps2 |= MMC_CAP2_CQE;
0570 
0571     ret = cqhci_init(cq_host, host->mmc, 1);
0572 
0573     return ret;
0574 }
0575 
0576 static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
0577                       struct sdhci_am654_data *sdhci_am654)
0578 {
0579     struct device *dev = mmc_dev(host->mmc);
0580     int i;
0581     int ret;
0582 
0583     ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding,
0584                  &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]);
0585     if (ret) {
0586         /*
0587          * ti,otap-del-sel-legacy is mandatory, look for old binding
0588          * if not found.
0589          */
0590         ret = device_property_read_u32(dev, "ti,otap-del-sel",
0591                            &sdhci_am654->otap_del_sel[0]);
0592         if (ret) {
0593             dev_err(dev, "Couldn't find otap-del-sel\n");
0594 
0595             return ret;
0596         }
0597 
0598         dev_info(dev, "Using legacy binding ti,otap-del-sel\n");
0599         sdhci_am654->legacy_otapdly = true;
0600 
0601         return 0;
0602     }
0603 
0604     for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) {
0605 
0606         ret = device_property_read_u32(dev, td[i].otap_binding,
0607                            &sdhci_am654->otap_del_sel[i]);
0608         if (ret) {
0609             dev_dbg(dev, "Couldn't find %s\n",
0610                 td[i].otap_binding);
0611             /*
0612              * Remove the corresponding capability
0613              * if an otap-del-sel value is not found
0614              */
0615             if (i <= MMC_TIMING_MMC_DDR52)
0616                 host->mmc->caps &= ~td[i].capability;
0617             else
0618                 host->mmc->caps2 &= ~td[i].capability;
0619         }
0620 
0621         if (td[i].itap_binding)
0622             device_property_read_u32(dev, td[i].itap_binding,
0623                          &sdhci_am654->itap_del_sel[i]);
0624     }
0625 
0626     return 0;
0627 }
0628 
0629 static int sdhci_am654_init(struct sdhci_host *host)
0630 {
0631     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0632     struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
0633     u32 ctl_cfg_2 = 0;
0634     u32 mask;
0635     u32 val;
0636     int ret;
0637 
0638     /* Reset OTAP to default value */
0639     mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
0640     regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
0641 
0642     if (sdhci_am654->flags & DLL_CALIB) {
0643         regmap_read(sdhci_am654->base, PHY_STAT1, &val);
0644         if (~val & CALDONE_MASK) {
0645             /* Calibrate IO lines */
0646             regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
0647                        PDB_MASK, PDB_MASK);
0648             ret = regmap_read_poll_timeout(sdhci_am654->base,
0649                                PHY_STAT1, val,
0650                                val & CALDONE_MASK,
0651                                1, 20);
0652             if (ret)
0653                 return ret;
0654         }
0655     }
0656 
0657     /* Enable pins by setting IO mux to 0 */
0658     if (sdhci_am654->flags & IOMUX_PRESENT)
0659         regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
0660                    IOMUX_ENABLE_MASK, 0);
0661 
0662     /* Set slot type based on SD or eMMC */
0663     if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
0664         ctl_cfg_2 = SLOTTYPE_EMBEDDED;
0665 
0666     regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
0667                ctl_cfg_2);
0668 
0669     /* Enable tuning for SDR50 */
0670     regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
0671                TUNINGFORSDR50_MASK);
0672 
0673     ret = sdhci_setup_host(host);
0674     if (ret)
0675         return ret;
0676 
0677     ret = sdhci_am654_cqe_add_host(host);
0678     if (ret)
0679         goto err_cleanup_host;
0680 
0681     ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
0682     if (ret)
0683         goto err_cleanup_host;
0684 
0685     ret = __sdhci_add_host(host);
0686     if (ret)
0687         goto err_cleanup_host;
0688 
0689     return 0;
0690 
0691 err_cleanup_host:
0692     sdhci_cleanup_host(host);
0693     return ret;
0694 }
0695 
0696 static int sdhci_am654_get_of_property(struct platform_device *pdev,
0697                     struct sdhci_am654_data *sdhci_am654)
0698 {
0699     struct device *dev = &pdev->dev;
0700     int drv_strength;
0701     int ret;
0702 
0703     if (sdhci_am654->flags & DLL_PRESENT) {
0704         ret = device_property_read_u32(dev, "ti,trm-icp",
0705                            &sdhci_am654->trm_icp);
0706         if (ret)
0707             return ret;
0708 
0709         ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
0710                            &drv_strength);
0711         if (ret)
0712             return ret;
0713 
0714         switch (drv_strength) {
0715         case 50:
0716             sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
0717             break;
0718         case 33:
0719             sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
0720             break;
0721         case 66:
0722             sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
0723             break;
0724         case 100:
0725             sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
0726             break;
0727         case 40:
0728             sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
0729             break;
0730         default:
0731             dev_err(dev, "Invalid driver strength\n");
0732             return -EINVAL;
0733         }
0734     }
0735 
0736     device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
0737     device_property_read_u32(dev, "ti,clkbuf-sel",
0738                  &sdhci_am654->clkbuf_sel);
0739 
0740     if (device_property_read_bool(dev, "ti,fails-without-test-cd"))
0741         sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST;
0742 
0743     sdhci_get_of_property(pdev);
0744 
0745     return 0;
0746 }
0747 
0748 static const struct of_device_id sdhci_am654_of_match[] = {
0749     {
0750         .compatible = "ti,am654-sdhci-5.1",
0751         .data = &sdhci_am654_drvdata,
0752     },
0753     {
0754         .compatible = "ti,j721e-sdhci-8bit",
0755         .data = &sdhci_j721e_8bit_drvdata,
0756     },
0757     {
0758         .compatible = "ti,j721e-sdhci-4bit",
0759         .data = &sdhci_j721e_4bit_drvdata,
0760     },
0761     {
0762         .compatible = "ti,am64-sdhci-8bit",
0763         .data = &sdhci_j721e_8bit_drvdata,
0764     },
0765     {
0766         .compatible = "ti,am64-sdhci-4bit",
0767         .data = &sdhci_j721e_4bit_drvdata,
0768     },
0769     {
0770         .compatible = "ti,am62-sdhci",
0771         .data = &sdhci_j721e_4bit_drvdata,
0772     },
0773     { /* sentinel */ }
0774 };
0775 MODULE_DEVICE_TABLE(of, sdhci_am654_of_match);
0776 
0777 static int sdhci_am654_probe(struct platform_device *pdev)
0778 {
0779     const struct sdhci_am654_driver_data *drvdata;
0780     const struct soc_device_attribute *soc;
0781     struct sdhci_pltfm_host *pltfm_host;
0782     struct sdhci_am654_data *sdhci_am654;
0783     const struct of_device_id *match;
0784     struct sdhci_host *host;
0785     struct clk *clk_xin;
0786     struct device *dev = &pdev->dev;
0787     void __iomem *base;
0788     int ret;
0789 
0790     match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
0791     drvdata = match->data;
0792 
0793     /* Update drvdata based on SoC revision */
0794     soc = soc_device_match(sdhci_am654_devices);
0795     if (soc && soc->data)
0796         drvdata = soc->data;
0797 
0798     host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
0799     if (IS_ERR(host))
0800         return PTR_ERR(host);
0801 
0802     pltfm_host = sdhci_priv(host);
0803     sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
0804     sdhci_am654->flags = drvdata->flags;
0805 
0806     clk_xin = devm_clk_get(dev, "clk_xin");
0807     if (IS_ERR(clk_xin)) {
0808         dev_err(dev, "clk_xin clock not found.\n");
0809         ret = PTR_ERR(clk_xin);
0810         goto err_pltfm_free;
0811     }
0812 
0813     pltfm_host->clk = clk_xin;
0814 
0815     /* Clocks are enabled using pm_runtime */
0816     pm_runtime_enable(dev);
0817     ret = pm_runtime_resume_and_get(dev);
0818     if (ret)
0819         goto pm_runtime_disable;
0820 
0821     base = devm_platform_ioremap_resource(pdev, 1);
0822     if (IS_ERR(base)) {
0823         ret = PTR_ERR(base);
0824         goto pm_runtime_put;
0825     }
0826 
0827     sdhci_am654->base = devm_regmap_init_mmio(dev, base,
0828                           &sdhci_am654_regmap_config);
0829     if (IS_ERR(sdhci_am654->base)) {
0830         dev_err(dev, "Failed to initialize regmap\n");
0831         ret = PTR_ERR(sdhci_am654->base);
0832         goto pm_runtime_put;
0833     }
0834 
0835     ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
0836     if (ret)
0837         goto pm_runtime_put;
0838 
0839     ret = mmc_of_parse(host->mmc);
0840     if (ret) {
0841         dev_err(dev, "parsing dt failed (%d)\n", ret);
0842         goto pm_runtime_put;
0843     }
0844 
0845     host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
0846 
0847     ret = sdhci_am654_init(host);
0848     if (ret)
0849         goto pm_runtime_put;
0850 
0851     return 0;
0852 
0853 pm_runtime_put:
0854     pm_runtime_put_sync(dev);
0855 pm_runtime_disable:
0856     pm_runtime_disable(dev);
0857 err_pltfm_free:
0858     sdhci_pltfm_free(pdev);
0859     return ret;
0860 }
0861 
0862 static int sdhci_am654_remove(struct platform_device *pdev)
0863 {
0864     struct sdhci_host *host = platform_get_drvdata(pdev);
0865     int ret;
0866 
0867     sdhci_remove_host(host, true);
0868     ret = pm_runtime_put_sync(&pdev->dev);
0869     if (ret < 0)
0870         return ret;
0871 
0872     pm_runtime_disable(&pdev->dev);
0873     sdhci_pltfm_free(pdev);
0874 
0875     return 0;
0876 }
0877 
0878 static struct platform_driver sdhci_am654_driver = {
0879     .driver = {
0880         .name = "sdhci-am654",
0881         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0882         .of_match_table = sdhci_am654_of_match,
0883     },
0884     .probe = sdhci_am654_probe,
0885     .remove = sdhci_am654_remove,
0886 };
0887 
0888 module_platform_driver(sdhci_am654_driver);
0889 
0890 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
0891 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
0892 MODULE_LICENSE("GPL");
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