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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
0004  *
0005  * Header file for Host Controller registers and I/O accessors.
0006  *
0007  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
0008  */
0009 #ifndef __SDHCI_HW_H
0010 #define __SDHCI_HW_H
0011 
0012 #include <linux/bits.h>
0013 #include <linux/scatterlist.h>
0014 #include <linux/compiler.h>
0015 #include <linux/types.h>
0016 #include <linux/io.h>
0017 #include <linux/leds.h>
0018 #include <linux/interrupt.h>
0019 
0020 #include <linux/mmc/host.h>
0021 
0022 /*
0023  * Controller registers
0024  */
0025 
0026 #define SDHCI_DMA_ADDRESS   0x00
0027 #define SDHCI_ARGUMENT2     SDHCI_DMA_ADDRESS
0028 #define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS
0029 
0030 #define SDHCI_BLOCK_SIZE    0x04
0031 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
0032 
0033 #define SDHCI_BLOCK_COUNT   0x06
0034 
0035 #define SDHCI_ARGUMENT      0x08
0036 
0037 #define SDHCI_TRANSFER_MODE 0x0C
0038 #define  SDHCI_TRNS_DMA     0x01
0039 #define  SDHCI_TRNS_BLK_CNT_EN  0x02
0040 #define  SDHCI_TRNS_AUTO_CMD12  0x04
0041 #define  SDHCI_TRNS_AUTO_CMD23  0x08
0042 #define  SDHCI_TRNS_AUTO_SEL    0x0C
0043 #define  SDHCI_TRNS_READ    0x10
0044 #define  SDHCI_TRNS_MULTI   0x20
0045 
0046 #define SDHCI_COMMAND       0x0E
0047 #define  SDHCI_CMD_RESP_MASK    0x03
0048 #define  SDHCI_CMD_CRC      0x08
0049 #define  SDHCI_CMD_INDEX    0x10
0050 #define  SDHCI_CMD_DATA     0x20
0051 #define  SDHCI_CMD_ABORTCMD 0xC0
0052 
0053 #define  SDHCI_CMD_RESP_NONE    0x00
0054 #define  SDHCI_CMD_RESP_LONG    0x01
0055 #define  SDHCI_CMD_RESP_SHORT   0x02
0056 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
0057 
0058 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
0059 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
0060 
0061 #define SDHCI_RESPONSE      0x10
0062 
0063 #define SDHCI_BUFFER        0x20
0064 
0065 #define SDHCI_PRESENT_STATE 0x24
0066 #define  SDHCI_CMD_INHIBIT  0x00000001
0067 #define  SDHCI_DATA_INHIBIT 0x00000002
0068 #define  SDHCI_DOING_WRITE  0x00000100
0069 #define  SDHCI_DOING_READ   0x00000200
0070 #define  SDHCI_SPACE_AVAILABLE  0x00000400
0071 #define  SDHCI_DATA_AVAILABLE   0x00000800
0072 #define  SDHCI_CARD_PRESENT 0x00010000
0073 #define   SDHCI_CARD_PRES_SHIFT 16
0074 #define  SDHCI_CD_STABLE    0x00020000
0075 #define  SDHCI_CD_LVL       0x00040000
0076 #define   SDHCI_CD_LVL_SHIFT    18
0077 #define  SDHCI_WRITE_PROTECT    0x00080000
0078 #define  SDHCI_DATA_LVL_MASK    0x00F00000
0079 #define   SDHCI_DATA_LVL_SHIFT  20
0080 #define   SDHCI_DATA_0_LVL_MASK 0x00100000
0081 #define  SDHCI_CMD_LVL      0x01000000
0082 
0083 #define SDHCI_HOST_CONTROL  0x28
0084 #define  SDHCI_CTRL_LED     0x01
0085 #define  SDHCI_CTRL_4BITBUS 0x02
0086 #define  SDHCI_CTRL_HISPD   0x04
0087 #define  SDHCI_CTRL_DMA_MASK    0x18
0088 #define   SDHCI_CTRL_SDMA   0x00
0089 #define   SDHCI_CTRL_ADMA1  0x08
0090 #define   SDHCI_CTRL_ADMA32 0x10
0091 #define   SDHCI_CTRL_ADMA64 0x18
0092 #define   SDHCI_CTRL_ADMA3  0x18
0093 #define  SDHCI_CTRL_8BITBUS 0x20
0094 #define  SDHCI_CTRL_CDTEST_INS  0x40
0095 #define  SDHCI_CTRL_CDTEST_EN   0x80
0096 
0097 #define SDHCI_POWER_CONTROL 0x29
0098 #define  SDHCI_POWER_ON     0x01
0099 #define  SDHCI_POWER_180    0x0A
0100 #define  SDHCI_POWER_300    0x0C
0101 #define  SDHCI_POWER_330    0x0E
0102 
0103 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
0104 
0105 #define SDHCI_WAKE_UP_CONTROL   0x2B
0106 #define  SDHCI_WAKE_ON_INT  0x01
0107 #define  SDHCI_WAKE_ON_INSERT   0x02
0108 #define  SDHCI_WAKE_ON_REMOVE   0x04
0109 
0110 #define SDHCI_CLOCK_CONTROL 0x2C
0111 #define  SDHCI_DIVIDER_SHIFT    8
0112 #define  SDHCI_DIVIDER_HI_SHIFT 6
0113 #define  SDHCI_DIV_MASK 0xFF
0114 #define  SDHCI_DIV_MASK_LEN 8
0115 #define  SDHCI_DIV_HI_MASK  0x300
0116 #define  SDHCI_PROG_CLOCK_MODE  0x0020
0117 #define  SDHCI_CLOCK_CARD_EN    0x0004
0118 #define  SDHCI_CLOCK_PLL_EN 0x0008
0119 #define  SDHCI_CLOCK_INT_STABLE 0x0002
0120 #define  SDHCI_CLOCK_INT_EN 0x0001
0121 
0122 #define SDHCI_TIMEOUT_CONTROL   0x2E
0123 
0124 #define SDHCI_SOFTWARE_RESET    0x2F
0125 #define  SDHCI_RESET_ALL    0x01
0126 #define  SDHCI_RESET_CMD    0x02
0127 #define  SDHCI_RESET_DATA   0x04
0128 
0129 #define SDHCI_INT_STATUS    0x30
0130 #define SDHCI_INT_ENABLE    0x34
0131 #define SDHCI_SIGNAL_ENABLE 0x38
0132 #define  SDHCI_INT_RESPONSE 0x00000001
0133 #define  SDHCI_INT_DATA_END 0x00000002
0134 #define  SDHCI_INT_BLK_GAP  0x00000004
0135 #define  SDHCI_INT_DMA_END  0x00000008
0136 #define  SDHCI_INT_SPACE_AVAIL  0x00000010
0137 #define  SDHCI_INT_DATA_AVAIL   0x00000020
0138 #define  SDHCI_INT_CARD_INSERT  0x00000040
0139 #define  SDHCI_INT_CARD_REMOVE  0x00000080
0140 #define  SDHCI_INT_CARD_INT 0x00000100
0141 #define  SDHCI_INT_RETUNE   0x00001000
0142 #define  SDHCI_INT_CQE      0x00004000
0143 #define  SDHCI_INT_ERROR    0x00008000
0144 #define  SDHCI_INT_TIMEOUT  0x00010000
0145 #define  SDHCI_INT_CRC      0x00020000
0146 #define  SDHCI_INT_END_BIT  0x00040000
0147 #define  SDHCI_INT_INDEX    0x00080000
0148 #define  SDHCI_INT_DATA_TIMEOUT 0x00100000
0149 #define  SDHCI_INT_DATA_CRC 0x00200000
0150 #define  SDHCI_INT_DATA_END_BIT 0x00400000
0151 #define  SDHCI_INT_BUS_POWER    0x00800000
0152 #define  SDHCI_INT_AUTO_CMD_ERR 0x01000000
0153 #define  SDHCI_INT_ADMA_ERROR   0x02000000
0154 
0155 #define  SDHCI_INT_NORMAL_MASK  0x00007FFF
0156 #define  SDHCI_INT_ERROR_MASK   0xFFFF8000
0157 
0158 #define  SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
0159         SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \
0160         SDHCI_INT_AUTO_CMD_ERR)
0161 #define  SDHCI_INT_DATA_MASK    (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
0162         SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
0163         SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
0164         SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
0165         SDHCI_INT_BLK_GAP)
0166 #define SDHCI_INT_ALL_MASK  ((unsigned int)-1)
0167 
0168 #define SDHCI_CQE_INT_ERR_MASK ( \
0169     SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \
0170     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \
0171     SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)
0172 
0173 #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE)
0174 
0175 #define SDHCI_AUTO_CMD_STATUS   0x3C
0176 #define  SDHCI_AUTO_CMD_TIMEOUT 0x00000002
0177 #define  SDHCI_AUTO_CMD_CRC 0x00000004
0178 #define  SDHCI_AUTO_CMD_END_BIT 0x00000008
0179 #define  SDHCI_AUTO_CMD_INDEX   0x00000010
0180 
0181 #define SDHCI_HOST_CONTROL2     0x3E
0182 #define  SDHCI_CTRL_UHS_MASK        0x0007
0183 #define   SDHCI_CTRL_UHS_SDR12      0x0000
0184 #define   SDHCI_CTRL_UHS_SDR25      0x0001
0185 #define   SDHCI_CTRL_UHS_SDR50      0x0002
0186 #define   SDHCI_CTRL_UHS_SDR104     0x0003
0187 #define   SDHCI_CTRL_UHS_DDR50      0x0004
0188 #define   SDHCI_CTRL_HS400      0x0005 /* Non-standard */
0189 #define  SDHCI_CTRL_VDD_180     0x0008
0190 #define  SDHCI_CTRL_DRV_TYPE_MASK   0x0030
0191 #define   SDHCI_CTRL_DRV_TYPE_B     0x0000
0192 #define   SDHCI_CTRL_DRV_TYPE_A     0x0010
0193 #define   SDHCI_CTRL_DRV_TYPE_C     0x0020
0194 #define   SDHCI_CTRL_DRV_TYPE_D     0x0030
0195 #define  SDHCI_CTRL_EXEC_TUNING     0x0040
0196 #define  SDHCI_CTRL_TUNED_CLK       0x0080
0197 #define  SDHCI_CMD23_ENABLE     0x0800
0198 #define  SDHCI_CTRL_V4_MODE     0x1000
0199 #define  SDHCI_CTRL_64BIT_ADDR      0x2000
0200 #define  SDHCI_CTRL_PRESET_VAL_ENABLE   0x8000
0201 
0202 #define SDHCI_CAPABILITIES  0x40
0203 #define  SDHCI_TIMEOUT_CLK_MASK     GENMASK(5, 0)
0204 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
0205 #define  SDHCI_TIMEOUT_CLK_UNIT 0x00000080
0206 #define  SDHCI_CLOCK_BASE_MASK      GENMASK(13, 8)
0207 #define  SDHCI_CLOCK_BASE_SHIFT 8
0208 #define  SDHCI_CLOCK_V3_BASE_MASK   GENMASK(15, 8)
0209 #define  SDHCI_MAX_BLOCK_MASK   0x00030000
0210 #define  SDHCI_MAX_BLOCK_SHIFT  16
0211 #define  SDHCI_CAN_DO_8BIT  0x00040000
0212 #define  SDHCI_CAN_DO_ADMA2 0x00080000
0213 #define  SDHCI_CAN_DO_ADMA1 0x00100000
0214 #define  SDHCI_CAN_DO_HISPD 0x00200000
0215 #define  SDHCI_CAN_DO_SDMA  0x00400000
0216 #define  SDHCI_CAN_DO_SUSPEND   0x00800000
0217 #define  SDHCI_CAN_VDD_330  0x01000000
0218 #define  SDHCI_CAN_VDD_300  0x02000000
0219 #define  SDHCI_CAN_VDD_180  0x04000000
0220 #define  SDHCI_CAN_64BIT_V4 0x08000000
0221 #define  SDHCI_CAN_64BIT    0x10000000
0222 
0223 #define SDHCI_CAPABILITIES_1    0x44
0224 #define  SDHCI_SUPPORT_SDR50    0x00000001
0225 #define  SDHCI_SUPPORT_SDR104   0x00000002
0226 #define  SDHCI_SUPPORT_DDR50    0x00000004
0227 #define  SDHCI_DRIVER_TYPE_A    0x00000010
0228 #define  SDHCI_DRIVER_TYPE_C    0x00000020
0229 #define  SDHCI_DRIVER_TYPE_D    0x00000040
0230 #define  SDHCI_RETUNING_TIMER_COUNT_MASK    GENMASK(11, 8)
0231 #define  SDHCI_USE_SDR50_TUNING         0x00002000
0232 #define  SDHCI_RETUNING_MODE_MASK       GENMASK(15, 14)
0233 #define  SDHCI_CLOCK_MUL_MASK           GENMASK(23, 16)
0234 #define  SDHCI_CAN_DO_ADMA3 0x08000000
0235 #define  SDHCI_SUPPORT_HS400    0x80000000 /* Non-standard */
0236 
0237 #define SDHCI_MAX_CURRENT       0x48
0238 #define  SDHCI_MAX_CURRENT_LIMIT    GENMASK(7, 0)
0239 #define  SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0)
0240 #define  SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8)
0241 #define  SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16)
0242 #define   SDHCI_MAX_CURRENT_MULTIPLIER  4
0243 
0244 /* 4C-4F reserved for more max current */
0245 
0246 #define SDHCI_SET_ACMD12_ERROR  0x50
0247 #define SDHCI_SET_INT_ERROR 0x52
0248 
0249 #define SDHCI_ADMA_ERROR    0x54
0250 
0251 /* 55-57 reserved */
0252 
0253 #define SDHCI_ADMA_ADDRESS  0x58
0254 #define SDHCI_ADMA_ADDRESS_HI   0x5C
0255 
0256 /* 60-FB reserved */
0257 
0258 #define SDHCI_PRESET_FOR_HIGH_SPEED 0x64
0259 #define SDHCI_PRESET_FOR_SDR12 0x66
0260 #define SDHCI_PRESET_FOR_SDR25 0x68
0261 #define SDHCI_PRESET_FOR_SDR50 0x6A
0262 #define SDHCI_PRESET_FOR_SDR104        0x6C
0263 #define SDHCI_PRESET_FOR_DDR50 0x6E
0264 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
0265 #define SDHCI_PRESET_DRV_MASK       GENMASK(15, 14)
0266 #define SDHCI_PRESET_CLKGEN_SEL     BIT(10)
0267 #define SDHCI_PRESET_SDCLK_FREQ_MASK    GENMASK(9, 0)
0268 
0269 #define SDHCI_SLOT_INT_STATUS   0xFC
0270 
0271 #define SDHCI_HOST_VERSION  0xFE
0272 #define  SDHCI_VENDOR_VER_MASK  0xFF00
0273 #define  SDHCI_VENDOR_VER_SHIFT 8
0274 #define  SDHCI_SPEC_VER_MASK    0x00FF
0275 #define  SDHCI_SPEC_VER_SHIFT   0
0276 #define   SDHCI_SPEC_100    0
0277 #define   SDHCI_SPEC_200    1
0278 #define   SDHCI_SPEC_300    2
0279 #define   SDHCI_SPEC_400    3
0280 #define   SDHCI_SPEC_410    4
0281 #define   SDHCI_SPEC_420    5
0282 
0283 /*
0284  * End of controller registers.
0285  */
0286 
0287 #define SDHCI_MAX_DIV_SPEC_200  256
0288 #define SDHCI_MAX_DIV_SPEC_300  2046
0289 
0290 /*
0291  * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
0292  */
0293 #define SDHCI_DEFAULT_BOUNDARY_SIZE  (512 * 1024)
0294 #define SDHCI_DEFAULT_BOUNDARY_ARG   (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
0295 
0296 /* ADMA2 32-bit DMA descriptor size */
0297 #define SDHCI_ADMA2_32_DESC_SZ  8
0298 
0299 /* ADMA2 32-bit descriptor */
0300 struct sdhci_adma2_32_desc {
0301     __le16  cmd;
0302     __le16  len;
0303     __le32  addr;
0304 }  __packed __aligned(4);
0305 
0306 /* ADMA2 data alignment */
0307 #define SDHCI_ADMA2_ALIGN   4
0308 #define SDHCI_ADMA2_MASK    (SDHCI_ADMA2_ALIGN - 1)
0309 
0310 /*
0311  * ADMA2 descriptor alignment.  Some controllers (e.g. Intel) require 8 byte
0312  * alignment for the descriptor table even in 32-bit DMA mode.  Memory
0313  * allocation is at least 8 byte aligned anyway, so just stipulate 8 always.
0314  */
0315 #define SDHCI_ADMA2_DESC_ALIGN  8
0316 
0317 /*
0318  * ADMA2 64-bit DMA descriptor size
0319  * According to SD Host Controller spec v4.10, there are two kinds of
0320  * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
0321  * Descriptor, if Host Version 4 Enable is set in the Host Control 2
0322  * register, 128-bit Descriptor will be selected.
0323  */
0324 #define SDHCI_ADMA2_64_DESC_SZ(host)    ((host)->v4_mode ? 16 : 12)
0325 
0326 /*
0327  * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
0328  * aligned.
0329  */
0330 struct sdhci_adma2_64_desc {
0331     __le16  cmd;
0332     __le16  len;
0333     __le32  addr_lo;
0334     __le32  addr_hi;
0335 }  __packed __aligned(4);
0336 
0337 #define ADMA2_TRAN_VALID    0x21
0338 #define ADMA2_NOP_END_VALID 0x3
0339 #define ADMA2_END       0x2
0340 
0341 /*
0342  * Maximum segments assuming a 512KiB maximum requisition size and a minimum
0343  * 4KiB page size. Note this also allows enough for multiple descriptors in
0344  * case of PAGE_SIZE >= 64KiB.
0345  */
0346 #define SDHCI_MAX_SEGS      128
0347 
0348 /* Allow for a a command request and a data request at the same time */
0349 #define SDHCI_MAX_MRQS      2
0350 
0351 /*
0352  * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms.
0353  * However since the start time of the command, the time between
0354  * command and response, and the time between response and start of data is
0355  * not known, set the command transfer time to 10ms.
0356  */
0357 #define MMC_CMD_TRANSFER_TIME   (10 * NSEC_PER_MSEC) /* max 10 ms */
0358 
0359 #define sdhci_err_stats_inc(host, err_name) \
0360     mmc_debugfs_err_stats_inc((host)->mmc, MMC_ERR_##err_name)
0361 
0362 enum sdhci_cookie {
0363     COOKIE_UNMAPPED,
0364     COOKIE_PRE_MAPPED,  /* mapped by sdhci_pre_req() */
0365     COOKIE_MAPPED,      /* mapped by sdhci_prepare_data() */
0366 };
0367 
0368 struct sdhci_host {
0369     /* Data set by hardware interface driver */
0370     const char *hw_name;    /* Hardware bus name */
0371 
0372     unsigned int quirks;    /* Deviations from spec. */
0373 
0374 /* Controller doesn't honor resets unless we touch the clock register */
0375 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET          (1<<0)
0376 /* Controller has bad caps bits, but really supports DMA */
0377 #define SDHCI_QUIRK_FORCE_DMA               (1<<1)
0378 /* Controller doesn't like to be reset when there is no card inserted. */
0379 #define SDHCI_QUIRK_NO_CARD_NO_RESET            (1<<2)
0380 /* Controller doesn't like clearing the power reg before a change */
0381 #define SDHCI_QUIRK_SINGLE_POWER_WRITE          (1<<3)
0382 /* Controller has flaky internal state so reset it on each ios change */
0383 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS       (1<<4)
0384 /* Controller has an unusable DMA engine */
0385 #define SDHCI_QUIRK_BROKEN_DMA              (1<<5)
0386 /* Controller has an unusable ADMA engine */
0387 #define SDHCI_QUIRK_BROKEN_ADMA             (1<<6)
0388 /* Controller can only DMA from 32-bit aligned addresses */
0389 #define SDHCI_QUIRK_32BIT_DMA_ADDR          (1<<7)
0390 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
0391 #define SDHCI_QUIRK_32BIT_DMA_SIZE          (1<<8)
0392 /* Controller can only ADMA chunks that are a multiple of 32 bits */
0393 #define SDHCI_QUIRK_32BIT_ADMA_SIZE         (1<<9)
0394 /* Controller needs to be reset after each request to stay stable */
0395 #define SDHCI_QUIRK_RESET_AFTER_REQUEST         (1<<10)
0396 /* Controller needs voltage and power writes to happen separately */
0397 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER     (1<<11)
0398 /* Controller provides an incorrect timeout value for transfers */
0399 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL          (1<<12)
0400 /* Controller has an issue with buffer bits for small transfers */
0401 #define SDHCI_QUIRK_BROKEN_SMALL_PIO            (1<<13)
0402 /* Controller does not provide transfer-complete interrupt when not busy */
0403 #define SDHCI_QUIRK_NO_BUSY_IRQ             (1<<14)
0404 /* Controller has unreliable card detection */
0405 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION       (1<<15)
0406 /* Controller reports inverted write-protect state */
0407 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT      (1<<16)
0408 /* Controller has unusable command queue engine */
0409 #define SDHCI_QUIRK_BROKEN_CQE              (1<<17)
0410 /* Controller does not like fast PIO transfers */
0411 #define SDHCI_QUIRK_PIO_NEEDS_DELAY         (1<<18)
0412 /* Controller does not have a LED */
0413 #define SDHCI_QUIRK_NO_LED              (1<<19)
0414 /* Controller has to be forced to use block size of 2048 bytes */
0415 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048           (1<<20)
0416 /* Controller cannot do multi-block transfers */
0417 #define SDHCI_QUIRK_NO_MULTIBLOCK           (1<<21)
0418 /* Controller can only handle 1-bit data transfers */
0419 #define SDHCI_QUIRK_FORCE_1_BIT_DATA            (1<<22)
0420 /* Controller needs 10ms delay between applying power and clock */
0421 #define SDHCI_QUIRK_DELAY_AFTER_POWER           (1<<23)
0422 /* Controller uses SDCLK instead of TMCLK for data timeouts */
0423 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK     (1<<24)
0424 /* Controller reports wrong base clock capability */
0425 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN       (1<<25)
0426 /* Controller cannot support End Attribute in NOP ADMA descriptor */
0427 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC       (1<<26)
0428 /* Controller is missing device caps. Use caps provided by host */
0429 #define SDHCI_QUIRK_MISSING_CAPS            (1<<27)
0430 /* Controller uses Auto CMD12 command to stop the transfer */
0431 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12      (1<<28)
0432 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
0433 #define SDHCI_QUIRK_NO_HISPD_BIT            (1<<29)
0434 /* Controller treats ADMA descriptors with length 0000h incorrectly */
0435 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC        (1<<30)
0436 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
0437 #define SDHCI_QUIRK_UNSTABLE_RO_DETECT          (1<<31)
0438 
0439     unsigned int quirks2;   /* More deviations from spec. */
0440 
0441 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON           (1<<0)
0442 #define SDHCI_QUIRK2_HOST_NO_CMD23          (1<<1)
0443 /* The system physically doesn't support 1.8v, even if the host does */
0444 #define SDHCI_QUIRK2_NO_1_8_V               (1<<2)
0445 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN        (1<<3)
0446 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON       (1<<4)
0447 /* Controller has a non-standard host control register */
0448 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL        (1<<5)
0449 /* Controller does not support HS200 */
0450 #define SDHCI_QUIRK2_BROKEN_HS200           (1<<6)
0451 /* Controller does not support DDR50 */
0452 #define SDHCI_QUIRK2_BROKEN_DDR50           (1<<7)
0453 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
0454 #define SDHCI_QUIRK2_STOP_WITH_TC           (1<<8)
0455 /* Controller does not support 64-bit DMA */
0456 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA          (1<<9)
0457 /* need clear transfer mode register before send cmd */
0458 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD  (1<<10)
0459 /* Capability register bit-63 indicates HS400 support */
0460 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400       (1<<11)
0461 /* forced tuned clock */
0462 #define SDHCI_QUIRK2_TUNING_WORK_AROUND         (1<<12)
0463 /* disable the block count for single block transactions */
0464 #define SDHCI_QUIRK2_SUPPORT_SINGLE         (1<<13)
0465 /* Controller broken with using ACMD23 */
0466 #define SDHCI_QUIRK2_ACMD23_BROKEN          (1<<14)
0467 /* Broken Clock divider zero in controller */
0468 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN      (1<<15)
0469 /* Controller has CRC in 136 bit Command Response */
0470 #define SDHCI_QUIRK2_RSP_136_HAS_CRC            (1<<16)
0471 /*
0472  * Disable HW timeout if the requested timeout is more than the maximum
0473  * obtainable timeout.
0474  */
0475 #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT         (1<<17)
0476 /*
0477  * 32-bit block count may not support eMMC where upper bits of CMD23 are used
0478  * for other purposes.  Consequently we support 16-bit block count by default.
0479  * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
0480  * block count.
0481  */
0482 #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT          (1<<18)
0483 
0484     int irq;        /* Device IRQ */
0485     void __iomem *ioaddr;   /* Mapped address */
0486     phys_addr_t mapbase;    /* physical address base */
0487     char *bounce_buffer;    /* For packing SDMA reads/writes */
0488     dma_addr_t bounce_addr;
0489     unsigned int bounce_buffer_size;
0490 
0491     const struct sdhci_ops *ops;    /* Low level hw interface */
0492 
0493     /* Internal data */
0494     struct mmc_host *mmc;   /* MMC structure */
0495     struct mmc_host_ops mmc_host_ops;   /* MMC host ops */
0496     u64 dma_mask;       /* custom DMA mask */
0497 
0498 #if IS_ENABLED(CONFIG_LEDS_CLASS)
0499     struct led_classdev led;    /* LED control */
0500     char led_name[32];
0501 #endif
0502 
0503     spinlock_t lock;    /* Mutex */
0504 
0505     int flags;      /* Host attributes */
0506 #define SDHCI_USE_SDMA      (1<<0)  /* Host is SDMA capable */
0507 #define SDHCI_USE_ADMA      (1<<1)  /* Host is ADMA capable */
0508 #define SDHCI_REQ_USE_DMA   (1<<2)  /* Use DMA for this req. */
0509 #define SDHCI_DEVICE_DEAD   (1<<3)  /* Device unresponsive */
0510 #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */
0511 #define SDHCI_AUTO_CMD12    (1<<6)  /* Auto CMD12 support */
0512 #define SDHCI_AUTO_CMD23    (1<<7)  /* Auto CMD23 support */
0513 #define SDHCI_PV_ENABLED    (1<<8)  /* Preset value enabled */
0514 #define SDHCI_USE_64_BIT_DMA    (1<<12) /* Use 64-bit DMA */
0515 #define SDHCI_HS400_TUNING  (1<<13) /* Tuning for HS400 */
0516 #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */
0517 #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */
0518 #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */
0519 
0520     unsigned int version;   /* SDHCI spec. version */
0521 
0522     unsigned int max_clk;   /* Max possible freq (MHz) */
0523     unsigned int timeout_clk;   /* Timeout freq (KHz) */
0524     u8 max_timeout_count;   /* Vendor specific max timeout count */
0525     unsigned int clk_mul;   /* Clock Muliplier value */
0526 
0527     unsigned int clock; /* Current clock (MHz) */
0528     u8 pwr;         /* Current voltage */
0529 
0530     bool runtime_suspended; /* Host is runtime suspended */
0531     bool bus_on;        /* Bus power prevents runtime suspend */
0532     bool preset_enabled;    /* Preset is enabled */
0533     bool pending_reset; /* Cmd/data reset is pending */
0534     bool irq_wake_enabled;  /* IRQ wakeup is enabled */
0535     bool v4_mode;       /* Host Version 4 Enable */
0536     bool use_external_dma;  /* Host selects to use external DMA */
0537     bool always_defer_done; /* Always defer to complete requests */
0538 
0539     struct mmc_request *mrqs_done[SDHCI_MAX_MRQS];  /* Requests done */
0540     struct mmc_command *cmd;    /* Current command */
0541     struct mmc_command *data_cmd;   /* Current data command */
0542     struct mmc_command *deferred_cmd;   /* Deferred command */
0543     struct mmc_data *data;  /* Current data request */
0544     unsigned int data_early:1;  /* Data finished before cmd */
0545 
0546     struct sg_mapping_iter sg_miter;    /* SG state for PIO */
0547     unsigned int blocks;    /* remaining PIO blocks */
0548 
0549     int sg_count;       /* Mapped sg entries */
0550     int max_adma;       /* Max. length in ADMA descriptor */
0551 
0552     void *adma_table;   /* ADMA descriptor table */
0553     void *align_buffer; /* Bounce buffer */
0554 
0555     size_t adma_table_sz;   /* ADMA descriptor table size */
0556     size_t align_buffer_sz; /* Bounce buffer size */
0557 
0558     dma_addr_t adma_addr;   /* Mapped ADMA descr. table */
0559     dma_addr_t align_addr;  /* Mapped bounce buffer */
0560 
0561     unsigned int desc_sz;   /* ADMA current descriptor size */
0562     unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */
0563 
0564     struct workqueue_struct *complete_wq;   /* Request completion wq */
0565     struct work_struct  complete_work;  /* Request completion work */
0566 
0567     struct timer_list timer;    /* Timer for timeouts */
0568     struct timer_list data_timer;   /* Timer for data timeouts */
0569 
0570 #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
0571     struct dma_chan *rx_chan;
0572     struct dma_chan *tx_chan;
0573 #endif
0574 
0575     u32 caps;       /* CAPABILITY_0 */
0576     u32 caps1;      /* CAPABILITY_1 */
0577     bool read_caps;     /* Capability flags have been read */
0578 
0579     bool sdhci_core_to_disable_vqmmc;  /* sdhci core can disable vqmmc */
0580     unsigned int            ocr_avail_sdio; /* OCR bit masks */
0581     unsigned int            ocr_avail_sd;
0582     unsigned int            ocr_avail_mmc;
0583     u32 ocr_mask;       /* available voltages */
0584 
0585     unsigned        timing;     /* Current timing */
0586 
0587     u32         thread_isr;
0588 
0589     /* cached registers */
0590     u32         ier;
0591 
0592     bool            cqe_on;     /* CQE is operating */
0593     u32         cqe_ier;    /* CQE interrupt mask */
0594     u32         cqe_err_ier;    /* CQE error interrupt mask */
0595 
0596     wait_queue_head_t   buf_ready_int;  /* Waitqueue for Buffer Read Ready interrupt */
0597     unsigned int        tuning_done;    /* Condition flag set when CMD19 succeeds */
0598 
0599     unsigned int        tuning_count;   /* Timer count for re-tuning */
0600     unsigned int        tuning_mode;    /* Re-tuning mode supported by host */
0601     unsigned int        tuning_err; /* Error code for re-tuning */
0602 #define SDHCI_TUNING_MODE_1 0
0603 #define SDHCI_TUNING_MODE_2 1
0604 #define SDHCI_TUNING_MODE_3 2
0605     /* Delay (ms) between tuning commands */
0606     int         tuning_delay;
0607     int         tuning_loop_count;
0608 
0609     /* Host SDMA buffer boundary. */
0610     u32         sdma_boundary;
0611 
0612     /* Host ADMA table count */
0613     u32         adma_table_cnt;
0614 
0615     u64         data_timeout;
0616 
0617     unsigned long private[] ____cacheline_aligned;
0618 };
0619 
0620 struct sdhci_ops {
0621 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
0622     u32     (*read_l)(struct sdhci_host *host, int reg);
0623     u16     (*read_w)(struct sdhci_host *host, int reg);
0624     u8      (*read_b)(struct sdhci_host *host, int reg);
0625     void        (*write_l)(struct sdhci_host *host, u32 val, int reg);
0626     void        (*write_w)(struct sdhci_host *host, u16 val, int reg);
0627     void        (*write_b)(struct sdhci_host *host, u8 val, int reg);
0628 #endif
0629 
0630     void    (*set_clock)(struct sdhci_host *host, unsigned int clock);
0631     void    (*set_power)(struct sdhci_host *host, unsigned char mode,
0632                  unsigned short vdd);
0633 
0634     u32     (*irq)(struct sdhci_host *host, u32 intmask);
0635 
0636     int     (*set_dma_mask)(struct sdhci_host *host);
0637     int     (*enable_dma)(struct sdhci_host *host);
0638     unsigned int    (*get_max_clock)(struct sdhci_host *host);
0639     unsigned int    (*get_min_clock)(struct sdhci_host *host);
0640     /* get_timeout_clock should return clk rate in unit of Hz */
0641     unsigned int    (*get_timeout_clock)(struct sdhci_host *host);
0642     unsigned int    (*get_max_timeout_count)(struct sdhci_host *host);
0643     void        (*set_timeout)(struct sdhci_host *host,
0644                        struct mmc_command *cmd);
0645     void        (*set_bus_width)(struct sdhci_host *host, int width);
0646     void (*platform_send_init_74_clocks)(struct sdhci_host *host,
0647                          u8 power_mode);
0648     unsigned int    (*get_ro)(struct sdhci_host *host);
0649     void        (*reset)(struct sdhci_host *host, u8 mask);
0650     int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
0651     void    (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
0652     void    (*hw_reset)(struct sdhci_host *host);
0653     void    (*adma_workaround)(struct sdhci_host *host, u32 intmask);
0654     void    (*card_event)(struct sdhci_host *host);
0655     void    (*voltage_switch)(struct sdhci_host *host);
0656     void    (*adma_write_desc)(struct sdhci_host *host, void **desc,
0657                    dma_addr_t addr, int len, unsigned int cmd);
0658     void    (*copy_to_bounce_buffer)(struct sdhci_host *host,
0659                      struct mmc_data *data,
0660                      unsigned int length);
0661     void    (*request_done)(struct sdhci_host *host,
0662                 struct mmc_request *mrq);
0663     void    (*dump_vendor_regs)(struct sdhci_host *host);
0664 };
0665 
0666 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
0667 
0668 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
0669 {
0670     if (unlikely(host->ops->write_l))
0671         host->ops->write_l(host, val, reg);
0672     else
0673         writel(val, host->ioaddr + reg);
0674 }
0675 
0676 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
0677 {
0678     if (unlikely(host->ops->write_w))
0679         host->ops->write_w(host, val, reg);
0680     else
0681         writew(val, host->ioaddr + reg);
0682 }
0683 
0684 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
0685 {
0686     if (unlikely(host->ops->write_b))
0687         host->ops->write_b(host, val, reg);
0688     else
0689         writeb(val, host->ioaddr + reg);
0690 }
0691 
0692 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
0693 {
0694     if (unlikely(host->ops->read_l))
0695         return host->ops->read_l(host, reg);
0696     else
0697         return readl(host->ioaddr + reg);
0698 }
0699 
0700 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
0701 {
0702     if (unlikely(host->ops->read_w))
0703         return host->ops->read_w(host, reg);
0704     else
0705         return readw(host->ioaddr + reg);
0706 }
0707 
0708 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
0709 {
0710     if (unlikely(host->ops->read_b))
0711         return host->ops->read_b(host, reg);
0712     else
0713         return readb(host->ioaddr + reg);
0714 }
0715 
0716 #else
0717 
0718 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
0719 {
0720     writel(val, host->ioaddr + reg);
0721 }
0722 
0723 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
0724 {
0725     writew(val, host->ioaddr + reg);
0726 }
0727 
0728 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
0729 {
0730     writeb(val, host->ioaddr + reg);
0731 }
0732 
0733 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
0734 {
0735     return readl(host->ioaddr + reg);
0736 }
0737 
0738 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
0739 {
0740     return readw(host->ioaddr + reg);
0741 }
0742 
0743 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
0744 {
0745     return readb(host->ioaddr + reg);
0746 }
0747 
0748 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
0749 
0750 struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size);
0751 void sdhci_free_host(struct sdhci_host *host);
0752 
0753 static inline void *sdhci_priv(struct sdhci_host *host)
0754 {
0755     return host->private;
0756 }
0757 
0758 void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
0759                const u32 *caps, const u32 *caps1);
0760 int sdhci_setup_host(struct sdhci_host *host);
0761 void sdhci_cleanup_host(struct sdhci_host *host);
0762 int __sdhci_add_host(struct sdhci_host *host);
0763 int sdhci_add_host(struct sdhci_host *host);
0764 void sdhci_remove_host(struct sdhci_host *host, int dead);
0765 
0766 static inline void sdhci_read_caps(struct sdhci_host *host)
0767 {
0768     __sdhci_read_caps(host, NULL, NULL, NULL);
0769 }
0770 
0771 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
0772            unsigned int *actual_clock);
0773 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
0774 void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
0775 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
0776              unsigned short vdd);
0777 void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
0778                      unsigned char mode,
0779                      unsigned short vdd);
0780 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
0781                unsigned short vdd);
0782 int sdhci_get_cd_nogpio(struct mmc_host *mmc);
0783 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq);
0784 int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq);
0785 void sdhci_set_bus_width(struct sdhci_host *host, int width);
0786 void sdhci_reset(struct sdhci_host *host, u8 mask);
0787 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
0788 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
0789 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
0790 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
0791                       struct mmc_ios *ios);
0792 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
0793 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
0794                dma_addr_t addr, int len, unsigned int cmd);
0795 
0796 #ifdef CONFIG_PM
0797 int sdhci_suspend_host(struct sdhci_host *host);
0798 int sdhci_resume_host(struct sdhci_host *host);
0799 int sdhci_runtime_suspend_host(struct sdhci_host *host);
0800 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset);
0801 #endif
0802 
0803 void sdhci_cqe_enable(struct mmc_host *mmc);
0804 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery);
0805 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
0806            int *data_error);
0807 
0808 void sdhci_dumpregs(struct sdhci_host *host);
0809 void sdhci_enable_v4_mode(struct sdhci_host *host);
0810 
0811 void sdhci_start_tuning(struct sdhci_host *host);
0812 void sdhci_end_tuning(struct sdhci_host *host);
0813 void sdhci_reset_tuning(struct sdhci_host *host);
0814 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode);
0815 void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode);
0816 void sdhci_switch_external_dma(struct sdhci_host *host, bool en);
0817 void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable);
0818 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd);
0819 
0820 #endif /* __SDHCI_HW_H */