mmc/host/sdhci-xenon.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2016 Marvell, All Rights Reserved.
0004  *
0005  * Author:  Hu Ziji <huziji@marvell.com>
0006  * Date:    2016-8-24
0007  */
0008 #ifndef SDHCI_XENON_H_
0009 #define SDHCI_XENON_H_
0010
0011 /* Register Offset of Xenon SDHC self-defined register */
0012 #define XENON_SYS_CFG_INFO          0x0104
0013 #define XENON_SLOT_TYPE_SDIO_SHIFT      24
0014 #define XENON_NR_SUPPORTED_SLOT_MASK        0x7
0015
0016 #define XENON_SYS_OP_CTRL           0x0108
0017 #define XENON_AUTO_CLKGATE_DISABLE_MASK     BIT(20)
0018 #define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT    8
0019 #define XENON_SLOT_ENABLE_SHIFT         0
0020
0021 #define XENON_SYS_EXT_OP_CTRL           0x010C
0022 #define XENON_MASK_CMD_CONFLICT_ERR     BIT(8)
0023
0024 #define XENON_SLOT_OP_STATUS_CTRL       0x0128
0025 #define XENON_TUN_CONSECUTIVE_TIMES_SHIFT   16
0026 #define XENON_TUN_CONSECUTIVE_TIMES_MASK    0x7
0027 #define XENON_TUN_CONSECUTIVE_TIMES     0x4
0028 #define XENON_TUNING_STEP_SHIFT         12
0029 #define XENON_TUNING_STEP_MASK          0xF
0030 #define XENON_TUNING_STEP_DIVIDER       BIT(6)
0031
0032 #define XENON_SLOT_EMMC_CTRL            0x0130
0033 #define XENON_ENABLE_RESP_STROBE        BIT(25)
0034 #define XENON_ENABLE_DATA_STROBE        BIT(24)
0035
0036 #define XENON_SLOT_RETUNING_REQ_CTRL        0x0144
0037 /* retuning compatible */
0038 #define XENON_RETUNING_COMPATIBLE       0x1
0039
0040 #define XENON_SLOT_EXT_PRESENT_STATE        0x014C
0041 #define XENON_DLL_LOCK_STATE            0x1
0042
0043 #define XENON_SLOT_DLL_CUR_DLY_VAL      0x0150
0044
0045 /* Tuning Parameter */
0046 #define XENON_TMR_RETUN_NO_PRESENT      0xF
0047 #define XENON_DEF_TUNING_COUNT          0x9
0048
0049 #define XENON_DEFAULT_SDCLK_FREQ        400000
0050 #define XENON_LOWEST_SDCLK_FREQ         100000
0051
0052 /* Xenon specific Mode Select value */
0053 #define XENON_CTRL_HS200            0x5
0054 #define XENON_CTRL_HS400            0x6
0055
0056 enum xenon_variant {
0057     XENON_A3700,
0058     XENON_AP806,
0059     XENON_AP807,
0060     XENON_CP110
0061 };
0062
0063 struct xenon_priv {
0064     unsigned char   tuning_count;
0065     /* idx of SDHC */
0066     u8      sdhc_id;
0067
0068     /*
0069      * eMMC/SD/SDIO require different register settings.
0070      * Xenon driver has to recognize card type
0071      * before mmc_host->card is not available.
0072      * This field records the card type during init.
0073      * It is updated in xenon_init_card().
0074      *
0075      * It is only valid during initialization after it is updated.
0076      * Do not access this variable in normal transfers after
0077      * initialization completes.
0078      */
0079     unsigned int    init_card_type;
0080
0081     /*
0082      * The bus_width, timing, and clock fields in below
0083      * record the current ios setting of Xenon SDHC.
0084      * Driver will adjust PHY setting if any change to
0085      * ios affects PHY timing.
0086      */
0087     unsigned char   bus_width;
0088     unsigned char   timing;
0089     unsigned int    clock;
0090     struct clk      *axi_clk;
0091
0092     int     phy_type;
0093     /*
0094      * Contains board-specific PHY parameters
0095      * passed from device tree.
0096      */
0097     void        *phy_params;
0098     struct xenon_emmc_phy_regs *emmc_phy_regs;
0099     bool restore_needed;
0100     enum xenon_variant hw_version;
0101 };
0102
0103 int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
0104 int xenon_phy_parse_params(struct device *dev,
0105                struct sdhci_host *host);
0106 void xenon_soc_pad_ctrl(struct sdhci_host *host,
0107             unsigned char signal_voltage);
0108 #endif