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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2010 Google, Inc.
0004  */
0005 
0006 #include <linux/delay.h>
0007 #include <linux/dma-mapping.h>
0008 #include <linux/err.h>
0009 #include <linux/module.h>
0010 #include <linux/init.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/clk.h>
0014 #include <linux/io.h>
0015 #include <linux/of.h>
0016 #include <linux/of_device.h>
0017 #include <linux/pinctrl/consumer.h>
0018 #include <linux/pm_opp.h>
0019 #include <linux/pm_runtime.h>
0020 #include <linux/regulator/consumer.h>
0021 #include <linux/reset.h>
0022 #include <linux/mmc/card.h>
0023 #include <linux/mmc/host.h>
0024 #include <linux/mmc/mmc.h>
0025 #include <linux/mmc/slot-gpio.h>
0026 #include <linux/gpio/consumer.h>
0027 #include <linux/ktime.h>
0028 
0029 #include <soc/tegra/common.h>
0030 
0031 #include "sdhci-pltfm.h"
0032 #include "cqhci.h"
0033 
0034 /* Tegra SDHOST controller vendor register definitions */
0035 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL           0x100
0036 #define SDHCI_CLOCK_CTRL_TAP_MASK           0x00ff0000
0037 #define SDHCI_CLOCK_CTRL_TAP_SHIFT          16
0038 #define SDHCI_CLOCK_CTRL_TRIM_MASK          0x1f000000
0039 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT         24
0040 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE      BIT(5)
0041 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE     BIT(3)
0042 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE    BIT(2)
0043 
0044 #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL          0x104
0045 #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE     BIT(31)
0046 
0047 #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES        0x10c
0048 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK     0x00003f00
0049 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT    8
0050 
0051 #define SDHCI_TEGRA_VENDOR_MISC_CTRL            0x120
0052 #define SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT     BIT(0)
0053 #define SDHCI_MISC_CTRL_ENABLE_SDR104           0x8
0054 #define SDHCI_MISC_CTRL_ENABLE_SDR50            0x10
0055 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300       0x20
0056 #define SDHCI_MISC_CTRL_ENABLE_DDR50            0x200
0057 
0058 #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG           0x1b0
0059 #define SDHCI_TEGRA_DLLCAL_CALIBRATE            BIT(31)
0060 
0061 #define SDHCI_TEGRA_VENDOR_DLLCAL_STA           0x1bc
0062 #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE           BIT(31)
0063 
0064 #define SDHCI_VNDR_TUN_CTRL0_0              0x1c0
0065 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP         0x20000
0066 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK     0x03fc0000
0067 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT    18
0068 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK         0x00001fc0
0069 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT        6
0070 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK      0x000e000
0071 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT     13
0072 #define TRIES_128                   2
0073 #define TRIES_256                   4
0074 #define SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK      0x7
0075 
0076 #define SDHCI_TEGRA_VNDR_TUN_CTRL1_0            0x1c4
0077 #define SDHCI_TEGRA_VNDR_TUN_STATUS0            0x1C8
0078 #define SDHCI_TEGRA_VNDR_TUN_STATUS1            0x1CC
0079 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK       0xFF
0080 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT  0x8
0081 #define TUNING_WORD_BIT_SIZE                32
0082 
0083 #define SDHCI_TEGRA_AUTO_CAL_CONFIG         0x1e4
0084 #define SDHCI_AUTO_CAL_START                BIT(31)
0085 #define SDHCI_AUTO_CAL_ENABLE               BIT(29)
0086 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK         0x0000ffff
0087 
0088 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL          0x1e0
0089 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK    0x0000000f
0090 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7
0091 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD   BIT(31)
0092 #define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK      0x07FFF000
0093 
0094 #define SDHCI_TEGRA_AUTO_CAL_STATUS         0x1ec
0095 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE         BIT(31)
0096 
0097 #define NVQUIRK_FORCE_SDHCI_SPEC_200            BIT(0)
0098 #define NVQUIRK_ENABLE_BLOCK_GAP_DET            BIT(1)
0099 #define NVQUIRK_ENABLE_SDHCI_SPEC_300           BIT(2)
0100 #define NVQUIRK_ENABLE_SDR50                BIT(3)
0101 #define NVQUIRK_ENABLE_SDR104               BIT(4)
0102 #define NVQUIRK_ENABLE_DDR50                BIT(5)
0103 /*
0104  * HAS_PADCALIB NVQUIRK is for SoC's supporting auto calibration of pads
0105  * drive strength.
0106  */
0107 #define NVQUIRK_HAS_PADCALIB                BIT(6)
0108 /*
0109  * NEEDS_PAD_CONTROL NVQUIRK is for SoC's having separate 3V3 and 1V8 pads.
0110  * 3V3/1V8 pad selection happens through pinctrl state selection depending
0111  * on the signaling mode.
0112  */
0113 #define NVQUIRK_NEEDS_PAD_CONTROL           BIT(7)
0114 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP         BIT(8)
0115 #define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING       BIT(9)
0116 
0117 /*
0118  * NVQUIRK_HAS_TMCLK is for SoC's having separate timeout clock for Tegra
0119  * SDMMC hardware data timeout.
0120  */
0121 #define NVQUIRK_HAS_TMCLK               BIT(10)
0122 
0123 #define NVQUIRK_HAS_ANDROID_GPT_SECTOR          BIT(11)
0124 
0125 /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */
0126 #define SDHCI_TEGRA_CQE_BASE_ADDR           0xF000
0127 
0128 #define SDHCI_TEGRA_CQE_TRNS_MODE   (SDHCI_TRNS_MULTI | \
0129                      SDHCI_TRNS_BLK_CNT_EN | \
0130                      SDHCI_TRNS_DMA)
0131 
0132 struct sdhci_tegra_soc_data {
0133     const struct sdhci_pltfm_data *pdata;
0134     u64 dma_mask;
0135     u32 nvquirks;
0136     u8 min_tap_delay;
0137     u8 max_tap_delay;
0138 };
0139 
0140 /* Magic pull up and pull down pad calibration offsets */
0141 struct sdhci_tegra_autocal_offsets {
0142     u32 pull_up_3v3;
0143     u32 pull_down_3v3;
0144     u32 pull_up_3v3_timeout;
0145     u32 pull_down_3v3_timeout;
0146     u32 pull_up_1v8;
0147     u32 pull_down_1v8;
0148     u32 pull_up_1v8_timeout;
0149     u32 pull_down_1v8_timeout;
0150     u32 pull_up_sdr104;
0151     u32 pull_down_sdr104;
0152     u32 pull_up_hs400;
0153     u32 pull_down_hs400;
0154 };
0155 
0156 struct sdhci_tegra {
0157     const struct sdhci_tegra_soc_data *soc_data;
0158     struct gpio_desc *power_gpio;
0159     struct clk *tmclk;
0160     bool ddr_signaling;
0161     bool pad_calib_required;
0162     bool pad_control_available;
0163 
0164     struct reset_control *rst;
0165     struct pinctrl *pinctrl_sdmmc;
0166     struct pinctrl_state *pinctrl_state_3v3;
0167     struct pinctrl_state *pinctrl_state_1v8;
0168     struct pinctrl_state *pinctrl_state_3v3_drv;
0169     struct pinctrl_state *pinctrl_state_1v8_drv;
0170 
0171     struct sdhci_tegra_autocal_offsets autocal_offsets;
0172     ktime_t last_calib;
0173 
0174     u32 default_tap;
0175     u32 default_trim;
0176     u32 dqs_trim;
0177     bool enable_hwcq;
0178     unsigned long curr_clk_rate;
0179     u8 tuned_tap_delay;
0180 };
0181 
0182 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
0183 {
0184     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0185     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
0186     const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
0187 
0188     if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
0189             (reg == SDHCI_HOST_VERSION))) {
0190         /* Erratum: Version register is invalid in HW. */
0191         return SDHCI_SPEC_200;
0192     }
0193 
0194     return readw(host->ioaddr + reg);
0195 }
0196 
0197 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
0198 {
0199     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0200 
0201     switch (reg) {
0202     case SDHCI_TRANSFER_MODE:
0203         /*
0204          * Postpone this write, we must do it together with a
0205          * command write that is down below.
0206          */
0207         pltfm_host->xfer_mode_shadow = val;
0208         return;
0209     case SDHCI_COMMAND:
0210         writel((val << 16) | pltfm_host->xfer_mode_shadow,
0211             host->ioaddr + SDHCI_TRANSFER_MODE);
0212         return;
0213     }
0214 
0215     writew(val, host->ioaddr + reg);
0216 }
0217 
0218 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
0219 {
0220     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0221     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
0222     const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
0223 
0224     /* Seems like we're getting spurious timeout and crc errors, so
0225      * disable signalling of them. In case of real errors software
0226      * timers should take care of eventually detecting them.
0227      */
0228     if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
0229         val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
0230 
0231     writel(val, host->ioaddr + reg);
0232 
0233     if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
0234             (reg == SDHCI_INT_ENABLE))) {
0235         /* Erratum: Must enable block gap interrupt detection */
0236         u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
0237         if (val & SDHCI_INT_CARD_INT)
0238             gap_ctrl |= 0x8;
0239         else
0240             gap_ctrl &= ~0x8;
0241         writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
0242     }
0243 }
0244 
0245 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable)
0246 {
0247     bool status;
0248     u32 reg;
0249 
0250     reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
0251     status = !!(reg & SDHCI_CLOCK_CARD_EN);
0252 
0253     if (status == enable)
0254         return status;
0255 
0256     if (enable)
0257         reg |= SDHCI_CLOCK_CARD_EN;
0258     else
0259         reg &= ~SDHCI_CLOCK_CARD_EN;
0260 
0261     sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
0262 
0263     return status;
0264 }
0265 
0266 static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
0267 {
0268     bool is_tuning_cmd = 0;
0269     bool clk_enabled;
0270     u8 cmd;
0271 
0272     if (reg == SDHCI_COMMAND) {
0273         cmd = SDHCI_GET_CMD(val);
0274         is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK ||
0275                 cmd == MMC_SEND_TUNING_BLOCK_HS200;
0276     }
0277 
0278     if (is_tuning_cmd)
0279         clk_enabled = tegra_sdhci_configure_card_clk(host, 0);
0280 
0281     writew(val, host->ioaddr + reg);
0282 
0283     if (is_tuning_cmd) {
0284         udelay(1);
0285         sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
0286         tegra_sdhci_configure_card_clk(host, clk_enabled);
0287     }
0288 }
0289 
0290 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
0291 {
0292     /*
0293      * Write-enable shall be assumed if GPIO is missing in a board's
0294      * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on
0295      * Tegra.
0296      */
0297     return mmc_gpio_get_ro(host->mmc);
0298 }
0299 
0300 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host)
0301 {
0302     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0303     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
0304     int has_1v8, has_3v3;
0305 
0306     /*
0307      * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad
0308      * voltage configuration in order to perform voltage switching. This
0309      * means that valid pinctrl info is required on SDHCI instances capable
0310      * of performing voltage switching. Whether or not an SDHCI instance is
0311      * capable of voltage switching is determined based on the regulator.
0312      */
0313 
0314     if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))
0315         return true;
0316 
0317     if (IS_ERR(host->mmc->supply.vqmmc))
0318         return false;
0319 
0320     has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc,
0321                          1700000, 1950000);
0322 
0323     has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc,
0324                          2700000, 3600000);
0325 
0326     if (has_1v8 == 1 && has_3v3 == 1)
0327         return tegra_host->pad_control_available;
0328 
0329     /* Fixed voltage, no pad control required. */
0330     return true;
0331 }
0332 
0333 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
0334 {
0335     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0336     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
0337     const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
0338     bool card_clk_enabled = false;
0339     u32 reg;
0340 
0341     /*
0342      * Touching the tap values is a bit tricky on some SoC generations.
0343      * The quirk enables a workaround for a glitch that sometimes occurs if
0344      * the tap values are changed.
0345      */
0346 
0347     if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP)
0348         card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
0349 
0350     reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
0351     reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
0352     reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
0353     sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
0354 
0355     if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP &&
0356         card_clk_enabled) {
0357         udelay(1);
0358         sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
0359         tegra_sdhci_configure_card_clk(host, card_clk_enabled);
0360     }
0361 }
0362 
0363 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
0364 {
0365     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0366     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
0367     const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
0368     u32 misc_ctrl, clk_ctrl, pad_ctrl;
0369 
0370     sdhci_reset(host, mask);
0371 
0372     if (!(mask & SDHCI_RESET_ALL))
0373         return;
0374 
0375     tegra_sdhci_set_tap(host, tegra_host->default_tap);
0376 
0377     misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
0378     clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
0379 
0380     misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 |
0381                SDHCI_MISC_CTRL_ENABLE_SDR50 |
0382                SDHCI_MISC_CTRL_ENABLE_DDR50 |
0383                SDHCI_MISC_CTRL_ENABLE_SDR104);
0384 
0385     clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK |
0386               SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE);
0387 
0388     if (tegra_sdhci_is_pad_and_regulator_valid(host)) {
0389         /* Erratum: Enable SDHCI spec v3.00 support */
0390         if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
0391             misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
0392         /* Advertise UHS modes as supported by host */
0393         if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
0394             misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50;
0395         if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
0396             misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;
0397         if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
0398             misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;
0399         if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
0400             clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
0401     }
0402 
0403     clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT;
0404 
0405     sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
0406     sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
0407 
0408     if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) {
0409         pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
0410         pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK;
0411         pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL;
0412         sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
0413 
0414         tegra_host->pad_calib_required = true;
0415     }
0416 
0417     tegra_host->ddr_signaling = false;
0418 }
0419 
0420 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable)
0421 {
0422     u32 val;
0423 
0424     /*
0425      * Enable or disable the additional I/O pad used by the drive strength
0426      * calibration process.
0427      */
0428     val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
0429 
0430     if (enable)
0431         val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD;
0432     else
0433         val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD;
0434 
0435     sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
0436 
0437     if (enable)
0438         usleep_range(1, 2);
0439 }
0440 
0441 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host,
0442                            u16 pdpu)
0443 {
0444     u32 reg;
0445 
0446     reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
0447     reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK;
0448     reg |= pdpu;
0449     sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
0450 }
0451 
0452 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage,
0453                    bool state_drvupdn)
0454 {
0455     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0456     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
0457     struct sdhci_tegra_autocal_offsets *offsets =
0458                         &tegra_host->autocal_offsets;
0459     struct pinctrl_state *pinctrl_drvupdn = NULL;
0460     int ret = 0;
0461     u8 drvup = 0, drvdn = 0;
0462     u32 reg;
0463 
0464     if (!state_drvupdn) {
0465         /* PADS Drive Strength */
0466         if (voltage == MMC_SIGNAL_VOLTAGE_180) {
0467             if (tegra_host->pinctrl_state_1v8_drv) {
0468                 pinctrl_drvupdn =
0469                     tegra_host->pinctrl_state_1v8_drv;
0470             } else {
0471                 drvup = offsets->pull_up_1v8_timeout;
0472                 drvdn = offsets->pull_down_1v8_timeout;
0473             }
0474         } else {
0475             if (tegra_host->pinctrl_state_3v3_drv) {
0476                 pinctrl_drvupdn =
0477                     tegra_host->pinctrl_state_3v3_drv;
0478             } else {
0479                 drvup = offsets->pull_up_3v3_timeout;
0480                 drvdn = offsets->pull_down_3v3_timeout;
0481             }
0482         }
0483 
0484         if (pinctrl_drvupdn != NULL) {
0485             ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
0486                             pinctrl_drvupdn);
0487             if (ret < 0)
0488                 dev_err(mmc_dev(host->mmc),
0489                     "failed pads drvupdn, ret: %d\n", ret);
0490         } else if ((drvup) || (drvdn)) {
0491             reg = sdhci_readl(host,
0492                     SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
0493             reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK;
0494             reg |= (drvup << 20) | (drvdn << 12);
0495             sdhci_writel(host, reg,
0496                     SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
0497         }
0498 
0499     } else {
0500         /* Dual Voltage PADS Voltage selection */
0501         if (!tegra_host->pad_control_available)
0502             return 0;
0503 
0504         if (voltage == MMC_SIGNAL_VOLTAGE_180) {
0505             ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
0506                         tegra_host->pinctrl_state_1v8);
0507             if (ret < 0)
0508                 dev_err(mmc_dev(host->mmc),
0509                     "setting 1.8V failed, ret: %d\n", ret);
0510         } else {
0511             ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
0512                         tegra_host->pinctrl_state_3v3);
0513             if (ret < 0)
0514                 dev_err(mmc_dev(host->mmc),
0515                     "setting 3.3V failed, ret: %d\n", ret);
0516         }
0517     }
0518 
0519     return ret;
0520 }
0521 
0522 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
0523 {
0524     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0525     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
0526     struct sdhci_tegra_autocal_offsets offsets =
0527             tegra_host->autocal_offsets;
0528     struct mmc_ios *ios = &host->mmc->ios;
0529     bool card_clk_enabled;
0530     u16 pdpu;
0531     u32 reg;
0532     int ret;
0533 
0534     switch (ios->timing) {
0535     case MMC_TIMING_UHS_SDR104:
0536         pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104;
0537         break;
0538     case MMC_TIMING_MMC_HS400:
0539         pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400;
0540         break;
0541     default:
0542         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
0543             pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8;
0544         else
0545             pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3;
0546     }
0547 
0548     /* Set initial offset before auto-calibration */
0549     tegra_sdhci_set_pad_autocal_offset(host, pdpu);
0550 
0551     card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
0552 
0553     tegra_sdhci_configure_cal_pad(host, true);
0554 
0555     reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
0556     reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
0557     sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
0558 
0559     usleep_range(1, 2);
0560     /* 10 ms timeout */
0561     ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS,
0562                  reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE),
0563                  1000, 10000);
0564 
0565     tegra_sdhci_configure_cal_pad(host, false);
0566 
0567     tegra_sdhci_configure_card_clk(host, card_clk_enabled);
0568 
0569     if (ret) {
0570         dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n");
0571 
0572         /* Disable automatic cal and use fixed Drive Strengths */
0573         reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
0574         reg &= ~SDHCI_AUTO_CAL_ENABLE;
0575         sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
0576 
0577         ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false);
0578         if (ret < 0)
0579             dev_err(mmc_dev(host->mmc),
0580                 "Setting drive strengths failed: %d\n", ret);
0581     }
0582 }
0583 
0584 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host)
0585 {
0586     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0587     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
0588     struct sdhci_tegra_autocal_offsets *autocal =
0589             &tegra_host->autocal_offsets;
0590     int err;
0591 
0592     err = device_property_read_u32(mmc_dev(host->mmc),
0593             "nvidia,pad-autocal-pull-up-offset-3v3",
0594             &autocal->pull_up_3v3);
0595     if (err)
0596         autocal->pull_up_3v3 = 0;
0597 
0598     err = device_property_read_u32(mmc_dev(host->mmc),
0599             "nvidia,pad-autocal-pull-down-offset-3v3",
0600             &autocal->pull_down_3v3);
0601     if (err)
0602         autocal->pull_down_3v3 = 0;
0603 
0604     err = device_property_read_u32(mmc_dev(host->mmc),
0605             "nvidia,pad-autocal-pull-up-offset-1v8",
0606             &autocal->pull_up_1v8);
0607     if (err)
0608         autocal->pull_up_1v8 = 0;
0609 
0610     err = device_property_read_u32(mmc_dev(host->mmc),
0611             "nvidia,pad-autocal-pull-down-offset-1v8",
0612             &autocal->pull_down_1v8);
0613     if (err)
0614         autocal->pull_down_1v8 = 0;
0615 
0616     err = device_property_read_u32(mmc_dev(host->mmc),
0617             "nvidia,pad-autocal-pull-up-offset-sdr104",
0618             &autocal->pull_up_sdr104);
0619     if (err)
0620         autocal->pull_up_sdr104 = autocal->pull_up_1v8;
0621 
0622     err = device_property_read_u32(mmc_dev(host->mmc),
0623             "nvidia,pad-autocal-pull-down-offset-sdr104",
0624             &autocal->pull_down_sdr104);
0625     if (err)
0626         autocal->pull_down_sdr104 = autocal->pull_down_1v8;
0627 
0628     err = device_property_read_u32(mmc_dev(host->mmc),
0629             "nvidia,pad-autocal-pull-up-offset-hs400",
0630             &autocal->pull_up_hs400);
0631     if (err)
0632         autocal->pull_up_hs400 = autocal->pull_up_1v8;
0633 
0634     err = device_property_read_u32(mmc_dev(host->mmc),
0635             "nvidia,pad-autocal-pull-down-offset-hs400",
0636             &autocal->pull_down_hs400);
0637     if (err)
0638         autocal->pull_down_hs400 = autocal->pull_down_1v8;
0639 
0640     /*
0641      * Different fail-safe drive strength values based on the signaling
0642      * voltage are applicable for SoCs supporting 3V3 and 1V8 pad controls.
0643      * So, avoid reading below device tree properties for SoCs that don't
0644      * have NVQUIRK_NEEDS_PAD_CONTROL.
0645      */
0646     if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))
0647         return;
0648 
0649     err = device_property_read_u32(mmc_dev(host->mmc),
0650             "nvidia,pad-autocal-pull-up-offset-3v3-timeout",
0651             &autocal->pull_up_3v3_timeout);
0652     if (err) {
0653         if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
0654             (tegra_host->pinctrl_state_3v3_drv == NULL))
0655             pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
0656                 mmc_hostname(host->mmc));
0657         autocal->pull_up_3v3_timeout = 0;
0658     }
0659 
0660     err = device_property_read_u32(mmc_dev(host->mmc),
0661             "nvidia,pad-autocal-pull-down-offset-3v3-timeout",
0662             &autocal->pull_down_3v3_timeout);
0663     if (err) {
0664         if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
0665             (tegra_host->pinctrl_state_3v3_drv == NULL))
0666             pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
0667                 mmc_hostname(host->mmc));
0668         autocal->pull_down_3v3_timeout = 0;
0669     }
0670 
0671     err = device_property_read_u32(mmc_dev(host->mmc),
0672             "nvidia,pad-autocal-pull-up-offset-1v8-timeout",
0673             &autocal->pull_up_1v8_timeout);
0674     if (err) {
0675         if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
0676             (tegra_host->pinctrl_state_1v8_drv == NULL))
0677             pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
0678                 mmc_hostname(host->mmc));
0679         autocal->pull_up_1v8_timeout = 0;
0680     }
0681 
0682     err = device_property_read_u32(mmc_dev(host->mmc),
0683             "nvidia,pad-autocal-pull-down-offset-1v8-timeout",
0684             &autocal->pull_down_1v8_timeout);
0685     if (err) {
0686         if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
0687             (tegra_host->pinctrl_state_1v8_drv == NULL))
0688             pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
0689                 mmc_hostname(host->mmc));
0690         autocal->pull_down_1v8_timeout = 0;
0691     }
0692 }
0693 
0694 static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
0695 {
0696     struct sdhci_host *host = mmc_priv(mmc);
0697     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0698     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
0699     ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib);
0700 
0701     /* 100 ms calibration interval is specified in the TRM */
0702     if (ktime_to_ms(since_calib) > 100) {
0703         tegra_sdhci_pad_autocalib(host);
0704         tegra_host->last_calib = ktime_get();
0705     }
0706 
0707     sdhci_request(mmc, mrq);
0708 }
0709 
0710 static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host)
0711 {
0712     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0713     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
0714     int err;
0715 
0716     err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-tap",
0717                        &tegra_host->default_tap);
0718     if (err)
0719         tegra_host->default_tap = 0;
0720 
0721     err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-trim",
0722                        &tegra_host->default_trim);
0723     if (err)
0724         tegra_host->default_trim = 0;
0725 
0726     err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,dqs-trim",
0727                        &tegra_host->dqs_trim);
0728     if (err)
0729         tegra_host->dqs_trim = 0x11;
0730 }
0731 
0732 static void tegra_sdhci_parse_dt(struct sdhci_host *host)
0733 {
0734     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0735     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
0736 
0737     if (device_property_read_bool(mmc_dev(host->mmc), "supports-cqe"))
0738         tegra_host->enable_hwcq = true;
0739     else
0740         tegra_host->enable_hwcq = false;
0741 
0742     tegra_sdhci_parse_pad_autocal_dt(host);
0743     tegra_sdhci_parse_tap_and_trim(host);
0744 }
0745 
0746 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
0747 {
0748     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0749     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
0750     struct device *dev = mmc_dev(host->mmc);
0751     unsigned long host_clk;
0752     int err;
0753 
0754     if (!clock)
0755         return sdhci_set_clock(host, clock);
0756 
0757     /*
0758      * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI
0759      * divider to be configured to divided the host clock by two. The SDHCI
0760      * clock divider is calculated as part of sdhci_set_clock() by
0761      * sdhci_calc_clk(). The divider is calculated from host->max_clk and
0762      * the requested clock rate.
0763      *
0764      * By setting the host->max_clk to clock * 2 the divider calculation
0765      * will always result in the correct value for DDR50/52 modes,
0766      * regardless of clock rate rounding, which may happen if the value
0767      * from clk_get_rate() is used.
0768      */
0769     host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
0770 
0771     err = dev_pm_opp_set_rate(dev, host_clk);
0772     if (err)
0773         dev_err(dev, "failed to set clk rate to %luHz: %d\n",
0774             host_clk, err);
0775 
0776     tegra_host->curr_clk_rate = host_clk;
0777     if (tegra_host->ddr_signaling)
0778         host->max_clk = host_clk;
0779     else
0780         host->max_clk = clk_get_rate(pltfm_host->clk);
0781 
0782     sdhci_set_clock(host, clock);
0783 
0784     if (tegra_host->pad_calib_required) {
0785         tegra_sdhci_pad_autocalib(host);
0786         tegra_host->pad_calib_required = false;
0787     }
0788 }
0789 
0790 static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc,
0791                           struct mmc_ios *ios)
0792 {
0793     struct sdhci_host *host = mmc_priv(mmc);
0794     u32 val;
0795 
0796     val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
0797 
0798     if (ios->enhanced_strobe) {
0799         val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
0800         /*
0801          * When CMD13 is sent from mmc_select_hs400es() after
0802          * switching to HS400ES mode, the bus is operating at
0803          * either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR.
0804          * To meet Tegra SDHCI requirement at HS400ES mode, force SDHCI
0805          * interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host
0806          * controller CAR clock and the interface clock are rate matched.
0807          */
0808         tegra_sdhci_set_clock(host, MMC_HS200_MAX_DTR);
0809     } else {
0810         val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
0811     }
0812 
0813     sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
0814 }
0815 
0816 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
0817 {
0818     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0819 
0820     return clk_round_rate(pltfm_host->clk, UINT_MAX);
0821 }
0822 
0823 static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim)
0824 {
0825     u32 val;
0826 
0827     val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);
0828     val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK;
0829     val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT;
0830     sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);
0831 }
0832 
0833 static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host)
0834 {
0835     u32 reg;
0836     int err;
0837 
0838     reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);
0839     reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE;
0840     sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);
0841 
0842     /* 1 ms sleep, 5 ms timeout */
0843     err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA,
0844                  reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE),
0845                  1000, 5000);
0846     if (err)
0847         dev_err(mmc_dev(host->mmc),
0848             "HS400 delay line calibration timed out\n");
0849 }
0850 
0851 static void tegra_sdhci_tap_correction(struct sdhci_host *host, u8 thd_up,
0852                        u8 thd_low, u8 fixed_tap)
0853 {
0854     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0855     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
0856     u32 val, tun_status;
0857     u8 word, bit, edge1, tap, window;
0858     bool tap_result;
0859     bool start_fail = false;
0860     bool start_pass = false;
0861     bool end_pass = false;
0862     bool first_fail = false;
0863     bool first_pass = false;
0864     u8 start_pass_tap = 0;
0865     u8 end_pass_tap = 0;
0866     u8 first_fail_tap = 0;
0867     u8 first_pass_tap = 0;
0868     u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE;
0869 
0870     /*
0871      * Read auto-tuned results and extract good valid passing window by
0872      * filtering out un-wanted bubble/partial/merged windows.
0873      */
0874     for (word = 0; word < total_tuning_words; word++) {
0875         val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);
0876         val &= ~SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK;
0877         val |= word;
0878         sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0);
0879         tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0);
0880         bit = 0;
0881         while (bit < TUNING_WORD_BIT_SIZE) {
0882             tap = word * TUNING_WORD_BIT_SIZE + bit;
0883             tap_result = tun_status & (1 << bit);
0884             if (!tap_result && !start_fail) {
0885                 start_fail = true;
0886                 if (!first_fail) {
0887                     first_fail_tap = tap;
0888                     first_fail = true;
0889                 }
0890 
0891             } else if (tap_result && start_fail && !start_pass) {
0892                 start_pass_tap = tap;
0893                 start_pass = true;
0894                 if (!first_pass) {
0895                     first_pass_tap = tap;
0896                     first_pass = true;
0897                 }
0898 
0899             } else if (!tap_result && start_fail && start_pass &&
0900                    !end_pass) {
0901                 end_pass_tap = tap - 1;
0902                 end_pass = true;
0903             } else if (tap_result && start_pass && start_fail &&
0904                    end_pass) {
0905                 window = end_pass_tap - start_pass_tap;
0906                 /* discard merged window and bubble window */
0907                 if (window >= thd_up || window < thd_low) {
0908                     start_pass_tap = tap;
0909                     end_pass = false;
0910                 } else {
0911                     /* set tap at middle of valid window */
0912                     tap = start_pass_tap + window / 2;
0913                     tegra_host->tuned_tap_delay = tap;
0914                     return;
0915                 }
0916             }
0917 
0918             bit++;
0919         }
0920     }
0921 
0922     if (!first_fail) {
0923         WARN(1, "no edge detected, continue with hw tuned delay.\n");
0924     } else if (first_pass) {
0925         /* set tap location at fixed tap relative to the first edge */
0926         edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2;
0927         if (edge1 - 1 > fixed_tap)
0928             tegra_host->tuned_tap_delay = edge1 - fixed_tap;
0929         else
0930             tegra_host->tuned_tap_delay = edge1 + fixed_tap;
0931     }
0932 }
0933 
0934 static void tegra_sdhci_post_tuning(struct sdhci_host *host)
0935 {
0936     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0937     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
0938     const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
0939     u32 avg_tap_dly, val, min_tap_dly, max_tap_dly;
0940     u8 fixed_tap, start_tap, end_tap, window_width;
0941     u8 thdupper, thdlower;
0942     u8 num_iter;
0943     u32 clk_rate_mhz, period_ps, bestcase, worstcase;
0944 
0945     /* retain HW tuned tap to use incase if no correction is needed */
0946     val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
0947     tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >>
0948                       SDHCI_CLOCK_CTRL_TAP_SHIFT;
0949     if (soc_data->min_tap_delay && soc_data->max_tap_delay) {
0950         min_tap_dly = soc_data->min_tap_delay;
0951         max_tap_dly = soc_data->max_tap_delay;
0952         clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC;
0953         period_ps = USEC_PER_SEC / clk_rate_mhz;
0954         bestcase = period_ps / min_tap_dly;
0955         worstcase = period_ps / max_tap_dly;
0956         /*
0957          * Upper and Lower bound thresholds used to detect merged and
0958          * bubble windows
0959          */
0960         thdupper = (2 * worstcase + bestcase) / 2;
0961         thdlower = worstcase / 4;
0962         /*
0963          * fixed tap is used when HW tuning result contains single edge
0964          * and tap is set at fixed tap delay relative to the first edge
0965          */
0966         avg_tap_dly = (period_ps * 2) / (min_tap_dly + max_tap_dly);
0967         fixed_tap = avg_tap_dly / 2;
0968 
0969         val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1);
0970         start_tap = val & SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK;
0971         end_tap = (val >> SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT) &
0972               SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK;
0973         window_width = end_tap - start_tap;
0974         num_iter = host->tuning_loop_count;
0975         /*
0976          * partial window includes edges of the tuning range.
0977          * merged window includes more taps so window width is higher
0978          * than upper threshold.
0979          */
0980         if (start_tap == 0 || (end_tap == (num_iter - 1)) ||
0981             (end_tap == num_iter - 2) || window_width >= thdupper) {
0982             pr_debug("%s: Apply tuning correction\n",
0983                  mmc_hostname(host->mmc));
0984             tegra_sdhci_tap_correction(host, thdupper, thdlower,
0985                            fixed_tap);
0986         }
0987     }
0988 
0989     tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay);
0990 }
0991 
0992 static int tegra_sdhci_execute_hw_tuning(struct mmc_host *mmc, u32 opcode)
0993 {
0994     struct sdhci_host *host = mmc_priv(mmc);
0995     int err;
0996 
0997     err = sdhci_execute_tuning(mmc, opcode);
0998     if (!err && !host->tuning_err)
0999         tegra_sdhci_post_tuning(host);
1000 
1001     return err;
1002 }
1003 
1004 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
1005                       unsigned timing)
1006 {
1007     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1008     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1009     bool set_default_tap = false;
1010     bool set_dqs_trim = false;
1011     bool do_hs400_dll_cal = false;
1012     u8 iter = TRIES_256;
1013     u32 val;
1014 
1015     tegra_host->ddr_signaling = false;
1016     switch (timing) {
1017     case MMC_TIMING_UHS_SDR50:
1018         break;
1019     case MMC_TIMING_UHS_SDR104:
1020     case MMC_TIMING_MMC_HS200:
1021         /* Don't set default tap on tunable modes. */
1022         iter = TRIES_128;
1023         break;
1024     case MMC_TIMING_MMC_HS400:
1025         set_dqs_trim = true;
1026         do_hs400_dll_cal = true;
1027         iter = TRIES_128;
1028         break;
1029     case MMC_TIMING_MMC_DDR52:
1030     case MMC_TIMING_UHS_DDR50:
1031         tegra_host->ddr_signaling = true;
1032         set_default_tap = true;
1033         break;
1034     default:
1035         set_default_tap = true;
1036         break;
1037     }
1038 
1039     val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);
1040     val &= ~(SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK |
1041          SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK |
1042          SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK);
1043     val |= (iter << SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT |
1044         0 << SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT |
1045         1 << SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT);
1046     sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0);
1047     sdhci_writel(host, 0, SDHCI_TEGRA_VNDR_TUN_CTRL1_0);
1048 
1049     host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256;
1050 
1051     sdhci_set_uhs_signaling(host, timing);
1052 
1053     tegra_sdhci_pad_autocalib(host);
1054 
1055     if (tegra_host->tuned_tap_delay && !set_default_tap)
1056         tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay);
1057     else
1058         tegra_sdhci_set_tap(host, tegra_host->default_tap);
1059 
1060     if (set_dqs_trim)
1061         tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim);
1062 
1063     if (do_hs400_dll_cal)
1064         tegra_sdhci_hs400_dll_cal(host);
1065 }
1066 
1067 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
1068 {
1069     unsigned int min, max;
1070 
1071     /*
1072      * Start search for minimum tap value at 10, as smaller values are
1073      * may wrongly be reported as working but fail at higher speeds,
1074      * according to the TRM.
1075      */
1076     min = 10;
1077     while (min < 255) {
1078         tegra_sdhci_set_tap(host, min);
1079         if (!mmc_send_tuning(host->mmc, opcode, NULL))
1080             break;
1081         min++;
1082     }
1083 
1084     /* Find the maximum tap value that still passes. */
1085     max = min + 1;
1086     while (max < 255) {
1087         tegra_sdhci_set_tap(host, max);
1088         if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1089             max--;
1090             break;
1091         }
1092         max++;
1093     }
1094 
1095     /* The TRM states the ideal tap value is at 75% in the passing range. */
1096     tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));
1097 
1098     return mmc_send_tuning(host->mmc, opcode, NULL);
1099 }
1100 
1101 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
1102                            struct mmc_ios *ios)
1103 {
1104     struct sdhci_host *host = mmc_priv(mmc);
1105     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1106     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1107     int ret = 0;
1108 
1109     if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1110         ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
1111         if (ret < 0)
1112             return ret;
1113         ret = sdhci_start_signal_voltage_switch(mmc, ios);
1114     } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
1115         ret = sdhci_start_signal_voltage_switch(mmc, ios);
1116         if (ret < 0)
1117             return ret;
1118         ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
1119     }
1120 
1121     if (tegra_host->pad_calib_required)
1122         tegra_sdhci_pad_autocalib(host);
1123 
1124     return ret;
1125 }
1126 
1127 static int tegra_sdhci_init_pinctrl_info(struct device *dev,
1128                      struct sdhci_tegra *tegra_host)
1129 {
1130     tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev);
1131     if (IS_ERR(tegra_host->pinctrl_sdmmc)) {
1132         dev_dbg(dev, "No pinctrl info, err: %ld\n",
1133             PTR_ERR(tegra_host->pinctrl_sdmmc));
1134         return -1;
1135     }
1136 
1137     tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state(
1138                 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv");
1139     if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) {
1140         if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV)
1141             tegra_host->pinctrl_state_1v8_drv = NULL;
1142     }
1143 
1144     tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state(
1145                 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv");
1146     if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) {
1147         if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV)
1148             tegra_host->pinctrl_state_3v3_drv = NULL;
1149     }
1150 
1151     tegra_host->pinctrl_state_3v3 =
1152         pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3");
1153     if (IS_ERR(tegra_host->pinctrl_state_3v3)) {
1154         dev_warn(dev, "Missing 3.3V pad state, err: %ld\n",
1155              PTR_ERR(tegra_host->pinctrl_state_3v3));
1156         return -1;
1157     }
1158 
1159     tegra_host->pinctrl_state_1v8 =
1160         pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8");
1161     if (IS_ERR(tegra_host->pinctrl_state_1v8)) {
1162         dev_warn(dev, "Missing 1.8V pad state, err: %ld\n",
1163              PTR_ERR(tegra_host->pinctrl_state_1v8));
1164         return -1;
1165     }
1166 
1167     tegra_host->pad_control_available = true;
1168 
1169     return 0;
1170 }
1171 
1172 static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
1173 {
1174     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1175     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1176     const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
1177 
1178     if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
1179         tegra_host->pad_calib_required = true;
1180 }
1181 
1182 static void tegra_cqhci_writel(struct cqhci_host *cq_host, u32 val, int reg)
1183 {
1184     struct mmc_host *mmc = cq_host->mmc;
1185     struct sdhci_host *host = mmc_priv(mmc);
1186     u8 ctrl;
1187     ktime_t timeout;
1188     bool timed_out;
1189 
1190     /*
1191      * During CQE resume/unhalt, CQHCI driver unhalts CQE prior to
1192      * cqhci_host_ops enable where SDHCI DMA and BLOCK_SIZE registers need
1193      * to be re-configured.
1194      * Tegra CQHCI/SDHCI prevents write access to block size register when
1195      * CQE is unhalted. So handling CQE resume sequence here to configure
1196      * SDHCI block registers prior to exiting CQE halt state.
1197      */
1198     if (reg == CQHCI_CTL && !(val & CQHCI_HALT) &&
1199         cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) {
1200         sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
1201         sdhci_cqe_enable(mmc);
1202         writel(val, cq_host->mmio + reg);
1203         timeout = ktime_add_us(ktime_get(), 50);
1204         while (1) {
1205             timed_out = ktime_compare(ktime_get(), timeout) > 0;
1206             ctrl = cqhci_readl(cq_host, CQHCI_CTL);
1207             if (!(ctrl & CQHCI_HALT) || timed_out)
1208                 break;
1209         }
1210         /*
1211          * CQE usually resumes very quick, but incase if Tegra CQE
1212          * doesn't resume retry unhalt.
1213          */
1214         if (timed_out)
1215             writel(val, cq_host->mmio + reg);
1216     } else {
1217         writel(val, cq_host->mmio + reg);
1218     }
1219 }
1220 
1221 static void sdhci_tegra_update_dcmd_desc(struct mmc_host *mmc,
1222                      struct mmc_request *mrq, u64 *data)
1223 {
1224     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(mmc_priv(mmc));
1225     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1226     const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
1227 
1228     if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING &&
1229         mrq->cmd->flags & MMC_RSP_R1B)
1230         *data |= CQHCI_CMD_TIMING(1);
1231 }
1232 
1233 static void sdhci_tegra_cqe_enable(struct mmc_host *mmc)
1234 {
1235     struct cqhci_host *cq_host = mmc->cqe_private;
1236     struct sdhci_host *host = mmc_priv(mmc);
1237     u32 val;
1238 
1239     /*
1240      * Tegra CQHCI/SDMMC design prevents write access to sdhci block size
1241      * register when CQE is enabled and unhalted.
1242      * CQHCI driver enables CQE prior to activation, so disable CQE before
1243      * programming block size in sdhci controller and enable it back.
1244      */
1245     if (!cq_host->activated) {
1246         val = cqhci_readl(cq_host, CQHCI_CFG);
1247         if (val & CQHCI_ENABLE)
1248             cqhci_writel(cq_host, (val & ~CQHCI_ENABLE),
1249                      CQHCI_CFG);
1250         sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
1251         sdhci_cqe_enable(mmc);
1252         if (val & CQHCI_ENABLE)
1253             cqhci_writel(cq_host, val, CQHCI_CFG);
1254     }
1255 
1256     /*
1257      * CMD CRC errors are seen sometimes with some eMMC devices when status
1258      * command is sent during transfer of last data block which is the
1259      * default case as send status command block counter (CBC) is 1.
1260      * Recommended fix to set CBC to 0 allowing send status command only
1261      * when data lines are idle.
1262      */
1263     val = cqhci_readl(cq_host, CQHCI_SSC1);
1264     val &= ~CQHCI_SSC1_CBC_MASK;
1265     cqhci_writel(cq_host, val, CQHCI_SSC1);
1266 }
1267 
1268 static void sdhci_tegra_dumpregs(struct mmc_host *mmc)
1269 {
1270     sdhci_dumpregs(mmc_priv(mmc));
1271 }
1272 
1273 static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask)
1274 {
1275     int cmd_error = 0;
1276     int data_error = 0;
1277 
1278     if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1279         return intmask;
1280 
1281     cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1282 
1283     return 0;
1284 }
1285 
1286 static void tegra_sdhci_set_timeout(struct sdhci_host *host,
1287                     struct mmc_command *cmd)
1288 {
1289     u32 val;
1290 
1291     /*
1292      * HW busy detection timeout is based on programmed data timeout
1293      * counter and maximum supported timeout is 11s which may not be
1294      * enough for long operations like cache flush, sleep awake, erase.
1295      *
1296      * ERASE_TIMEOUT_LIMIT bit of VENDOR_MISC_CTRL register allows
1297      * host controller to wait for busy state until the card is busy
1298      * without HW timeout.
1299      *
1300      * So, use infinite busy wait mode for operations that may take
1301      * more than maximum HW busy timeout of 11s otherwise use finite
1302      * busy wait mode.
1303      */
1304     val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
1305     if (cmd && cmd->busy_timeout >= 11 * MSEC_PER_SEC)
1306         val |= SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT;
1307     else
1308         val &= ~SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT;
1309     sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_MISC_CTRL);
1310 
1311     __sdhci_set_timeout(host, cmd);
1312 }
1313 
1314 static void sdhci_tegra_cqe_pre_enable(struct mmc_host *mmc)
1315 {
1316     struct cqhci_host *cq_host = mmc->cqe_private;
1317     u32 reg;
1318 
1319     reg = cqhci_readl(cq_host, CQHCI_CFG);
1320     reg |= CQHCI_ENABLE;
1321     cqhci_writel(cq_host, reg, CQHCI_CFG);
1322 }
1323 
1324 static void sdhci_tegra_cqe_post_disable(struct mmc_host *mmc)
1325 {
1326     struct cqhci_host *cq_host = mmc->cqe_private;
1327     struct sdhci_host *host = mmc_priv(mmc);
1328     u32 reg;
1329 
1330     reg = cqhci_readl(cq_host, CQHCI_CFG);
1331     reg &= ~CQHCI_ENABLE;
1332     cqhci_writel(cq_host, reg, CQHCI_CFG);
1333     sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1334 }
1335 
1336 static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = {
1337     .write_l    = tegra_cqhci_writel,
1338     .enable = sdhci_tegra_cqe_enable,
1339     .disable = sdhci_cqe_disable,
1340     .dumpregs = sdhci_tegra_dumpregs,
1341     .update_dcmd_desc = sdhci_tegra_update_dcmd_desc,
1342     .pre_enable = sdhci_tegra_cqe_pre_enable,
1343     .post_disable = sdhci_tegra_cqe_post_disable,
1344 };
1345 
1346 static int tegra_sdhci_set_dma_mask(struct sdhci_host *host)
1347 {
1348     struct sdhci_pltfm_host *platform = sdhci_priv(host);
1349     struct sdhci_tegra *tegra = sdhci_pltfm_priv(platform);
1350     const struct sdhci_tegra_soc_data *soc = tegra->soc_data;
1351     struct device *dev = mmc_dev(host->mmc);
1352 
1353     if (soc->dma_mask)
1354         return dma_set_mask_and_coherent(dev, soc->dma_mask);
1355 
1356     return 0;
1357 }
1358 
1359 static const struct sdhci_ops tegra_sdhci_ops = {
1360     .get_ro     = tegra_sdhci_get_ro,
1361     .read_w     = tegra_sdhci_readw,
1362     .write_l    = tegra_sdhci_writel,
1363     .set_clock  = tegra_sdhci_set_clock,
1364     .set_dma_mask = tegra_sdhci_set_dma_mask,
1365     .set_bus_width = sdhci_set_bus_width,
1366     .reset      = tegra_sdhci_reset,
1367     .platform_execute_tuning = tegra_sdhci_execute_tuning,
1368     .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1369     .voltage_switch = tegra_sdhci_voltage_switch,
1370     .get_max_clock = tegra_sdhci_get_max_clock,
1371 };
1372 
1373 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
1374     .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1375           SDHCI_QUIRK_SINGLE_POWER_WRITE |
1376           SDHCI_QUIRK_NO_HISPD_BIT |
1377           SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1378           SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1379     .ops  = &tegra_sdhci_ops,
1380 };
1381 
1382 static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
1383     .pdata = &sdhci_tegra20_pdata,
1384     .dma_mask = DMA_BIT_MASK(32),
1385     .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
1386             NVQUIRK_HAS_ANDROID_GPT_SECTOR |
1387             NVQUIRK_ENABLE_BLOCK_GAP_DET,
1388 };
1389 
1390 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
1391     .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1392           SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1393           SDHCI_QUIRK_SINGLE_POWER_WRITE |
1394           SDHCI_QUIRK_NO_HISPD_BIT |
1395           SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1396           SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1397     .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1398            SDHCI_QUIRK2_BROKEN_HS200 |
1399            /*
1400             * Auto-CMD23 leads to "Got command interrupt 0x00010000 even
1401             * though no command operation was in progress."
1402             *
1403             * The exact reason is unknown, as the same hardware seems
1404             * to support Auto CMD23 on a downstream 3.1 kernel.
1405             */
1406            SDHCI_QUIRK2_ACMD23_BROKEN,
1407     .ops  = &tegra_sdhci_ops,
1408 };
1409 
1410 static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
1411     .pdata = &sdhci_tegra30_pdata,
1412     .dma_mask = DMA_BIT_MASK(32),
1413     .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
1414             NVQUIRK_ENABLE_SDR50 |
1415             NVQUIRK_ENABLE_SDR104 |
1416             NVQUIRK_HAS_ANDROID_GPT_SECTOR |
1417             NVQUIRK_HAS_PADCALIB,
1418 };
1419 
1420 static const struct sdhci_ops tegra114_sdhci_ops = {
1421     .get_ro     = tegra_sdhci_get_ro,
1422     .read_w     = tegra_sdhci_readw,
1423     .write_w    = tegra_sdhci_writew,
1424     .write_l    = tegra_sdhci_writel,
1425     .set_clock  = tegra_sdhci_set_clock,
1426     .set_dma_mask = tegra_sdhci_set_dma_mask,
1427     .set_bus_width = sdhci_set_bus_width,
1428     .reset      = tegra_sdhci_reset,
1429     .platform_execute_tuning = tegra_sdhci_execute_tuning,
1430     .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1431     .voltage_switch = tegra_sdhci_voltage_switch,
1432     .get_max_clock = tegra_sdhci_get_max_clock,
1433 };
1434 
1435 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
1436     .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1437           SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1438           SDHCI_QUIRK_SINGLE_POWER_WRITE |
1439           SDHCI_QUIRK_NO_HISPD_BIT |
1440           SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1441           SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1442     .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1443     .ops  = &tegra114_sdhci_ops,
1444 };
1445 
1446 static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
1447     .pdata = &sdhci_tegra114_pdata,
1448     .dma_mask = DMA_BIT_MASK(32),
1449     .nvquirks = NVQUIRK_HAS_ANDROID_GPT_SECTOR,
1450 };
1451 
1452 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = {
1453     .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1454           SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1455           SDHCI_QUIRK_SINGLE_POWER_WRITE |
1456           SDHCI_QUIRK_NO_HISPD_BIT |
1457           SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1458           SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1459     .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1460     .ops  = &tegra114_sdhci_ops,
1461 };
1462 
1463 static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
1464     .pdata = &sdhci_tegra124_pdata,
1465     .dma_mask = DMA_BIT_MASK(34),
1466     .nvquirks = NVQUIRK_HAS_ANDROID_GPT_SECTOR,
1467 };
1468 
1469 static const struct sdhci_ops tegra210_sdhci_ops = {
1470     .get_ro     = tegra_sdhci_get_ro,
1471     .read_w     = tegra_sdhci_readw,
1472     .write_w    = tegra210_sdhci_writew,
1473     .write_l    = tegra_sdhci_writel,
1474     .set_clock  = tegra_sdhci_set_clock,
1475     .set_dma_mask = tegra_sdhci_set_dma_mask,
1476     .set_bus_width = sdhci_set_bus_width,
1477     .reset      = tegra_sdhci_reset,
1478     .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1479     .voltage_switch = tegra_sdhci_voltage_switch,
1480     .get_max_clock = tegra_sdhci_get_max_clock,
1481     .set_timeout = tegra_sdhci_set_timeout,
1482 };
1483 
1484 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
1485     .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1486           SDHCI_QUIRK_SINGLE_POWER_WRITE |
1487           SDHCI_QUIRK_NO_HISPD_BIT |
1488           SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1489           SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1490     .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1491     .ops  = &tegra210_sdhci_ops,
1492 };
1493 
1494 static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
1495     .pdata = &sdhci_tegra210_pdata,
1496     .dma_mask = DMA_BIT_MASK(34),
1497     .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1498             NVQUIRK_HAS_PADCALIB |
1499             NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
1500             NVQUIRK_ENABLE_SDR50 |
1501             NVQUIRK_ENABLE_SDR104 |
1502             NVQUIRK_HAS_TMCLK,
1503     .min_tap_delay = 106,
1504     .max_tap_delay = 185,
1505 };
1506 
1507 static const struct sdhci_ops tegra186_sdhci_ops = {
1508     .get_ro     = tegra_sdhci_get_ro,
1509     .read_w     = tegra_sdhci_readw,
1510     .write_l    = tegra_sdhci_writel,
1511     .set_clock  = tegra_sdhci_set_clock,
1512     .set_dma_mask = tegra_sdhci_set_dma_mask,
1513     .set_bus_width = sdhci_set_bus_width,
1514     .reset      = tegra_sdhci_reset,
1515     .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1516     .voltage_switch = tegra_sdhci_voltage_switch,
1517     .get_max_clock = tegra_sdhci_get_max_clock,
1518     .irq = sdhci_tegra_cqhci_irq,
1519     .set_timeout = tegra_sdhci_set_timeout,
1520 };
1521 
1522 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
1523     .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1524           SDHCI_QUIRK_SINGLE_POWER_WRITE |
1525           SDHCI_QUIRK_NO_HISPD_BIT |
1526           SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1527           SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1528     .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1529     .ops  = &tegra186_sdhci_ops,
1530 };
1531 
1532 static const struct sdhci_tegra_soc_data soc_data_tegra186 = {
1533     .pdata = &sdhci_tegra186_pdata,
1534     .dma_mask = DMA_BIT_MASK(40),
1535     .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1536             NVQUIRK_HAS_PADCALIB |
1537             NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
1538             NVQUIRK_ENABLE_SDR50 |
1539             NVQUIRK_ENABLE_SDR104 |
1540             NVQUIRK_HAS_TMCLK |
1541             NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING,
1542     .min_tap_delay = 84,
1543     .max_tap_delay = 136,
1544 };
1545 
1546 static const struct sdhci_tegra_soc_data soc_data_tegra194 = {
1547     .pdata = &sdhci_tegra186_pdata,
1548     .dma_mask = DMA_BIT_MASK(39),
1549     .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1550             NVQUIRK_HAS_PADCALIB |
1551             NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
1552             NVQUIRK_ENABLE_SDR50 |
1553             NVQUIRK_ENABLE_SDR104 |
1554             NVQUIRK_HAS_TMCLK,
1555     .min_tap_delay = 96,
1556     .max_tap_delay = 139,
1557 };
1558 
1559 static const struct of_device_id sdhci_tegra_dt_match[] = {
1560     { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
1561     { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
1562     { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
1563     { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
1564     { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
1565     { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
1566     { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
1567     {}
1568 };
1569 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
1570 
1571 static int sdhci_tegra_add_host(struct sdhci_host *host)
1572 {
1573     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1574     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1575     struct cqhci_host *cq_host;
1576     bool dma64;
1577     int ret;
1578 
1579     if (!tegra_host->enable_hwcq)
1580         return sdhci_add_host(host);
1581 
1582     sdhci_enable_v4_mode(host);
1583 
1584     ret = sdhci_setup_host(host);
1585     if (ret)
1586         return ret;
1587 
1588     host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1589 
1590     cq_host = devm_kzalloc(mmc_dev(host->mmc),
1591                 sizeof(*cq_host), GFP_KERNEL);
1592     if (!cq_host) {
1593         ret = -ENOMEM;
1594         goto cleanup;
1595     }
1596 
1597     cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR;
1598     cq_host->ops = &sdhci_tegra_cqhci_ops;
1599 
1600     dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1601     if (dma64)
1602         cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1603 
1604     ret = cqhci_init(cq_host, host->mmc, dma64);
1605     if (ret)
1606         goto cleanup;
1607 
1608     ret = __sdhci_add_host(host);
1609     if (ret)
1610         goto cleanup;
1611 
1612     return 0;
1613 
1614 cleanup:
1615     sdhci_cleanup_host(host);
1616     return ret;
1617 }
1618 
1619 static int sdhci_tegra_probe(struct platform_device *pdev)
1620 {
1621     const struct sdhci_tegra_soc_data *soc_data;
1622     struct sdhci_host *host;
1623     struct sdhci_pltfm_host *pltfm_host;
1624     struct sdhci_tegra *tegra_host;
1625     struct clk *clk;
1626     int rc;
1627 
1628     soc_data = of_device_get_match_data(&pdev->dev);
1629     if (!soc_data)
1630         return -EINVAL;
1631 
1632     host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
1633     if (IS_ERR(host))
1634         return PTR_ERR(host);
1635     pltfm_host = sdhci_priv(host);
1636 
1637     tegra_host = sdhci_pltfm_priv(pltfm_host);
1638     tegra_host->ddr_signaling = false;
1639     tegra_host->pad_calib_required = false;
1640     tegra_host->pad_control_available = false;
1641     tegra_host->soc_data = soc_data;
1642 
1643     if (soc_data->nvquirks & NVQUIRK_HAS_ANDROID_GPT_SECTOR)
1644         host->mmc->caps2 |= MMC_CAP2_ALT_GPT_TEGRA;
1645 
1646     if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) {
1647         rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host);
1648         if (rc == 0)
1649             host->mmc_host_ops.start_signal_voltage_switch =
1650                 sdhci_tegra_start_signal_voltage_switch;
1651     }
1652 
1653     /* Hook to periodically rerun pad calibration */
1654     if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
1655         host->mmc_host_ops.request = tegra_sdhci_request;
1656 
1657     host->mmc_host_ops.hs400_enhanced_strobe =
1658             tegra_sdhci_hs400_enhanced_strobe;
1659 
1660     if (!host->ops->platform_execute_tuning)
1661         host->mmc_host_ops.execute_tuning =
1662                 tegra_sdhci_execute_hw_tuning;
1663 
1664     rc = mmc_of_parse(host->mmc);
1665     if (rc)
1666         goto err_parse_dt;
1667 
1668     if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
1669         host->mmc->caps |= MMC_CAP_1_8V_DDR;
1670 
1671     /* HW busy detection is supported, but R1B responses are required. */
1672     host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
1673 
1674     /* GPIO CD can be set as a wakeup source */
1675     host->mmc->caps |= MMC_CAP_CD_WAKE;
1676 
1677     tegra_sdhci_parse_dt(host);
1678 
1679     tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
1680                              GPIOD_OUT_HIGH);
1681     if (IS_ERR(tegra_host->power_gpio)) {
1682         rc = PTR_ERR(tegra_host->power_gpio);
1683         goto err_power_req;
1684     }
1685 
1686     /*
1687      * Tegra210 has a separate SDMMC_LEGACY_TM clock used for host
1688      * timeout clock and SW can choose TMCLK or SDCLK for hardware
1689      * data timeout through the bit USE_TMCLK_FOR_DATA_TIMEOUT of
1690      * the register SDHCI_TEGRA_VENDOR_SYS_SW_CTRL.
1691      *
1692      * USE_TMCLK_FOR_DATA_TIMEOUT bit default is set to 1 and SDMMC uses
1693      * 12Mhz TMCLK which is advertised in host capability register.
1694      * With TMCLK of 12Mhz provides maximum data timeout period that can
1695      * be achieved is 11s better than using SDCLK for data timeout.
1696      *
1697      * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's
1698      * supporting separate TMCLK.
1699      */
1700 
1701     if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) {
1702         clk = devm_clk_get(&pdev->dev, "tmclk");
1703         if (IS_ERR(clk)) {
1704             rc = PTR_ERR(clk);
1705             if (rc == -EPROBE_DEFER)
1706                 goto err_power_req;
1707 
1708             dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc);
1709             clk = NULL;
1710         }
1711 
1712         clk_set_rate(clk, 12000000);
1713         rc = clk_prepare_enable(clk);
1714         if (rc) {
1715             dev_err(&pdev->dev,
1716                 "failed to enable tmclk: %d\n", rc);
1717             goto err_power_req;
1718         }
1719 
1720         tegra_host->tmclk = clk;
1721     }
1722 
1723     clk = devm_clk_get(mmc_dev(host->mmc), NULL);
1724     if (IS_ERR(clk)) {
1725         rc = dev_err_probe(&pdev->dev, PTR_ERR(clk),
1726                    "failed to get clock\n");
1727         goto err_clk_get;
1728     }
1729     pltfm_host->clk = clk;
1730 
1731     tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev,
1732                                "sdhci");
1733     if (IS_ERR(tegra_host->rst)) {
1734         rc = PTR_ERR(tegra_host->rst);
1735         dev_err(&pdev->dev, "failed to get reset control: %d\n", rc);
1736         goto err_rst_get;
1737     }
1738 
1739     rc = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
1740     if (rc)
1741         goto err_rst_get;
1742 
1743     pm_runtime_enable(&pdev->dev);
1744     rc = pm_runtime_resume_and_get(&pdev->dev);
1745     if (rc)
1746         goto err_pm_get;
1747 
1748     rc = reset_control_assert(tegra_host->rst);
1749     if (rc)
1750         goto err_rst_assert;
1751 
1752     usleep_range(2000, 4000);
1753 
1754     rc = reset_control_deassert(tegra_host->rst);
1755     if (rc)
1756         goto err_rst_assert;
1757 
1758     usleep_range(2000, 4000);
1759 
1760     rc = sdhci_tegra_add_host(host);
1761     if (rc)
1762         goto err_add_host;
1763 
1764     return 0;
1765 
1766 err_add_host:
1767     reset_control_assert(tegra_host->rst);
1768 err_rst_assert:
1769     pm_runtime_put_sync_suspend(&pdev->dev);
1770 err_pm_get:
1771     pm_runtime_disable(&pdev->dev);
1772 err_rst_get:
1773 err_clk_get:
1774     clk_disable_unprepare(tegra_host->tmclk);
1775 err_power_req:
1776 err_parse_dt:
1777     sdhci_pltfm_free(pdev);
1778     return rc;
1779 }
1780 
1781 static int sdhci_tegra_remove(struct platform_device *pdev)
1782 {
1783     struct sdhci_host *host = platform_get_drvdata(pdev);
1784     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1785     struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1786 
1787     sdhci_remove_host(host, 0);
1788 
1789     reset_control_assert(tegra_host->rst);
1790     usleep_range(2000, 4000);
1791 
1792     pm_runtime_put_sync_suspend(&pdev->dev);
1793     pm_runtime_force_suspend(&pdev->dev);
1794 
1795     clk_disable_unprepare(tegra_host->tmclk);
1796     sdhci_pltfm_free(pdev);
1797 
1798     return 0;
1799 }
1800 
1801 static int __maybe_unused sdhci_tegra_runtime_suspend(struct device *dev)
1802 {
1803     struct sdhci_host *host = dev_get_drvdata(dev);
1804     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1805 
1806     clk_disable_unprepare(pltfm_host->clk);
1807 
1808     return 0;
1809 }
1810 
1811 static int __maybe_unused sdhci_tegra_runtime_resume(struct device *dev)
1812 {
1813     struct sdhci_host *host = dev_get_drvdata(dev);
1814     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1815 
1816     return clk_prepare_enable(pltfm_host->clk);
1817 }
1818 
1819 #ifdef CONFIG_PM_SLEEP
1820 static int sdhci_tegra_suspend(struct device *dev)
1821 {
1822     struct sdhci_host *host = dev_get_drvdata(dev);
1823     int ret;
1824 
1825     if (host->mmc->caps2 & MMC_CAP2_CQE) {
1826         ret = cqhci_suspend(host->mmc);
1827         if (ret)
1828             return ret;
1829     }
1830 
1831     ret = sdhci_suspend_host(host);
1832     if (ret) {
1833         cqhci_resume(host->mmc);
1834         return ret;
1835     }
1836 
1837     ret = pm_runtime_force_suspend(dev);
1838     if (ret) {
1839         sdhci_resume_host(host);
1840         cqhci_resume(host->mmc);
1841         return ret;
1842     }
1843 
1844     return mmc_gpio_set_cd_wake(host->mmc, true);
1845 }
1846 
1847 static int sdhci_tegra_resume(struct device *dev)
1848 {
1849     struct sdhci_host *host = dev_get_drvdata(dev);
1850     int ret;
1851 
1852     ret = mmc_gpio_set_cd_wake(host->mmc, false);
1853     if (ret)
1854         return ret;
1855 
1856     ret = pm_runtime_force_resume(dev);
1857     if (ret)
1858         return ret;
1859 
1860     ret = sdhci_resume_host(host);
1861     if (ret)
1862         goto disable_clk;
1863 
1864     if (host->mmc->caps2 & MMC_CAP2_CQE) {
1865         ret = cqhci_resume(host->mmc);
1866         if (ret)
1867             goto suspend_host;
1868     }
1869 
1870     return 0;
1871 
1872 suspend_host:
1873     sdhci_suspend_host(host);
1874 disable_clk:
1875     pm_runtime_force_suspend(dev);
1876     return ret;
1877 }
1878 #endif
1879 
1880 static const struct dev_pm_ops sdhci_tegra_dev_pm_ops = {
1881     SET_RUNTIME_PM_OPS(sdhci_tegra_runtime_suspend, sdhci_tegra_runtime_resume,
1882                NULL)
1883     SET_SYSTEM_SLEEP_PM_OPS(sdhci_tegra_suspend, sdhci_tegra_resume)
1884 };
1885 
1886 static struct platform_driver sdhci_tegra_driver = {
1887     .driver     = {
1888         .name   = "sdhci-tegra",
1889         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1890         .of_match_table = sdhci_tegra_dt_match,
1891         .pm = &sdhci_tegra_dev_pm_ops,
1892     },
1893     .probe      = sdhci_tegra_probe,
1894     .remove     = sdhci_tegra_remove,
1895 };
1896 
1897 module_platform_driver(sdhci_tegra_driver);
1898 
1899 MODULE_DESCRIPTION("SDHCI driver for Tegra");
1900 MODULE_AUTHOR("Google, Inc.");
1901 MODULE_LICENSE("GPL v2");
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