mmc/host/sdhci-pxav2.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2010 Marvell International Ltd.
0004  *      Zhangfei Gao <zhangfei.gao@marvell.com>
0005  *      Kevin Wang <dwang4@marvell.com>
0006  *      Jun Nie <njun@marvell.com>
0007  *      Qiming Wu <wuqm@marvell.com>
0008  *      Philip Rakity <prakity@marvell.com>
0009  */
0010
0011 #include <linux/err.h>
0012 #include <linux/init.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/clk.h>
0015 #include <linux/module.h>
0016 #include <linux/io.h>
0017 #include <linux/mmc/card.h>
0018 #include <linux/mmc/host.h>
0019 #include <linux/platform_data/pxa_sdhci.h>
0020 #include <linux/slab.h>
0021 #include <linux/of.h>
0022 #include <linux/of_device.h>
0023
0024 #include "sdhci.h"
0025 #include "sdhci-pltfm.h"
0026
0027 #define SD_FIFO_PARAM       0xe0
0028 #define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */
0029 #define CLK_GATE_ON     0x0200 /* Disable/enable Clock Gate */
0030 #define CLK_GATE_CTL        0x0100 /* Clock Gate Control */
0031 #define CLK_GATE_SETTING_BITS   (DIS_PAD_SD_CLK_GATE | \
0032         CLK_GATE_ON | CLK_GATE_CTL)
0033
0034 #define SD_CLOCK_BURST_SIZE_SETUP   0xe6
0035 #define SDCLK_SEL_SHIFT     8
0036 #define SDCLK_SEL_MASK      0x3
0037 #define SDCLK_DELAY_SHIFT   10
0038 #define SDCLK_DELAY_MASK    0x3c
0039
0040 #define SD_CE_ATA_2     0xea
0041 #define MMC_CARD        0x1000
0042 #define MMC_WIDTH       0x0100
0043
0044 static void pxav2_reset(struct sdhci_host *host, u8 mask)
0045 {
0046     struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
0047     struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
0048
0049     sdhci_reset(host, mask);
0050
0051     if (mask == SDHCI_RESET_ALL) {
0052         u16 tmp = 0;
0053
0054         /*
0055          * tune timing of read data/command when crc error happen
0056          * no performance impact
0057          */
0058         if (pdata && pdata->clk_delay_sel == 1) {
0059             tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
0060
0061             tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
0062             tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
0063                 << SDCLK_DELAY_SHIFT;
0064             tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
0065             tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
0066
0067             writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
0068         }
0069
0070         if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) {
0071             tmp = readw(host->ioaddr + SD_FIFO_PARAM);
0072             tmp &= ~CLK_GATE_SETTING_BITS;
0073             writew(tmp, host->ioaddr + SD_FIFO_PARAM);
0074         } else {
0075             tmp = readw(host->ioaddr + SD_FIFO_PARAM);
0076             tmp &= ~CLK_GATE_SETTING_BITS;
0077             tmp |= CLK_GATE_SETTING_BITS;
0078             writew(tmp, host->ioaddr + SD_FIFO_PARAM);
0079         }
0080     }
0081 }
0082
0083 static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width)
0084 {
0085     u8 ctrl;
0086     u16 tmp;
0087
0088     ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
0089     tmp = readw(host->ioaddr + SD_CE_ATA_2);
0090     if (width == MMC_BUS_WIDTH_8) {
0091         ctrl &= ~SDHCI_CTRL_4BITBUS;
0092         tmp |= MMC_CARD | MMC_WIDTH;
0093     } else {
0094         tmp &= ~(MMC_CARD | MMC_WIDTH);
0095         if (width == MMC_BUS_WIDTH_4)
0096             ctrl |= SDHCI_CTRL_4BITBUS;
0097         else
0098             ctrl &= ~SDHCI_CTRL_4BITBUS;
0099     }
0100     writew(tmp, host->ioaddr + SD_CE_ATA_2);
0101     writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
0102 }
0103
0104 static const struct sdhci_ops pxav2_sdhci_ops = {
0105     .set_clock     = sdhci_set_clock,
0106     .get_max_clock = sdhci_pltfm_clk_get_max_clock,
0107     .set_bus_width = pxav2_mmc_set_bus_width,
0108     .reset         = pxav2_reset,
0109     .set_uhs_signaling = sdhci_set_uhs_signaling,
0110 };
0111
0112 #ifdef CONFIG_OF
0113 static const struct of_device_id sdhci_pxav2_of_match[] = {
0114     {
0115         .compatible = "mrvl,pxav2-mmc",
0116     },
0117     {},
0118 };
0119 MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match);
0120
0121 static struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
0122 {
0123     struct sdhci_pxa_platdata *pdata;
0124     struct device_node *np = dev->of_node;
0125     u32 bus_width;
0126     u32 clk_delay_cycles;
0127
0128     pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
0129     if (!pdata)
0130         return NULL;
0131
0132     if (of_find_property(np, "non-removable", NULL))
0133         pdata->flags |= PXA_FLAG_CARD_PERMANENT;
0134
0135     of_property_read_u32(np, "bus-width", &bus_width);
0136     if (bus_width == 8)
0137         pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;
0138
0139     of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
0140     if (clk_delay_cycles > 0) {
0141         pdata->clk_delay_sel = 1;
0142         pdata->clk_delay_cycles = clk_delay_cycles;
0143     }
0144
0145     return pdata;
0146 }
0147 #else
0148 static inline struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
0149 {
0150     return NULL;
0151 }
0152 #endif
0153
0154 static int sdhci_pxav2_probe(struct platform_device *pdev)
0155 {
0156     struct sdhci_pltfm_host *pltfm_host;
0157     struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
0158     struct device *dev = &pdev->dev;
0159     struct sdhci_host *host = NULL;
0160     const struct of_device_id *match;
0161
0162     int ret;
0163     struct clk *clk;
0164
0165     host = sdhci_pltfm_init(pdev, NULL, 0);
0166     if (IS_ERR(host))
0167         return PTR_ERR(host);
0168
0169     pltfm_host = sdhci_priv(host);
0170
0171     clk = devm_clk_get(dev, "PXA-SDHCLK");
0172     if (IS_ERR(clk)) {
0173         dev_err(dev, "failed to get io clock\n");
0174         ret = PTR_ERR(clk);
0175         goto free;
0176     }
0177     pltfm_host->clk = clk;
0178     ret = clk_prepare_enable(clk);
0179     if (ret) {
0180         dev_err(&pdev->dev, "failed to enable io clock\n");
0181         goto free;
0182     }
0183
0184     host->quirks = SDHCI_QUIRK_BROKEN_ADMA
0185         | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
0186         | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
0187
0188     match = of_match_device(of_match_ptr(sdhci_pxav2_of_match), &pdev->dev);
0189     if (match) {
0190         pdata = pxav2_get_mmc_pdata(dev);
0191     }
0192     if (pdata) {
0193         if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
0194             /* on-chip device */
0195             host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
0196             host->mmc->caps |= MMC_CAP_NONREMOVABLE;
0197         }
0198
0199         /* If slot design supports 8 bit data, indicate this to MMC. */
0200         if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
0201             host->mmc->caps |= MMC_CAP_8_BIT_DATA;
0202
0203         if (pdata->quirks)
0204             host->quirks |= pdata->quirks;
0205         if (pdata->host_caps)
0206             host->mmc->caps |= pdata->host_caps;
0207         if (pdata->pm_caps)
0208             host->mmc->pm_caps |= pdata->pm_caps;
0209     }
0210
0211     host->ops = &pxav2_sdhci_ops;
0212
0213     ret = sdhci_add_host(host);
0214     if (ret)
0215         goto disable_clk;
0216
0217     return 0;
0218
0219 disable_clk:
0220     clk_disable_unprepare(clk);
0221 free:
0222     sdhci_pltfm_free(pdev);
0223     return ret;
0224 }
0225
0226 static struct platform_driver sdhci_pxav2_driver = {
0227     .driver     = {
0228         .name   = "sdhci-pxav2",
0229         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0230         .of_match_table = of_match_ptr(sdhci_pxav2_of_match),
0231         .pm = &sdhci_pltfm_pmops,
0232     },
0233     .probe      = sdhci_pxav2_probe,
0234     .remove     = sdhci_pltfm_unregister,
0235 };
0236
0237 module_platform_driver(sdhci_pxav2_driver);
0238
0239 MODULE_DESCRIPTION("SDHCI driver for pxav2");
0240 MODULE_AUTHOR("Marvell International Ltd.");
0241 MODULE_LICENSE("GPL v2");
0242