mmc/host/sdhci-pltfm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2010 MontaVista Software, LLC.
0004  *
0005  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
0006  */
0007
0008 #ifndef _DRIVERS_MMC_SDHCI_PLTFM_H
0009 #define _DRIVERS_MMC_SDHCI_PLTFM_H
0010
0011 #include <linux/clk.h>
0012 #include <linux/platform_device.h>
0013 #include "sdhci.h"
0014
0015 struct sdhci_pltfm_data {
0016     const struct sdhci_ops *ops;
0017     unsigned int quirks;
0018     unsigned int quirks2;
0019 };
0020
0021 struct sdhci_pltfm_host {
0022     struct clk *clk;
0023
0024     /* migrate from sdhci_of_host */
0025     unsigned int clock;
0026     u16 xfer_mode_shadow;
0027
0028     unsigned long private[] ____cacheline_aligned;
0029 };
0030
0031 #ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
0032 /*
0033  * These accessors are designed for big endian hosts doing I/O to
0034  * little endian controllers incorporating a 32-bit hardware byte swapper.
0035  */
0036 static inline u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg)
0037 {
0038     return in_be32(host->ioaddr + reg);
0039 }
0040
0041 static inline u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg)
0042 {
0043     return in_be16(host->ioaddr + (reg ^ 0x2));
0044 }
0045
0046 static inline u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg)
0047 {
0048     return in_8(host->ioaddr + (reg ^ 0x3));
0049 }
0050
0051 static inline void sdhci_be32bs_writel(struct sdhci_host *host,
0052                        u32 val, int reg)
0053 {
0054     out_be32(host->ioaddr + reg, val);
0055 }
0056
0057 static inline void sdhci_be32bs_writew(struct sdhci_host *host,
0058                        u16 val, int reg)
0059 {
0060     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0061     int base = reg & ~0x3;
0062     int shift = (reg & 0x2) * 8;
0063
0064     switch (reg) {
0065     case SDHCI_TRANSFER_MODE:
0066         /*
0067          * Postpone this write, we must do it together with a
0068          * command write that is down below.
0069          */
0070         pltfm_host->xfer_mode_shadow = val;
0071         return;
0072     case SDHCI_COMMAND:
0073         sdhci_be32bs_writel(host,
0074                     val << 16 | pltfm_host->xfer_mode_shadow,
0075                     SDHCI_TRANSFER_MODE);
0076         return;
0077     }
0078     clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
0079 }
0080
0081 static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)
0082 {
0083     int base = reg & ~0x3;
0084     int shift = (reg & 0x3) * 8;
0085
0086     clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
0087 }
0088 #endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */
0089
0090 void sdhci_get_property(struct platform_device *pdev);
0091
0092 static inline void sdhci_get_of_property(struct platform_device *pdev)
0093 {
0094     return sdhci_get_property(pdev);
0095 }
0096
0097 extern struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
0098                       const struct sdhci_pltfm_data *pdata,
0099                       size_t priv_size);
0100 extern void sdhci_pltfm_free(struct platform_device *pdev);
0101
0102 extern int sdhci_pltfm_register(struct platform_device *pdev,
0103                 const struct sdhci_pltfm_data *pdata,
0104                 size_t priv_size);
0105 extern int sdhci_pltfm_unregister(struct platform_device *pdev);
0106
0107 extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host);
0108
0109 static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host)
0110 {
0111     return host->private;
0112 }
0113
0114 extern const struct dev_pm_ops sdhci_pltfm_pmops;
0115 #ifdef CONFIG_PM_SLEEP
0116 int sdhci_pltfm_suspend(struct device *dev);
0117 int sdhci_pltfm_resume(struct device *dev);
0118 #else
0119 static inline int sdhci_pltfm_suspend(struct device *dev) { return 0; }
0120 static inline int sdhci_pltfm_resume(struct device *dev) { return 0; }
0121 #endif
0122
0123 #endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */