mmc/host/sdhci-pci.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __SDHCI_PCI_H
0003 #define __SDHCI_PCI_H
0004
0005 /*
0006  * PCI device IDs, sub IDs
0007  */
0008
0009 #define PCI_DEVICE_ID_O2_SDS0       0x8420
0010 #define PCI_DEVICE_ID_O2_SDS1       0x8421
0011 #define PCI_DEVICE_ID_O2_FUJIN2     0x8520
0012 #define PCI_DEVICE_ID_O2_SEABIRD0   0x8620
0013 #define PCI_DEVICE_ID_O2_SEABIRD1   0x8621
0014
0015 #define PCI_DEVICE_ID_INTEL_PCH_SDIO0   0x8809
0016 #define PCI_DEVICE_ID_INTEL_PCH_SDIO1   0x880a
0017 #define PCI_DEVICE_ID_INTEL_BYT_EMMC    0x0f14
0018 #define PCI_DEVICE_ID_INTEL_BYT_SDIO    0x0f15
0019 #define PCI_DEVICE_ID_INTEL_BYT_SD  0x0f16
0020 #define PCI_DEVICE_ID_INTEL_BYT_EMMC2   0x0f50
0021 #define PCI_DEVICE_ID_INTEL_BSW_EMMC    0x2294
0022 #define PCI_DEVICE_ID_INTEL_BSW_SDIO    0x2295
0023 #define PCI_DEVICE_ID_INTEL_BSW_SD  0x2296
0024 #define PCI_DEVICE_ID_INTEL_MRFLD_MMC   0x1190
0025 #define PCI_DEVICE_ID_INTEL_CLV_SDIO0   0x08f9
0026 #define PCI_DEVICE_ID_INTEL_CLV_SDIO1   0x08fa
0027 #define PCI_DEVICE_ID_INTEL_CLV_SDIO2   0x08fb
0028 #define PCI_DEVICE_ID_INTEL_CLV_EMMC0   0x08e5
0029 #define PCI_DEVICE_ID_INTEL_CLV_EMMC1   0x08e6
0030 #define PCI_DEVICE_ID_INTEL_QRK_SD  0x08A7
0031 #define PCI_DEVICE_ID_INTEL_SPT_EMMC    0x9d2b
0032 #define PCI_DEVICE_ID_INTEL_SPT_SDIO    0x9d2c
0033 #define PCI_DEVICE_ID_INTEL_SPT_SD  0x9d2d
0034 #define PCI_DEVICE_ID_INTEL_DNV_EMMC    0x19db
0035 #define PCI_DEVICE_ID_INTEL_CDF_EMMC    0x18db
0036 #define PCI_DEVICE_ID_INTEL_BXT_SD  0x0aca
0037 #define PCI_DEVICE_ID_INTEL_BXT_EMMC    0x0acc
0038 #define PCI_DEVICE_ID_INTEL_BXT_SDIO    0x0ad0
0039 #define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca
0040 #define PCI_DEVICE_ID_INTEL_BXTM_EMMC   0x1acc
0041 #define PCI_DEVICE_ID_INTEL_BXTM_SDIO   0x1ad0
0042 #define PCI_DEVICE_ID_INTEL_APL_SD  0x5aca
0043 #define PCI_DEVICE_ID_INTEL_APL_EMMC    0x5acc
0044 #define PCI_DEVICE_ID_INTEL_APL_SDIO    0x5ad0
0045 #define PCI_DEVICE_ID_INTEL_GLK_SD  0x31ca
0046 #define PCI_DEVICE_ID_INTEL_GLK_EMMC    0x31cc
0047 #define PCI_DEVICE_ID_INTEL_GLK_SDIO    0x31d0
0048 #define PCI_DEVICE_ID_INTEL_CNP_EMMC    0x9dc4
0049 #define PCI_DEVICE_ID_INTEL_CNP_SD  0x9df5
0050 #define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375
0051 #define PCI_DEVICE_ID_INTEL_ICP_EMMC    0x34c4
0052 #define PCI_DEVICE_ID_INTEL_ICP_SD  0x34f8
0053 #define PCI_DEVICE_ID_INTEL_EHL_EMMC    0x4b47
0054 #define PCI_DEVICE_ID_INTEL_EHL_SD  0x4b48
0055 #define PCI_DEVICE_ID_INTEL_CML_EMMC    0x02c4
0056 #define PCI_DEVICE_ID_INTEL_CML_SD  0x02f5
0057 #define PCI_DEVICE_ID_INTEL_CMLH_SD 0x06f5
0058 #define PCI_DEVICE_ID_INTEL_JSL_EMMC    0x4dc4
0059 #define PCI_DEVICE_ID_INTEL_JSL_SD  0x4df8
0060 #define PCI_DEVICE_ID_INTEL_LKF_EMMC    0x98c4
0061 #define PCI_DEVICE_ID_INTEL_LKF_SD  0x98f8
0062 #define PCI_DEVICE_ID_INTEL_ADL_EMMC    0x54c4
0063
0064 #define PCI_DEVICE_ID_SYSKONNECT_8000   0x8000
0065 #define PCI_DEVICE_ID_VIA_95D0      0x95d0
0066 #define PCI_DEVICE_ID_REALTEK_5250  0x5250
0067
0068 #define PCI_SUBDEVICE_ID_NI_7884    0x7884
0069 #define PCI_SUBDEVICE_ID_NI_78E3    0x78e3
0070
0071 #define PCI_VENDOR_ID_ARASAN        0x16e6
0072 #define PCI_DEVICE_ID_ARASAN_PHY_EMMC   0x0670
0073
0074 #define PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC 0xc202
0075
0076 #define PCI_DEVICE_ID_GLI_9755      0x9755
0077 #define PCI_DEVICE_ID_GLI_9750      0x9750
0078 #define PCI_DEVICE_ID_GLI_9763E     0xe763
0079
0080 /*
0081  * PCI device class and mask
0082  */
0083
0084 #define SYSTEM_SDHCI            (PCI_CLASS_SYSTEM_SDHCI << 8)
0085 #define PCI_CLASS_MASK          0xFFFF00
0086
0087 /*
0088  * Macros for PCI device-description
0089  */
0090
0091 #define _PCI_VEND(vend) PCI_VENDOR_ID_##vend
0092 #define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev
0093 #define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev
0094
0095 #define SDHCI_PCI_DEVICE(vend, dev, cfg) { \
0096     .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
0097     .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
0098     .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
0099 }
0100
0101 #define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \
0102     .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
0103     .subvendor = _PCI_VEND(subvend), \
0104     .subdevice = _PCI_SUBDEV(subvend, subdev), \
0105     .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
0106 }
0107
0108 #define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \
0109     .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \
0110     .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
0111     .class = (cl), .class_mask = (cl_msk), \
0112     .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
0113 }
0114
0115 /*
0116  * PCI registers
0117  */
0118
0119 #define PCI_SDHCI_IFPIO         0x00
0120 #define PCI_SDHCI_IFDMA         0x01
0121 #define PCI_SDHCI_IFVENDOR      0x02
0122
0123 #define PCI_SLOT_INFO           0x40    /* 8 bits */
0124 #define  PCI_SLOT_INFO_SLOTS(x)     ((x >> 4) & 7)
0125 #define  PCI_SLOT_INFO_FIRST_BAR_MASK   0x07
0126
0127 #define MAX_SLOTS           8
0128
0129 struct sdhci_pci_chip;
0130 struct sdhci_pci_slot;
0131
0132 struct sdhci_pci_fixes {
0133     unsigned int        quirks;
0134     unsigned int        quirks2;
0135     bool            allow_runtime_pm;
0136     bool            own_cd_for_runtime_pm;
0137
0138     int         (*probe) (struct sdhci_pci_chip *);
0139
0140     int         (*probe_slot) (struct sdhci_pci_slot *);
0141     int         (*add_host) (struct sdhci_pci_slot *);
0142     void            (*remove_slot) (struct sdhci_pci_slot *, int);
0143
0144 #ifdef CONFIG_PM_SLEEP
0145     int         (*suspend) (struct sdhci_pci_chip *);
0146     int         (*resume) (struct sdhci_pci_chip *);
0147 #endif
0148 #ifdef CONFIG_PM
0149     int         (*runtime_suspend) (struct sdhci_pci_chip *);
0150     int         (*runtime_resume) (struct sdhci_pci_chip *);
0151 #endif
0152
0153     const struct sdhci_ops  *ops;
0154     size_t          priv_size;
0155 };
0156
0157 struct sdhci_pci_slot {
0158     struct sdhci_pci_chip   *chip;
0159     struct sdhci_host   *host;
0160
0161     int         cd_idx;
0162     bool            cd_override_level;
0163
0164     void (*hw_reset)(struct sdhci_host *host);
0165     unsigned long       private[] ____cacheline_aligned;
0166 };
0167
0168 struct sdhci_pci_chip {
0169     struct pci_dev      *pdev;
0170
0171     unsigned int        quirks;
0172     unsigned int        quirks2;
0173     bool            allow_runtime_pm;
0174     bool            pm_retune;
0175     bool            rpm_retune;
0176     const struct sdhci_pci_fixes *fixes;
0177
0178     int         num_slots;  /* Slots on controller */
0179     struct sdhci_pci_slot   *slots[MAX_SLOTS]; /* Pointers to host slots */
0180 };
0181
0182 static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot)
0183 {
0184     return (void *)slot->private;
0185 }
0186
0187 #ifdef CONFIG_PM_SLEEP
0188 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip);
0189 #endif
0190 int sdhci_pci_enable_dma(struct sdhci_host *host);
0191
0192 extern const struct sdhci_pci_fixes sdhci_arasan;
0193 extern const struct sdhci_pci_fixes sdhci_snps;
0194 extern const struct sdhci_pci_fixes sdhci_o2;
0195 extern const struct sdhci_pci_fixes sdhci_gl9750;
0196 extern const struct sdhci_pci_fixes sdhci_gl9755;
0197 extern const struct sdhci_pci_fixes sdhci_gl9763e;
0198
0199 #endif /* __SDHCI_PCI_H */