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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2013 BayHub Technology Ltd.
0004  *
0005  * Authors: Peter Guo <peter.guo@bayhubtech.com>
0006  *          Adam Lee <adam.lee@canonical.com>
0007  *          Ernest Zhang <ernest.zhang@bayhubtech.com>
0008  */
0009 
0010 #include <linux/pci.h>
0011 #include <linux/mmc/host.h>
0012 #include <linux/mmc/mmc.h>
0013 #include <linux/delay.h>
0014 #include <linux/iopoll.h>
0015 #include <linux/bitfield.h>
0016 
0017 #include "sdhci.h"
0018 #include "sdhci-pci.h"
0019 
0020 /*
0021  * O2Micro device registers
0022  */
0023 
0024 #define O2_SD_MISC_REG5     0x64
0025 #define O2_SD_LD0_CTRL      0x68
0026 #define O2_SD_DEV_CTRL      0x88
0027 #define O2_SD_LOCK_WP       0xD3
0028 #define O2_SD_TEST_REG      0xD4
0029 #define O2_SD_FUNC_REG0     0xDC
0030 #define O2_SD_MULTI_VCC3V   0xEE
0031 #define O2_SD_CLKREQ        0xEC
0032 #define O2_SD_CAPS      0xE0
0033 #define O2_SD_ADMA1     0xE2
0034 #define O2_SD_ADMA2     0xE7
0035 #define O2_SD_INF_MOD       0xF1
0036 #define O2_SD_MISC_CTRL4    0xFC
0037 #define O2_SD_MISC_CTRL     0x1C0
0038 #define O2_SD_PWR_FORCE_L0  0x0002
0039 #define O2_SD_TUNING_CTRL   0x300
0040 #define O2_SD_PLL_SETTING   0x304
0041 #define O2_SD_MISC_SETTING  0x308
0042 #define O2_SD_CLK_SETTING   0x328
0043 #define O2_SD_CAP_REG2      0x330
0044 #define O2_SD_CAP_REG0      0x334
0045 #define O2_SD_UHS1_CAP_SETTING  0x33C
0046 #define O2_SD_DELAY_CTRL    0x350
0047 #define O2_SD_OUTPUT_CLK_SOURCE_SWITCH  0x354
0048 #define O2_SD_UHS2_L1_CTRL  0x35C
0049 #define O2_SD_FUNC_REG3     0x3E0
0050 #define O2_SD_FUNC_REG4     0x3E4
0051 #define O2_SD_LED_ENABLE    BIT(6)
0052 #define O2_SD_FREG0_LEDOFF  BIT(13)
0053 #define O2_SD_SEL_DLL       BIT(16)
0054 #define O2_SD_FREG4_ENABLE_CLK_SET  BIT(22)
0055 #define O2_SD_PHASE_MASK    GENMASK(23, 20)
0056 #define O2_SD_FIX_PHASE     FIELD_PREP(O2_SD_PHASE_MASK, 0x9)
0057 
0058 #define O2_SD_VENDOR_SETTING    0x110
0059 #define O2_SD_VENDOR_SETTING2   0x1C8
0060 #define O2_SD_HW_TUNING_DISABLE BIT(4)
0061 
0062 #define O2_PLL_DLL_WDT_CONTROL1 0x1CC
0063 #define  O2_PLL_FORCE_ACTIVE    BIT(18)
0064 #define  O2_PLL_LOCK_STATUS BIT(14)
0065 #define  O2_PLL_SOFT_RESET  BIT(12)
0066 #define  O2_DLL_LOCK_STATUS BIT(11)
0067 
0068 #define O2_SD_DETECT_SETTING 0x324
0069 
0070 static const u32 dmdn_table[] = {0x2B1C0000,
0071     0x2C1A0000, 0x371B0000, 0x35100000};
0072 #define DMDN_SZ ARRAY_SIZE(dmdn_table)
0073 
0074 struct o2_host {
0075     u8 dll_adjust_count;
0076 };
0077 
0078 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
0079 {
0080     ktime_t timeout;
0081     u32 scratch32;
0082 
0083     /* Wait max 50 ms */
0084     timeout = ktime_add_ms(ktime_get(), 50);
0085     while (1) {
0086         bool timedout = ktime_after(ktime_get(), timeout);
0087 
0088         scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
0089         if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
0090             == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
0091             break;
0092 
0093         if (timedout) {
0094             pr_err("%s: Card Detect debounce never finished.\n",
0095                    mmc_hostname(host->mmc));
0096             sdhci_dumpregs(host);
0097             return;
0098         }
0099         udelay(10);
0100     }
0101 }
0102 
0103 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
0104 {
0105     ktime_t timeout;
0106     u16 scratch;
0107     u32 scratch32;
0108 
0109     /* PLL software reset */
0110     scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
0111     scratch32 |= O2_PLL_SOFT_RESET;
0112     sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
0113     udelay(1);
0114     scratch32 &= ~(O2_PLL_SOFT_RESET);
0115     sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
0116 
0117     /* PLL force active */
0118     scratch32 |= O2_PLL_FORCE_ACTIVE;
0119     sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
0120 
0121     /* Wait max 20 ms */
0122     timeout = ktime_add_ms(ktime_get(), 20);
0123     while (1) {
0124         bool timedout = ktime_after(ktime_get(), timeout);
0125 
0126         scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
0127         if (scratch & O2_PLL_LOCK_STATUS)
0128             break;
0129         if (timedout) {
0130             pr_err("%s: Internal clock never stabilised.\n",
0131                    mmc_hostname(host->mmc));
0132             sdhci_dumpregs(host);
0133             goto out;
0134         }
0135         udelay(10);
0136     }
0137 
0138     /* Wait for card detect finish */
0139     udelay(1);
0140     sdhci_o2_wait_card_detect_stable(host);
0141 
0142 out:
0143     /* Cancel PLL force active */
0144     scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
0145     scratch32 &= ~O2_PLL_FORCE_ACTIVE;
0146     sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
0147 }
0148 
0149 static int sdhci_o2_get_cd(struct mmc_host *mmc)
0150 {
0151     struct sdhci_host *host = mmc_priv(mmc);
0152 
0153     if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
0154         sdhci_o2_enable_internal_clock(host);
0155     else
0156         sdhci_o2_wait_card_detect_stable(host);
0157 
0158     return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
0159 }
0160 
0161 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
0162 {
0163     u32 scratch_32;
0164 
0165     pci_read_config_dword(chip->pdev,
0166                   O2_SD_PLL_SETTING, &scratch_32);
0167 
0168     scratch_32 &= 0x0000FFFF;
0169     scratch_32 |= value;
0170 
0171     pci_write_config_dword(chip->pdev,
0172                    O2_SD_PLL_SETTING, scratch_32);
0173 }
0174 
0175 static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
0176 {
0177     return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
0178 }
0179 
0180 /*
0181  * This function is used to detect dll lock status.
0182  * Since the dll lock status bit will toggle randomly
0183  * with very short interval which needs to be polled
0184  * as fast as possible. Set sleep_us as 1 microsecond.
0185  */
0186 static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
0187 {
0188     u32 scratch32 = 0;
0189 
0190     return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
0191         scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000);
0192 }
0193 
0194 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
0195 {
0196     u16 reg;
0197 
0198     /* enable hardware tuning */
0199     reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
0200     reg &= ~O2_SD_HW_TUNING_DISABLE;
0201     sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
0202 }
0203 
0204 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
0205 {
0206     int i;
0207 
0208     sdhci_send_tuning(host, opcode);
0209 
0210     for (i = 0; i < 150; i++) {
0211         u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
0212 
0213         if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
0214             if (ctrl & SDHCI_CTRL_TUNED_CLK) {
0215                 host->tuning_done = true;
0216                 return;
0217             }
0218             pr_warn("%s: HW tuning failed !\n",
0219                 mmc_hostname(host->mmc));
0220             break;
0221         }
0222 
0223         mdelay(1);
0224     }
0225 
0226     pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
0227         mmc_hostname(host->mmc));
0228     sdhci_reset_tuning(host);
0229 }
0230 
0231 /*
0232  * This function is used to fix o2 dll shift issue.
0233  * It isn't necessary to detect card present before recovery.
0234  * Firstly, it is used by bht emmc card, which is embedded.
0235  * Second, before call recovery card present will be detected
0236  * outside of the execute tuning function.
0237  */
0238 static int sdhci_o2_dll_recovery(struct sdhci_host *host)
0239 {
0240     int ret = 0;
0241     u8 scratch_8 = 0;
0242     u32 scratch_32 = 0;
0243     struct sdhci_pci_slot *slot = sdhci_priv(host);
0244     struct sdhci_pci_chip *chip = slot->chip;
0245     struct o2_host *o2_host = sdhci_pci_priv(slot);
0246 
0247     /* UnLock WP */
0248     pci_read_config_byte(chip->pdev,
0249             O2_SD_LOCK_WP, &scratch_8);
0250     scratch_8 &= 0x7f;
0251     pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
0252     while (o2_host->dll_adjust_count < DMDN_SZ && !ret) {
0253         /* Disable clock */
0254         sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
0255 
0256         /* PLL software reset */
0257         scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
0258         scratch_32 |= O2_PLL_SOFT_RESET;
0259         sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
0260 
0261         pci_read_config_dword(chip->pdev,
0262                         O2_SD_FUNC_REG4,
0263                         &scratch_32);
0264         /* Enable Base Clk setting change */
0265         scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
0266         pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
0267         o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]);
0268 
0269         /* Enable internal clock */
0270         scratch_8 = SDHCI_CLOCK_INT_EN;
0271         sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
0272 
0273         if (sdhci_o2_get_cd(host->mmc)) {
0274             /*
0275              * need wait at least 5ms for dll status stable,
0276              * after enable internal clock
0277              */
0278             usleep_range(5000, 6000);
0279             if (sdhci_o2_wait_dll_detect_lock(host)) {
0280                 scratch_8 |= SDHCI_CLOCK_CARD_EN;
0281                 sdhci_writeb(host, scratch_8,
0282                     SDHCI_CLOCK_CONTROL);
0283                 ret = 1;
0284             } else {
0285                 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n",
0286                     mmc_hostname(host->mmc),
0287                     o2_host->dll_adjust_count);
0288             }
0289         } else {
0290             pr_err("%s: card present detect failed.\n",
0291                 mmc_hostname(host->mmc));
0292             break;
0293         }
0294 
0295         o2_host->dll_adjust_count++;
0296     }
0297     if (!ret && o2_host->dll_adjust_count == DMDN_SZ)
0298         pr_err("%s: DLL adjust over max times\n",
0299         mmc_hostname(host->mmc));
0300     /* Lock WP */
0301     pci_read_config_byte(chip->pdev,
0302                    O2_SD_LOCK_WP, &scratch_8);
0303     scratch_8 |= 0x80;
0304     pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
0305     return ret;
0306 }
0307 
0308 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
0309 {
0310     struct sdhci_host *host = mmc_priv(mmc);
0311     struct sdhci_pci_slot *slot = sdhci_priv(host);
0312     struct sdhci_pci_chip *chip = slot->chip;
0313     int current_bus_width = 0;
0314     u32 scratch32 = 0;
0315     u16 scratch = 0;
0316     u8  scratch_8 = 0;
0317     u32 reg_val;
0318 
0319     /*
0320      * This handler only implements the eMMC tuning that is specific to
0321      * this controller.  Fall back to the standard method for other TIMING.
0322      */
0323     if ((host->timing != MMC_TIMING_MMC_HS200) &&
0324         (host->timing != MMC_TIMING_UHS_SDR104))
0325         return sdhci_execute_tuning(mmc, opcode);
0326 
0327     if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) &&
0328             (opcode != MMC_SEND_TUNING_BLOCK)))
0329         return -EINVAL;
0330 
0331     /* Force power mode enter L0 */
0332     scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
0333     scratch |= O2_SD_PWR_FORCE_L0;
0334     sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
0335 
0336     /* Stop clk */
0337     reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
0338     reg_val &= ~SDHCI_CLOCK_CARD_EN;
0339     sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
0340 
0341     /* UnLock WP */
0342     pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
0343     scratch_8 &= 0x7f;
0344     pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
0345 
0346     /* Set pcr 0x354[16] to choose dll clock, and set the default phase */
0347     pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &reg_val);
0348     reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
0349     reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
0350     pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
0351 
0352     /* Lock WP */
0353     pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
0354     scratch_8 |= 0x80;
0355     pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
0356 
0357     /* Start clk */
0358     reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
0359     reg_val |= SDHCI_CLOCK_CARD_EN;
0360     sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
0361 
0362     /* wait DLL lock, timeout value 5ms */
0363     if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
0364         scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000))
0365         pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n",
0366                 mmc_hostname(host->mmc));
0367     /*
0368      * Judge the tuning reason, whether caused by dll shift
0369      * If cause by dll shift, should call sdhci_o2_dll_recovery
0370      */
0371     if (!sdhci_o2_wait_dll_detect_lock(host))
0372         if (!sdhci_o2_dll_recovery(host)) {
0373             pr_err("%s: o2 dll recovery failed\n",
0374                 mmc_hostname(host->mmc));
0375             return -EINVAL;
0376         }
0377     /*
0378      * o2 sdhci host didn't support 8bit emmc tuning
0379      */
0380     if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
0381         current_bus_width = mmc->ios.bus_width;
0382         mmc->ios.bus_width = MMC_BUS_WIDTH_4;
0383         sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
0384     }
0385 
0386     sdhci_o2_set_tuning_mode(host);
0387 
0388     sdhci_start_tuning(host);
0389 
0390     __sdhci_o2_execute_tuning(host, opcode);
0391 
0392     sdhci_end_tuning(host);
0393 
0394     if (current_bus_width == MMC_BUS_WIDTH_8) {
0395         mmc->ios.bus_width = MMC_BUS_WIDTH_8;
0396         sdhci_set_bus_width(host, current_bus_width);
0397     }
0398 
0399     /* Cancel force power mode enter L0 */
0400     scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
0401     scratch &= ~(O2_SD_PWR_FORCE_L0);
0402     sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
0403 
0404     sdhci_reset(host, SDHCI_RESET_CMD);
0405     sdhci_reset(host, SDHCI_RESET_DATA);
0406 
0407     host->flags &= ~SDHCI_HS400_TUNING;
0408     return 0;
0409 }
0410 
0411 static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
0412 {
0413     int ret;
0414     u32 scratch_32;
0415 
0416     /* Set led of SD host function enable */
0417     ret = pci_read_config_dword(chip->pdev,
0418                     O2_SD_FUNC_REG0, &scratch_32);
0419     if (ret)
0420         return;
0421 
0422     scratch_32 &= ~O2_SD_FREG0_LEDOFF;
0423     pci_write_config_dword(chip->pdev,
0424                    O2_SD_FUNC_REG0, scratch_32);
0425 
0426     ret = pci_read_config_dword(chip->pdev,
0427                     O2_SD_TEST_REG, &scratch_32);
0428     if (ret)
0429         return;
0430 
0431     scratch_32 |= O2_SD_LED_ENABLE;
0432     pci_write_config_dword(chip->pdev,
0433                    O2_SD_TEST_REG, scratch_32);
0434 }
0435 
0436 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
0437 {
0438     u32 scratch_32;
0439     int ret;
0440     /* Improve write performance for SD3.0 */
0441     ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
0442     if (ret)
0443         return;
0444     scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
0445     pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
0446 
0447     /* Enable Link abnormal reset generating Reset */
0448     ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
0449     if (ret)
0450         return;
0451     scratch_32 &= ~((1 << 19) | (1 << 11));
0452     scratch_32 |= (1 << 10);
0453     pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
0454 
0455     /* set card power over current protection */
0456     ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
0457     if (ret)
0458         return;
0459     scratch_32 |= (1 << 4);
0460     pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
0461 
0462     /* adjust the output delay for SD mode */
0463     pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
0464 
0465     /* Set the output voltage setting of Aux 1.2v LDO */
0466     ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
0467     if (ret)
0468         return;
0469     scratch_32 &= ~(3 << 12);
0470     pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
0471 
0472     /* Set Max power supply capability of SD host */
0473     ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
0474     if (ret)
0475         return;
0476     scratch_32 &= ~(0x01FE);
0477     scratch_32 |= 0x00CC;
0478     pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
0479     /* Set DLL Tuning Window */
0480     ret = pci_read_config_dword(chip->pdev,
0481                     O2_SD_TUNING_CTRL, &scratch_32);
0482     if (ret)
0483         return;
0484     scratch_32 &= ~(0x000000FF);
0485     scratch_32 |= 0x00000066;
0486     pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
0487 
0488     /* Set UHS2 T_EIDLE */
0489     ret = pci_read_config_dword(chip->pdev,
0490                     O2_SD_UHS2_L1_CTRL, &scratch_32);
0491     if (ret)
0492         return;
0493     scratch_32 &= ~(0x000000FC);
0494     scratch_32 |= 0x00000084;
0495     pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
0496 
0497     /* Set UHS2 Termination */
0498     ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
0499     if (ret)
0500         return;
0501     scratch_32 &= ~((1 << 21) | (1 << 30));
0502 
0503     pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
0504 
0505     /* Set L1 Entrance Timer */
0506     ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
0507     if (ret)
0508         return;
0509     scratch_32 &= ~(0xf0000000);
0510     scratch_32 |= 0x30000000;
0511     pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
0512 
0513     ret = pci_read_config_dword(chip->pdev,
0514                     O2_SD_MISC_CTRL4, &scratch_32);
0515     if (ret)
0516         return;
0517     scratch_32 &= ~(0x000f0000);
0518     scratch_32 |= 0x00080000;
0519     pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
0520 }
0521 
0522 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
0523                     struct sdhci_host *host)
0524 {
0525     int ret;
0526 
0527     ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
0528     if (!ret) {
0529         pr_info("%s: unsupported MSI, use INTx irq\n",
0530             mmc_hostname(host->mmc));
0531         return;
0532     }
0533 
0534     ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
0535                     PCI_IRQ_MSI | PCI_IRQ_MSIX);
0536     if (ret < 0) {
0537         pr_err("%s: enable PCI MSI failed, err=%d\n",
0538                mmc_hostname(host->mmc), ret);
0539         return;
0540     }
0541 
0542     host->irq = pci_irq_vector(chip->pdev, 0);
0543 }
0544 
0545 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
0546 {
0547     /* Enable internal clock */
0548     clk |= SDHCI_CLOCK_INT_EN;
0549     sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
0550 
0551     sdhci_o2_enable_internal_clock(host);
0552     if (sdhci_o2_get_cd(host->mmc)) {
0553         clk |= SDHCI_CLOCK_CARD_EN;
0554         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
0555     }
0556 }
0557 
0558 static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
0559 {
0560     u16 clk;
0561     u8 scratch;
0562     u32 scratch_32;
0563     struct sdhci_pci_slot *slot = sdhci_priv(host);
0564     struct sdhci_pci_chip *chip = slot->chip;
0565 
0566     host->mmc->actual_clock = 0;
0567 
0568     sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
0569 
0570     if (clock == 0)
0571         return;
0572 
0573     /* UnLock WP */
0574     pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
0575     scratch &= 0x7f;
0576     pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
0577 
0578     if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) {
0579         pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
0580 
0581         if ((scratch_32 & 0xFFFF0000) != 0x2c280000)
0582             o2_pci_set_baseclk(chip, 0x2c280000);
0583     } else {
0584         pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
0585 
0586         if ((scratch_32 & 0xFFFF0000) != 0x25100000)
0587             o2_pci_set_baseclk(chip, 0x25100000);
0588     }
0589 
0590     pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32);
0591     scratch_32 &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
0592     pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32);
0593 
0594     /* Lock WP */
0595     pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
0596     scratch |= 0x80;
0597     pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
0598 
0599     clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
0600     sdhci_o2_enable_clk(host, clk);
0601 }
0602 
0603 static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
0604 {
0605     struct sdhci_pci_chip *chip;
0606     struct sdhci_host *host;
0607     struct o2_host *o2_host = sdhci_pci_priv(slot);
0608     u32 reg, caps;
0609     int ret;
0610 
0611     chip = slot->chip;
0612     host = slot->host;
0613 
0614     o2_host->dll_adjust_count = 0;
0615     caps = sdhci_readl(host, SDHCI_CAPABILITIES);
0616 
0617     /*
0618      * mmc_select_bus_width() will test the bus to determine the actual bus
0619      * width.
0620      */
0621     if (caps & SDHCI_CAN_DO_8BIT)
0622         host->mmc->caps |= MMC_CAP_8_BIT_DATA;
0623 
0624     switch (chip->pdev->device) {
0625     case PCI_DEVICE_ID_O2_SDS0:
0626     case PCI_DEVICE_ID_O2_SEABIRD0:
0627     case PCI_DEVICE_ID_O2_SEABIRD1:
0628     case PCI_DEVICE_ID_O2_SDS1:
0629     case PCI_DEVICE_ID_O2_FUJIN2:
0630         reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
0631         if (reg & 0x1)
0632             host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
0633 
0634         sdhci_pci_o2_enable_msi(chip, host);
0635 
0636         if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
0637             ret = pci_read_config_dword(chip->pdev,
0638                             O2_SD_MISC_SETTING, &reg);
0639             if (ret)
0640                 return -EIO;
0641             if (reg & (1 << 4)) {
0642                 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
0643                     mmc_hostname(host->mmc));
0644                 host->flags &= ~SDHCI_SIGNALING_330;
0645                 host->flags |= SDHCI_SIGNALING_180;
0646                 host->mmc->caps2 |= MMC_CAP2_NO_SD;
0647                 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
0648                 pci_write_config_dword(chip->pdev,
0649                                O2_SD_DETECT_SETTING, 3);
0650             }
0651 
0652             slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
0653         }
0654 
0655         if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) {
0656             slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
0657             host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
0658             host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
0659         }
0660 
0661         host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
0662 
0663         if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
0664             break;
0665         /* set dll watch dog timer */
0666         reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
0667         reg |= (1 << 12);
0668         sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
0669 
0670         break;
0671     default:
0672         break;
0673     }
0674 
0675     return 0;
0676 }
0677 
0678 static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
0679 {
0680     int ret;
0681     u8 scratch;
0682     u32 scratch_32;
0683 
0684     switch (chip->pdev->device) {
0685     case PCI_DEVICE_ID_O2_8220:
0686     case PCI_DEVICE_ID_O2_8221:
0687     case PCI_DEVICE_ID_O2_8320:
0688     case PCI_DEVICE_ID_O2_8321:
0689         /* This extra setup is required due to broken ADMA. */
0690         ret = pci_read_config_byte(chip->pdev,
0691                 O2_SD_LOCK_WP, &scratch);
0692         if (ret)
0693             return ret;
0694         scratch &= 0x7f;
0695         pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
0696 
0697         /* Set Multi 3 to VCC3V# */
0698         pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
0699 
0700         /* Disable CLK_REQ# support after media DET */
0701         ret = pci_read_config_byte(chip->pdev,
0702                 O2_SD_CLKREQ, &scratch);
0703         if (ret)
0704             return ret;
0705         scratch |= 0x20;
0706         pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
0707 
0708         /* Choose capabilities, enable SDMA.  We have to write 0x01
0709          * to the capabilities register first to unlock it.
0710          */
0711         ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
0712         if (ret)
0713             return ret;
0714         scratch |= 0x01;
0715         pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
0716         pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
0717 
0718         /* Disable ADMA1/2 */
0719         pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
0720         pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
0721 
0722         /* Disable the infinite transfer mode */
0723         ret = pci_read_config_byte(chip->pdev,
0724                 O2_SD_INF_MOD, &scratch);
0725         if (ret)
0726             return ret;
0727         scratch |= 0x08;
0728         pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
0729 
0730         /* Lock WP */
0731         ret = pci_read_config_byte(chip->pdev,
0732                 O2_SD_LOCK_WP, &scratch);
0733         if (ret)
0734             return ret;
0735         scratch |= 0x80;
0736         pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
0737         break;
0738     case PCI_DEVICE_ID_O2_SDS0:
0739     case PCI_DEVICE_ID_O2_SDS1:
0740     case PCI_DEVICE_ID_O2_FUJIN2:
0741         /* UnLock WP */
0742         ret = pci_read_config_byte(chip->pdev,
0743                 O2_SD_LOCK_WP, &scratch);
0744         if (ret)
0745             return ret;
0746 
0747         scratch &= 0x7f;
0748         pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
0749 
0750         /* DevId=8520 subId= 0x11 or 0x12  Type Chip support */
0751         if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
0752             ret = pci_read_config_dword(chip->pdev,
0753                             O2_SD_FUNC_REG0,
0754                             &scratch_32);
0755             if (ret)
0756                 return ret;
0757             scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
0758 
0759             /* Check Whether subId is 0x11 or 0x12 */
0760             if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
0761                 scratch_32 = 0x25100000;
0762 
0763                 o2_pci_set_baseclk(chip, scratch_32);
0764                 ret = pci_read_config_dword(chip->pdev,
0765                                 O2_SD_FUNC_REG4,
0766                                 &scratch_32);
0767                 if (ret)
0768                     return ret;
0769 
0770                 /* Enable Base Clk setting change */
0771                 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
0772                 pci_write_config_dword(chip->pdev,
0773                                O2_SD_FUNC_REG4,
0774                                scratch_32);
0775 
0776                 /* Set Tuning Window to 4 */
0777                 pci_write_config_byte(chip->pdev,
0778                               O2_SD_TUNING_CTRL, 0x44);
0779 
0780                 break;
0781             }
0782         }
0783 
0784         /* Enable 8520 led function */
0785         o2_pci_led_enable(chip);
0786 
0787         /* Set timeout CLK */
0788         ret = pci_read_config_dword(chip->pdev,
0789                         O2_SD_CLK_SETTING, &scratch_32);
0790         if (ret)
0791             return ret;
0792 
0793         scratch_32 &= ~(0xFF00);
0794         scratch_32 |= 0x07E0C800;
0795         pci_write_config_dword(chip->pdev,
0796                        O2_SD_CLK_SETTING, scratch_32);
0797 
0798         ret = pci_read_config_dword(chip->pdev,
0799                         O2_SD_CLKREQ, &scratch_32);
0800         if (ret)
0801             return ret;
0802         scratch_32 |= 0x3;
0803         pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
0804 
0805         ret = pci_read_config_dword(chip->pdev,
0806                         O2_SD_PLL_SETTING, &scratch_32);
0807         if (ret)
0808             return ret;
0809 
0810         scratch_32 &= ~(0x1F3F070E);
0811         scratch_32 |= 0x18270106;
0812         pci_write_config_dword(chip->pdev,
0813                        O2_SD_PLL_SETTING, scratch_32);
0814 
0815         /* Disable UHS1 funciton */
0816         ret = pci_read_config_dword(chip->pdev,
0817                         O2_SD_CAP_REG2, &scratch_32);
0818         if (ret)
0819             return ret;
0820         scratch_32 &= ~(0xE0);
0821         pci_write_config_dword(chip->pdev,
0822                        O2_SD_CAP_REG2, scratch_32);
0823 
0824         if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
0825             sdhci_pci_o2_fujin2_pci_init(chip);
0826 
0827         /* Lock WP */
0828         ret = pci_read_config_byte(chip->pdev,
0829                        O2_SD_LOCK_WP, &scratch);
0830         if (ret)
0831             return ret;
0832         scratch |= 0x80;
0833         pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
0834         break;
0835     case PCI_DEVICE_ID_O2_SEABIRD0:
0836     case PCI_DEVICE_ID_O2_SEABIRD1:
0837         /* UnLock WP */
0838         ret = pci_read_config_byte(chip->pdev,
0839                 O2_SD_LOCK_WP, &scratch);
0840         if (ret)
0841             return ret;
0842 
0843         scratch &= 0x7f;
0844         pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
0845 
0846         ret = pci_read_config_dword(chip->pdev,
0847                         O2_SD_PLL_SETTING, &scratch_32);
0848         if (ret)
0849             return ret;
0850 
0851         if ((scratch_32 & 0xff000000) == 0x01000000) {
0852             scratch_32 &= 0x0000FFFF;
0853             scratch_32 |= 0x1F340000;
0854 
0855             pci_write_config_dword(chip->pdev,
0856                            O2_SD_PLL_SETTING, scratch_32);
0857         } else {
0858             scratch_32 &= 0x0000FFFF;
0859             scratch_32 |= 0x25100000;
0860 
0861             pci_write_config_dword(chip->pdev,
0862                            O2_SD_PLL_SETTING, scratch_32);
0863 
0864             ret = pci_read_config_dword(chip->pdev,
0865                             O2_SD_FUNC_REG4,
0866                             &scratch_32);
0867             if (ret)
0868                 return ret;
0869             scratch_32 |= (1 << 22);
0870             pci_write_config_dword(chip->pdev,
0871                            O2_SD_FUNC_REG4, scratch_32);
0872         }
0873 
0874         /* Set Tuning Windows to 5 */
0875         pci_write_config_byte(chip->pdev,
0876                 O2_SD_TUNING_CTRL, 0x55);
0877         /* Lock WP */
0878         ret = pci_read_config_byte(chip->pdev,
0879                        O2_SD_LOCK_WP, &scratch);
0880         if (ret)
0881             return ret;
0882         scratch |= 0x80;
0883         pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
0884         break;
0885     }
0886 
0887     return 0;
0888 }
0889 
0890 #ifdef CONFIG_PM_SLEEP
0891 static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
0892 {
0893     sdhci_pci_o2_probe(chip);
0894     return sdhci_pci_resume_host(chip);
0895 }
0896 #endif
0897 
0898 static const struct sdhci_ops sdhci_pci_o2_ops = {
0899     .set_clock = sdhci_pci_o2_set_clock,
0900     .enable_dma = sdhci_pci_enable_dma,
0901     .set_bus_width = sdhci_set_bus_width,
0902     .reset = sdhci_reset,
0903     .set_uhs_signaling = sdhci_set_uhs_signaling,
0904 };
0905 
0906 const struct sdhci_pci_fixes sdhci_o2 = {
0907     .probe = sdhci_pci_o2_probe,
0908     .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
0909     .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
0910     .probe_slot = sdhci_pci_o2_probe_slot,
0911 #ifdef CONFIG_PM_SLEEP
0912     .resume = sdhci_pci_o2_resume,
0913 #endif
0914     .ops = &sdhci_pci_o2_ops,
0915     .priv_size = sizeof(struct o2_host),
0916 };
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