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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (C) 2019 Genesys Logic, Inc.
0004  *
0005  * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw>
0006  *
0007  * Version: v0.9.0 (2019-08-08)
0008  */
0009 
0010 #include <linux/bitfield.h>
0011 #include <linux/bits.h>
0012 #include <linux/pci.h>
0013 #include <linux/mmc/mmc.h>
0014 #include <linux/delay.h>
0015 #include <linux/of.h>
0016 #include <linux/iopoll.h>
0017 #include "sdhci.h"
0018 #include "sdhci-pci.h"
0019 #include "cqhci.h"
0020 
0021 /*  Genesys Logic extra registers */
0022 #define SDHCI_GLI_9750_WT         0x800
0023 #define   SDHCI_GLI_9750_WT_EN      BIT(0)
0024 #define   GLI_9750_WT_EN_ON     0x1
0025 #define   GLI_9750_WT_EN_OFF        0x0
0026 
0027 #define SDHCI_GLI_9750_CFG2          0x848
0028 #define   SDHCI_GLI_9750_CFG2_L1DLY    GENMASK(28, 24)
0029 #define   GLI_9750_CFG2_L1DLY_VALUE    0x1F
0030 
0031 #define SDHCI_GLI_9750_DRIVING      0x860
0032 #define   SDHCI_GLI_9750_DRIVING_1    GENMASK(11, 0)
0033 #define   SDHCI_GLI_9750_DRIVING_2    GENMASK(27, 26)
0034 #define   GLI_9750_DRIVING_1_VALUE    0xFFF
0035 #define   GLI_9750_DRIVING_2_VALUE    0x3
0036 #define   SDHCI_GLI_9750_SEL_1        BIT(29)
0037 #define   SDHCI_GLI_9750_SEL_2        BIT(31)
0038 #define   SDHCI_GLI_9750_ALL_RST      (BIT(24)|BIT(25)|BIT(28)|BIT(30))
0039 
0040 #define SDHCI_GLI_9750_PLL        0x864
0041 #define   SDHCI_GLI_9750_PLL_LDIV       GENMASK(9, 0)
0042 #define   SDHCI_GLI_9750_PLL_PDIV       GENMASK(14, 12)
0043 #define   SDHCI_GLI_9750_PLL_DIR        BIT(15)
0044 #define   SDHCI_GLI_9750_PLL_TX2_INV    BIT(23)
0045 #define   SDHCI_GLI_9750_PLL_TX2_DLY    GENMASK(22, 20)
0046 #define   GLI_9750_PLL_TX2_INV_VALUE    0x1
0047 #define   GLI_9750_PLL_TX2_DLY_VALUE    0x0
0048 #define   SDHCI_GLI_9750_PLLSSC_STEP    GENMASK(28, 24)
0049 #define   SDHCI_GLI_9750_PLLSSC_EN      BIT(31)
0050 
0051 #define SDHCI_GLI_9750_PLLSSC        0x86C
0052 #define   SDHCI_GLI_9750_PLLSSC_PPM    GENMASK(31, 16)
0053 
0054 #define SDHCI_GLI_9750_SW_CTRL      0x874
0055 #define   SDHCI_GLI_9750_SW_CTRL_4    GENMASK(7, 6)
0056 #define   GLI_9750_SW_CTRL_4_VALUE    0x3
0057 
0058 #define SDHCI_GLI_9750_MISC            0x878
0059 #define   SDHCI_GLI_9750_MISC_TX1_INV    BIT(2)
0060 #define   SDHCI_GLI_9750_MISC_RX_INV     BIT(3)
0061 #define   SDHCI_GLI_9750_MISC_TX1_DLY    GENMASK(6, 4)
0062 #define   GLI_9750_MISC_TX1_INV_VALUE    0x0
0063 #define   GLI_9750_MISC_RX_INV_ON        0x1
0064 #define   GLI_9750_MISC_RX_INV_OFF       0x0
0065 #define   GLI_9750_MISC_RX_INV_VALUE     GLI_9750_MISC_RX_INV_OFF
0066 #define   GLI_9750_MISC_TX1_DLY_VALUE    0x5
0067 #define   SDHCI_GLI_9750_MISC_SSC_OFF    BIT(26)
0068 
0069 #define SDHCI_GLI_9750_TUNING_CONTROL             0x540
0070 #define   SDHCI_GLI_9750_TUNING_CONTROL_EN          BIT(4)
0071 #define   GLI_9750_TUNING_CONTROL_EN_ON             0x1
0072 #define   GLI_9750_TUNING_CONTROL_EN_OFF            0x0
0073 #define   SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1    BIT(16)
0074 #define   SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2    GENMASK(20, 19)
0075 #define   GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE    0x1
0076 #define   GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE    0x2
0077 
0078 #define SDHCI_GLI_9750_TUNING_PARAMETERS           0x544
0079 #define   SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY    GENMASK(2, 0)
0080 #define   GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE    0x1
0081 
0082 #define SDHCI_GLI_9763E_CTRL_HS400  0x7
0083 
0084 #define SDHCI_GLI_9763E_HS400_ES_REG      0x52C
0085 #define   SDHCI_GLI_9763E_HS400_ES_BIT      BIT(8)
0086 
0087 #define PCIE_GLI_9763E_VHS   0x884
0088 #define   GLI_9763E_VHS_REV    GENMASK(19, 16)
0089 #define   GLI_9763E_VHS_REV_R      0x0
0090 #define   GLI_9763E_VHS_REV_M      0x1
0091 #define   GLI_9763E_VHS_REV_W      0x2
0092 #define PCIE_GLI_9763E_MB    0x888
0093 #define   GLI_9763E_MB_CMDQ_OFF    BIT(19)
0094 #define   GLI_9763E_MB_ERP_ON      BIT(7)
0095 #define PCIE_GLI_9763E_SCR   0x8E0
0096 #define   GLI_9763E_SCR_AXI_REQ    BIT(9)
0097 
0098 #define PCIE_GLI_9763E_CFG       0x8A0
0099 #define   GLI_9763E_CFG_LPSN_DIS   BIT(12)
0100 
0101 #define PCIE_GLI_9763E_CFG2      0x8A4
0102 #define   GLI_9763E_CFG2_L1DLY     GENMASK(28, 19)
0103 #define   GLI_9763E_CFG2_L1DLY_MID 0x54
0104 
0105 #define PCIE_GLI_9763E_MMC_CTRL  0x960
0106 #define   GLI_9763E_HS400_SLOW     BIT(3)
0107 
0108 #define PCIE_GLI_9763E_CLKRXDLY  0x934
0109 #define   GLI_9763E_HS400_RXDLY    GENMASK(31, 28)
0110 #define   GLI_9763E_HS400_RXDLY_5  0x5
0111 
0112 #define SDHCI_GLI_9763E_CQE_BASE_ADDR    0x200
0113 #define GLI_9763E_CQE_TRNS_MODE    (SDHCI_TRNS_MULTI | \
0114                     SDHCI_TRNS_BLK_CNT_EN | \
0115                     SDHCI_TRNS_DMA)
0116 
0117 #define PCI_GLI_9755_WT       0x800
0118 #define   PCI_GLI_9755_WT_EN    BIT(0)
0119 #define   GLI_9755_WT_EN_ON     0x1
0120 #define   GLI_9755_WT_EN_OFF    0x0
0121 
0122 #define PCI_GLI_9755_PECONF   0x44
0123 #define   PCI_GLI_9755_LFCLK    GENMASK(14, 12)
0124 #define   PCI_GLI_9755_DMACLK   BIT(29)
0125 #define   PCI_GLI_9755_INVERT_CD  BIT(30)
0126 #define   PCI_GLI_9755_INVERT_WP  BIT(31)
0127 
0128 #define PCI_GLI_9755_CFG2          0x48
0129 #define   PCI_GLI_9755_CFG2_L1DLY    GENMASK(28, 24)
0130 #define   GLI_9755_CFG2_L1DLY_VALUE  0x1F
0131 
0132 #define PCI_GLI_9755_PLL            0x64
0133 #define   PCI_GLI_9755_PLL_LDIV       GENMASK(9, 0)
0134 #define   PCI_GLI_9755_PLL_PDIV       GENMASK(14, 12)
0135 #define   PCI_GLI_9755_PLL_DIR        BIT(15)
0136 #define   PCI_GLI_9755_PLLSSC_STEP    GENMASK(28, 24)
0137 #define   PCI_GLI_9755_PLLSSC_EN      BIT(31)
0138 
0139 #define PCI_GLI_9755_PLLSSC        0x68
0140 #define   PCI_GLI_9755_PLLSSC_PPM    GENMASK(15, 0)
0141 
0142 #define PCI_GLI_9755_SerDes  0x70
0143 #define PCI_GLI_9755_SCP_DIS   BIT(19)
0144 
0145 #define PCI_GLI_9755_MISC       0x78
0146 #define   PCI_GLI_9755_MISC_SSC_OFF    BIT(26)
0147 
0148 #define PCI_GLI_9755_PM_CTRL     0xFC
0149 #define   PCI_GLI_9755_PM_STATE    GENMASK(1, 0)
0150 
0151 #define GLI_MAX_TUNING_LOOP 40
0152 
0153 /* Genesys Logic chipset */
0154 static inline void gl9750_wt_on(struct sdhci_host *host)
0155 {
0156     u32 wt_value;
0157     u32 wt_enable;
0158 
0159     wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
0160     wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
0161 
0162     if (wt_enable == GLI_9750_WT_EN_ON)
0163         return;
0164 
0165     wt_value &= ~SDHCI_GLI_9750_WT_EN;
0166     wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON);
0167 
0168     sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
0169 }
0170 
0171 static inline void gl9750_wt_off(struct sdhci_host *host)
0172 {
0173     u32 wt_value;
0174     u32 wt_enable;
0175 
0176     wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
0177     wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
0178 
0179     if (wt_enable == GLI_9750_WT_EN_OFF)
0180         return;
0181 
0182     wt_value &= ~SDHCI_GLI_9750_WT_EN;
0183     wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF);
0184 
0185     sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
0186 }
0187 
0188 static void gli_set_9750(struct sdhci_host *host)
0189 {
0190     u32 driving_value;
0191     u32 pll_value;
0192     u32 sw_ctrl_value;
0193     u32 misc_value;
0194     u32 parameter_value;
0195     u32 control_value;
0196     u16 ctrl2;
0197 
0198     gl9750_wt_on(host);
0199 
0200     driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
0201     pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
0202     sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
0203     misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
0204     parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);
0205     control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
0206 
0207     driving_value &= ~(SDHCI_GLI_9750_DRIVING_1);
0208     driving_value &= ~(SDHCI_GLI_9750_DRIVING_2);
0209     driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1,
0210                     GLI_9750_DRIVING_1_VALUE);
0211     driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2,
0212                     GLI_9750_DRIVING_2_VALUE);
0213     driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST);
0214     driving_value |= SDHCI_GLI_9750_SEL_2;
0215     sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);
0216 
0217     sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4;
0218     sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4,
0219                     GLI_9750_SW_CTRL_4_VALUE);
0220     sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);
0221 
0222     /* reset the tuning flow after reinit and before starting tuning */
0223     pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV;
0224     pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY;
0225     pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV,
0226                 GLI_9750_PLL_TX2_INV_VALUE);
0227     pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY,
0228                 GLI_9750_PLL_TX2_DLY_VALUE);
0229 
0230     misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV;
0231     misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
0232     misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY;
0233     misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV,
0234                  GLI_9750_MISC_TX1_INV_VALUE);
0235     misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
0236                  GLI_9750_MISC_RX_INV_VALUE);
0237     misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY,
0238                  GLI_9750_MISC_TX1_DLY_VALUE);
0239 
0240     parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY;
0241     parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY,
0242                       GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE);
0243 
0244     control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;
0245     control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;
0246     control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,
0247                     GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE);
0248     control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,
0249                     GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE);
0250 
0251     sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);
0252     sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
0253 
0254     /* disable tuned clk */
0255     ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
0256     ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
0257     sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
0258 
0259     /* enable tuning parameters control */
0260     control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
0261     control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
0262                     GLI_9750_TUNING_CONTROL_EN_ON);
0263     sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
0264 
0265     /* write tuning parameters */
0266     sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);
0267 
0268     /* disable tuning parameters control */
0269     control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
0270     control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
0271                     GLI_9750_TUNING_CONTROL_EN_OFF);
0272     sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
0273 
0274     /* clear tuned clk */
0275     ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
0276     ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
0277     sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
0278 
0279     gl9750_wt_off(host);
0280 }
0281 
0282 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)
0283 {
0284     u32 misc_value;
0285 
0286     gl9750_wt_on(host);
0287 
0288     misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
0289     misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
0290     if (b) {
0291         misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
0292                      GLI_9750_MISC_RX_INV_ON);
0293     } else {
0294         misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
0295                      GLI_9750_MISC_RX_INV_OFF);
0296     }
0297     sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
0298 
0299     gl9750_wt_off(host);
0300 }
0301 
0302 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)
0303 {
0304     int i;
0305     int rx_inv;
0306 
0307     for (rx_inv = 0; rx_inv < 2; rx_inv++) {
0308         gli_set_9750_rx_inv(host, !!rx_inv);
0309         sdhci_start_tuning(host);
0310 
0311         for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) {
0312             u16 ctrl;
0313 
0314             sdhci_send_tuning(host, opcode);
0315 
0316             if (!host->tuning_done) {
0317                 sdhci_abort_tuning(host, opcode);
0318                 break;
0319             }
0320 
0321             ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
0322             if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
0323                 if (ctrl & SDHCI_CTRL_TUNED_CLK)
0324                     return 0; /* Success! */
0325                 break;
0326             }
0327         }
0328     }
0329     if (!host->tuning_done) {
0330         pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
0331             mmc_hostname(host->mmc));
0332         return -ETIMEDOUT;
0333     }
0334 
0335     pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
0336         mmc_hostname(host->mmc));
0337     sdhci_reset_tuning(host);
0338 
0339     return -EAGAIN;
0340 }
0341 
0342 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
0343 {
0344     host->mmc->retune_period = 0;
0345     if (host->tuning_mode == SDHCI_TUNING_MODE_1)
0346         host->mmc->retune_period = host->tuning_count;
0347 
0348     gli_set_9750(host);
0349     host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);
0350     sdhci_end_tuning(host);
0351 
0352     return 0;
0353 }
0354 
0355 static void gl9750_disable_ssc_pll(struct sdhci_host *host)
0356 {
0357     u32 pll;
0358 
0359     gl9750_wt_on(host);
0360     pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
0361     pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);
0362     sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
0363     gl9750_wt_off(host);
0364 }
0365 
0366 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
0367 {
0368     u32 pll;
0369 
0370     gl9750_wt_on(host);
0371     pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
0372     pll &= ~(SDHCI_GLI_9750_PLL_LDIV |
0373          SDHCI_GLI_9750_PLL_PDIV |
0374          SDHCI_GLI_9750_PLL_DIR);
0375     pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |
0376            FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) |
0377            FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir);
0378     sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
0379     gl9750_wt_off(host);
0380 
0381     /* wait for pll stable */
0382     mdelay(1);
0383 }
0384 
0385 static bool gl9750_ssc_enable(struct sdhci_host *host)
0386 {
0387     u32 misc;
0388     u8 off;
0389 
0390     gl9750_wt_on(host);
0391     misc = sdhci_readl(host, SDHCI_GLI_9750_MISC);
0392     off = FIELD_GET(SDHCI_GLI_9750_MISC_SSC_OFF, misc);
0393     gl9750_wt_off(host);
0394 
0395     return !off;
0396 }
0397 
0398 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
0399 {
0400     u32 pll;
0401     u32 ssc;
0402 
0403     gl9750_wt_on(host);
0404     pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
0405     ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
0406     pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |
0407          SDHCI_GLI_9750_PLLSSC_EN);
0408     ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;
0409     pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |
0410            FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable);
0411     ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);
0412     sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
0413     sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
0414     gl9750_wt_off(host);
0415 }
0416 
0417 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
0418 {
0419     bool enable = gl9750_ssc_enable(host);
0420 
0421     /* set pll to 205MHz and ssc */
0422     gl9750_set_ssc(host, enable, 0xF, 0x5A1D);
0423     gl9750_set_pll(host, 0x1, 0x246, 0x0);
0424 }
0425 
0426 static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host)
0427 {
0428     bool enable = gl9750_ssc_enable(host);
0429 
0430     /* set pll to 100MHz and ssc */
0431     gl9750_set_ssc(host, enable, 0xE, 0x51EC);
0432     gl9750_set_pll(host, 0x1, 0x244, 0x1);
0433 }
0434 
0435 static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host)
0436 {
0437     bool enable = gl9750_ssc_enable(host);
0438 
0439     /* set pll to 50MHz and ssc */
0440     gl9750_set_ssc(host, enable, 0xE, 0x51EC);
0441     gl9750_set_pll(host, 0x1, 0x244, 0x3);
0442 }
0443 
0444 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
0445 {
0446     struct mmc_ios *ios = &host->mmc->ios;
0447     u16 clk;
0448 
0449     host->mmc->actual_clock = 0;
0450 
0451     gl9750_disable_ssc_pll(host);
0452     sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
0453 
0454     if (clock == 0)
0455         return;
0456 
0457     clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
0458     if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
0459         host->mmc->actual_clock = 205000000;
0460         gl9750_set_ssc_pll_205mhz(host);
0461     } else if (clock == 100000000) {
0462         gl9750_set_ssc_pll_100mhz(host);
0463     } else if (clock == 50000000) {
0464         gl9750_set_ssc_pll_50mhz(host);
0465     }
0466 
0467     sdhci_enable_clk(host, clk);
0468 }
0469 
0470 static void gl9750_hw_setting(struct sdhci_host *host)
0471 {
0472     u32 value;
0473 
0474     gl9750_wt_on(host);
0475 
0476     value = sdhci_readl(host, SDHCI_GLI_9750_CFG2);
0477     value &= ~SDHCI_GLI_9750_CFG2_L1DLY;
0478     /* set ASPM L1 entry delay to 7.9us */
0479     value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY,
0480                 GLI_9750_CFG2_L1DLY_VALUE);
0481     sdhci_writel(host, value, SDHCI_GLI_9750_CFG2);
0482 
0483     gl9750_wt_off(host);
0484 }
0485 
0486 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
0487 {
0488     int ret;
0489 
0490     ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1,
0491                     PCI_IRQ_MSI | PCI_IRQ_MSIX);
0492     if (ret < 0) {
0493         pr_warn("%s: enable PCI MSI failed, error=%d\n",
0494                mmc_hostname(slot->host->mmc), ret);
0495         return;
0496     }
0497 
0498     slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
0499 }
0500 
0501 static inline void gl9755_wt_on(struct pci_dev *pdev)
0502 {
0503     u32 wt_value;
0504     u32 wt_enable;
0505 
0506     pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
0507     wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
0508 
0509     if (wt_enable == GLI_9755_WT_EN_ON)
0510         return;
0511 
0512     wt_value &= ~PCI_GLI_9755_WT_EN;
0513     wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON);
0514 
0515     pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
0516 }
0517 
0518 static inline void gl9755_wt_off(struct pci_dev *pdev)
0519 {
0520     u32 wt_value;
0521     u32 wt_enable;
0522 
0523     pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
0524     wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
0525 
0526     if (wt_enable == GLI_9755_WT_EN_OFF)
0527         return;
0528 
0529     wt_value &= ~PCI_GLI_9755_WT_EN;
0530     wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF);
0531 
0532     pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
0533 }
0534 
0535 static void gl9755_disable_ssc_pll(struct pci_dev *pdev)
0536 {
0537     u32 pll;
0538 
0539     gl9755_wt_on(pdev);
0540     pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
0541     pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);
0542     pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
0543     gl9755_wt_off(pdev);
0544 }
0545 
0546 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
0547 {
0548     u32 pll;
0549 
0550     gl9755_wt_on(pdev);
0551     pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
0552     pll &= ~(PCI_GLI_9755_PLL_LDIV |
0553          PCI_GLI_9755_PLL_PDIV |
0554          PCI_GLI_9755_PLL_DIR);
0555     pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |
0556            FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) |
0557            FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir);
0558     pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
0559     gl9755_wt_off(pdev);
0560 
0561     /* wait for pll stable */
0562     mdelay(1);
0563 }
0564 
0565 static bool gl9755_ssc_enable(struct pci_dev *pdev)
0566 {
0567     u32 misc;
0568     u8 off;
0569 
0570     gl9755_wt_on(pdev);
0571     pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc);
0572     off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc);
0573     gl9755_wt_off(pdev);
0574 
0575     return !off;
0576 }
0577 
0578 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
0579 {
0580     u32 pll;
0581     u32 ssc;
0582 
0583     gl9755_wt_on(pdev);
0584     pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
0585     pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);
0586     pll &= ~(PCI_GLI_9755_PLLSSC_STEP |
0587          PCI_GLI_9755_PLLSSC_EN);
0588     ssc &= ~PCI_GLI_9755_PLLSSC_PPM;
0589     pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |
0590            FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable);
0591     ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);
0592     pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);
0593     pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
0594     gl9755_wt_off(pdev);
0595 }
0596 
0597 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
0598 {
0599     bool enable = gl9755_ssc_enable(pdev);
0600 
0601     /* set pll to 205MHz and ssc */
0602     gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D);
0603     gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
0604 }
0605 
0606 static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev)
0607 {
0608     bool enable = gl9755_ssc_enable(pdev);
0609 
0610     /* set pll to 100MHz and ssc */
0611     gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);
0612     gl9755_set_pll(pdev, 0x1, 0x244, 0x1);
0613 }
0614 
0615 static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev)
0616 {
0617     bool enable = gl9755_ssc_enable(pdev);
0618 
0619     /* set pll to 50MHz and ssc */
0620     gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);
0621     gl9755_set_pll(pdev, 0x1, 0x244, 0x3);
0622 }
0623 
0624 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
0625 {
0626     struct sdhci_pci_slot *slot = sdhci_priv(host);
0627     struct mmc_ios *ios = &host->mmc->ios;
0628     struct pci_dev *pdev;
0629     u16 clk;
0630 
0631     pdev = slot->chip->pdev;
0632     host->mmc->actual_clock = 0;
0633 
0634     gl9755_disable_ssc_pll(pdev);
0635     sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
0636 
0637     if (clock == 0)
0638         return;
0639 
0640     clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
0641     if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
0642         host->mmc->actual_clock = 205000000;
0643         gl9755_set_ssc_pll_205mhz(pdev);
0644     } else if (clock == 100000000) {
0645         gl9755_set_ssc_pll_100mhz(pdev);
0646     } else if (clock == 50000000) {
0647         gl9755_set_ssc_pll_50mhz(pdev);
0648     }
0649 
0650     sdhci_enable_clk(host, clk);
0651 }
0652 
0653 static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
0654 {
0655     struct pci_dev *pdev = slot->chip->pdev;
0656     u32 value;
0657 
0658     gl9755_wt_on(pdev);
0659 
0660     pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value);
0661     /*
0662      * Apple ARM64 platforms using these chips may have
0663      * inverted CD/WP detection.
0664      */
0665     if (of_property_read_bool(pdev->dev.of_node, "cd-inverted"))
0666         value |= PCI_GLI_9755_INVERT_CD;
0667     if (of_property_read_bool(pdev->dev.of_node, "wp-inverted"))
0668         value |= PCI_GLI_9755_INVERT_WP;
0669     value &= ~PCI_GLI_9755_LFCLK;
0670     value &= ~PCI_GLI_9755_DMACLK;
0671     pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value);
0672 
0673     /* enable short circuit protection */
0674     pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value);
0675     value &= ~PCI_GLI_9755_SCP_DIS;
0676     pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value);
0677 
0678     pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value);
0679     value &= ~PCI_GLI_9755_CFG2_L1DLY;
0680     /* set ASPM L1 entry delay to 7.9us */
0681     value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY,
0682                 GLI_9755_CFG2_L1DLY_VALUE);
0683     pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
0684 
0685     /* toggle PM state to allow GL9755 to enter ASPM L1.2 */
0686     pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value);
0687     value |= PCI_GLI_9755_PM_STATE;
0688     pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
0689     value &= ~PCI_GLI_9755_PM_STATE;
0690     pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
0691 
0692     gl9755_wt_off(pdev);
0693 }
0694 
0695 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
0696 {
0697     struct sdhci_host *host = slot->host;
0698 
0699     gl9750_hw_setting(host);
0700     gli_pcie_enable_msi(slot);
0701     slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
0702     sdhci_enable_v4_mode(host);
0703 
0704     return 0;
0705 }
0706 
0707 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)
0708 {
0709     struct sdhci_host *host = slot->host;
0710 
0711     gl9755_hw_setting(slot);
0712     gli_pcie_enable_msi(slot);
0713     slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
0714     sdhci_enable_v4_mode(host);
0715 
0716     return 0;
0717 }
0718 
0719 static void sdhci_gli_voltage_switch(struct sdhci_host *host)
0720 {
0721     /*
0722      * According to Section 3.6.1 signal voltage switch procedure in
0723      * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
0724      * follows:
0725      * (6) Set 1.8V Signal Enable in the Host Control 2 register.
0726      * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
0727      *     period.
0728      * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
0729      *     step (12).
0730      *
0731      * Wait 5ms after set 1.8V signal enable in Host Control 2 register
0732      * to ensure 1.8V signal enable bit is set by GL9750/GL9755.
0733      *
0734      * ...however, the controller in the NUC10i3FNK4 (a 9755) requires
0735      * slightly longer than 5ms before the control register reports that
0736      * 1.8V is ready, and far longer still before the card will actually
0737      * work reliably.
0738      */
0739     usleep_range(100000, 110000);
0740 }
0741 
0742 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
0743 {
0744     sdhci_reset(host, mask);
0745     gli_set_9750(host);
0746 }
0747 
0748 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
0749 {
0750     u32 value;
0751 
0752     value = readl(host->ioaddr + reg);
0753     if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff)))
0754         value |= 0xc8;
0755 
0756     return value;
0757 }
0758 
0759 #ifdef CONFIG_PM_SLEEP
0760 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip)
0761 {
0762     struct sdhci_pci_slot *slot = chip->slots[0];
0763 
0764     pci_free_irq_vectors(slot->chip->pdev);
0765     gli_pcie_enable_msi(slot);
0766 
0767     return sdhci_pci_resume_host(chip);
0768 }
0769 
0770 static int sdhci_cqhci_gli_resume(struct sdhci_pci_chip *chip)
0771 {
0772     struct sdhci_pci_slot *slot = chip->slots[0];
0773     int ret;
0774 
0775     ret = sdhci_pci_gli_resume(chip);
0776     if (ret)
0777         return ret;
0778 
0779     return cqhci_resume(slot->host->mmc);
0780 }
0781 
0782 static int sdhci_cqhci_gli_suspend(struct sdhci_pci_chip *chip)
0783 {
0784     struct sdhci_pci_slot *slot = chip->slots[0];
0785     int ret;
0786 
0787     ret = cqhci_suspend(slot->host->mmc);
0788     if (ret)
0789         return ret;
0790 
0791     return sdhci_suspend_host(slot->host);
0792 }
0793 #endif
0794 
0795 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc,
0796                       struct mmc_ios *ios)
0797 {
0798     struct sdhci_host *host = mmc_priv(mmc);
0799     u32 val;
0800 
0801     val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);
0802     if (ios->enhanced_strobe)
0803         val |= SDHCI_GLI_9763E_HS400_ES_BIT;
0804     else
0805         val &= ~SDHCI_GLI_9763E_HS400_ES_BIT;
0806 
0807     sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);
0808 }
0809 
0810 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,
0811                     unsigned int timing)
0812 {
0813     u16 ctrl_2;
0814 
0815     ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
0816     ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
0817     if (timing == MMC_TIMING_MMC_HS200)
0818         ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
0819     else if (timing == MMC_TIMING_MMC_HS)
0820         ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
0821     else if (timing == MMC_TIMING_MMC_DDR52)
0822         ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
0823     else if (timing == MMC_TIMING_MMC_HS400)
0824         ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400;
0825 
0826     sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
0827 }
0828 
0829 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc)
0830 {
0831     sdhci_dumpregs(mmc_priv(mmc));
0832 }
0833 
0834 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc)
0835 {
0836     struct cqhci_host *cq_host = mmc->cqe_private;
0837     u32 value;
0838 
0839     value = cqhci_readl(cq_host, CQHCI_CFG);
0840     value |= CQHCI_ENABLE;
0841     cqhci_writel(cq_host, value, CQHCI_CFG);
0842 }
0843 
0844 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc)
0845 {
0846     struct sdhci_host *host = mmc_priv(mmc);
0847 
0848     sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
0849     sdhci_cqe_enable(mmc);
0850 }
0851 
0852 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)
0853 {
0854     int cmd_error = 0;
0855     int data_error = 0;
0856 
0857     if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
0858         return intmask;
0859 
0860     cqhci_irq(host->mmc, intmask, cmd_error, data_error);
0861 
0862     return 0;
0863 }
0864 
0865 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc)
0866 {
0867     struct sdhci_host *host = mmc_priv(mmc);
0868     struct cqhci_host *cq_host = mmc->cqe_private;
0869     u32 value;
0870 
0871     value = cqhci_readl(cq_host, CQHCI_CFG);
0872     value &= ~CQHCI_ENABLE;
0873     cqhci_writel(cq_host, value, CQHCI_CFG);
0874     sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
0875 }
0876 
0877 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = {
0878     .enable         = sdhci_gl9763e_cqe_enable,
0879     .disable        = sdhci_cqe_disable,
0880     .dumpregs       = sdhci_gl9763e_dumpregs,
0881     .pre_enable     = sdhci_gl9763e_cqe_pre_enable,
0882     .post_disable   = sdhci_gl9763e_cqe_post_disable,
0883 };
0884 
0885 static int gl9763e_add_host(struct sdhci_pci_slot *slot)
0886 {
0887     struct device *dev = &slot->chip->pdev->dev;
0888     struct sdhci_host *host = slot->host;
0889     struct cqhci_host *cq_host;
0890     bool dma64;
0891     int ret;
0892 
0893     ret = sdhci_setup_host(host);
0894     if (ret)
0895         return ret;
0896 
0897     cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
0898     if (!cq_host) {
0899         ret = -ENOMEM;
0900         goto cleanup;
0901     }
0902 
0903     cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;
0904     cq_host->ops = &sdhci_gl9763e_cqhci_ops;
0905 
0906     dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
0907     if (dma64)
0908         cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
0909 
0910     ret = cqhci_init(cq_host, host->mmc, dma64);
0911     if (ret)
0912         goto cleanup;
0913 
0914     ret = __sdhci_add_host(host);
0915     if (ret)
0916         goto cleanup;
0917 
0918     return 0;
0919 
0920 cleanup:
0921     sdhci_cleanup_host(host);
0922     return ret;
0923 }
0924 
0925 static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask)
0926 {
0927     if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) &&
0928         host->mmc->cqe_private)
0929         cqhci_deactivate(host->mmc);
0930     sdhci_reset(host, mask);
0931 }
0932 
0933 static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
0934 {
0935     struct pci_dev *pdev = slot->chip->pdev;
0936     u32 value;
0937 
0938     pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
0939     value &= ~GLI_9763E_VHS_REV;
0940     value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
0941     pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
0942 
0943     pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value);
0944     value |= GLI_9763E_SCR_AXI_REQ;
0945     pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);
0946 
0947     pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value);
0948     value &= ~GLI_9763E_HS400_SLOW;
0949     pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value);
0950 
0951     pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
0952     value &= ~GLI_9763E_CFG2_L1DLY;
0953     /* set ASPM L1 entry delay to 21us */
0954     value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);
0955     pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
0956 
0957     pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value);
0958     value &= ~GLI_9763E_HS400_RXDLY;
0959     value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5);
0960     pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value);
0961 
0962     pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
0963     value &= ~GLI_9763E_VHS_REV;
0964     value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
0965     pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
0966 }
0967 
0968 #ifdef CONFIG_PM
0969 static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot, bool enable)
0970 {
0971     struct pci_dev *pdev = slot->chip->pdev;
0972     u32 value;
0973 
0974     pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
0975     value &= ~GLI_9763E_VHS_REV;
0976     value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
0977     pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
0978 
0979     pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &value);
0980 
0981     if (enable)
0982         value &= ~GLI_9763E_CFG_LPSN_DIS;
0983     else
0984         value |= GLI_9763E_CFG_LPSN_DIS;
0985 
0986     pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG, value);
0987 
0988     pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
0989     value &= ~GLI_9763E_VHS_REV;
0990     value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
0991     pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
0992 }
0993 
0994 static int gl9763e_runtime_suspend(struct sdhci_pci_chip *chip)
0995 {
0996     struct sdhci_pci_slot *slot = chip->slots[0];
0997     struct sdhci_host *host = slot->host;
0998     u16 clock;
0999 
1000     /* Enable LPM negotiation to allow entering L1 state */
1001     gl9763e_set_low_power_negotiation(slot, true);
1002 
1003     clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1004     clock &= ~(SDHCI_CLOCK_PLL_EN | SDHCI_CLOCK_CARD_EN);
1005     sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1006 
1007     return 0;
1008 }
1009 
1010 static int gl9763e_runtime_resume(struct sdhci_pci_chip *chip)
1011 {
1012     struct sdhci_pci_slot *slot = chip->slots[0];
1013     struct sdhci_host *host = slot->host;
1014     u16 clock;
1015 
1016     if (host->mmc->ios.power_mode != MMC_POWER_ON)
1017         return 0;
1018 
1019     clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1020 
1021     clock |= SDHCI_CLOCK_PLL_EN;
1022     clock &= ~SDHCI_CLOCK_INT_STABLE;
1023     sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1024 
1025     /* Wait max 150 ms */
1026     if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE),
1027                   1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) {
1028         pr_err("%s: PLL clock never stabilised.\n",
1029                mmc_hostname(host->mmc));
1030         sdhci_dumpregs(host);
1031     }
1032 
1033     clock |= SDHCI_CLOCK_CARD_EN;
1034     sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1035 
1036     /* Disable LPM negotiation to avoid entering L1 state. */
1037     gl9763e_set_low_power_negotiation(slot, false);
1038 
1039     return 0;
1040 }
1041 #endif
1042 
1043 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
1044 {
1045     struct pci_dev *pdev = slot->chip->pdev;
1046     struct sdhci_host *host = slot->host;
1047     u32 value;
1048 
1049     host->mmc->caps |= MMC_CAP_8_BIT_DATA |
1050                MMC_CAP_1_8V_DDR |
1051                MMC_CAP_NONREMOVABLE;
1052     host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |
1053                 MMC_CAP2_HS400_1_8V |
1054                 MMC_CAP2_HS400_ES |
1055                 MMC_CAP2_NO_SDIO |
1056                 MMC_CAP2_NO_SD;
1057 
1058     pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value);
1059     if (!(value & GLI_9763E_MB_CMDQ_OFF))
1060         if (value & GLI_9763E_MB_ERP_ON)
1061             host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1062 
1063     gli_pcie_enable_msi(slot);
1064     host->mmc_host_ops.hs400_enhanced_strobe =
1065                     gl9763e_hs400_enhanced_strobe;
1066     gli_set_gl9763e(slot);
1067     sdhci_enable_v4_mode(host);
1068 
1069     return 0;
1070 }
1071 
1072 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
1073 
1074 static u16 sdhci_gli_readw(struct sdhci_host *host, int reg)
1075 {
1076     u32 val = readl(host->ioaddr + (reg & ~3));
1077     u16 word;
1078 
1079     word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff;
1080     return word;
1081 }
1082 
1083 static u8 sdhci_gli_readb(struct sdhci_host *host, int reg)
1084 {
1085     u32 val = readl(host->ioaddr + (reg & ~3));
1086     u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff;
1087 
1088     return byte;
1089 }
1090 
1091 static const struct sdhci_ops sdhci_gl9755_ops = {
1092     .read_w         = sdhci_gli_readw,
1093     .read_b         = sdhci_gli_readb,
1094     .set_clock      = sdhci_gl9755_set_clock,
1095     .enable_dma     = sdhci_pci_enable_dma,
1096     .set_bus_width      = sdhci_set_bus_width,
1097     .reset          = sdhci_reset,
1098     .set_uhs_signaling  = sdhci_set_uhs_signaling,
1099     .voltage_switch     = sdhci_gli_voltage_switch,
1100 };
1101 
1102 const struct sdhci_pci_fixes sdhci_gl9755 = {
1103     .quirks     = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1104     .quirks2    = SDHCI_QUIRK2_BROKEN_DDR50,
1105     .probe_slot = gli_probe_slot_gl9755,
1106     .ops            = &sdhci_gl9755_ops,
1107 #ifdef CONFIG_PM_SLEEP
1108     .resume         = sdhci_pci_gli_resume,
1109 #endif
1110 };
1111 
1112 static const struct sdhci_ops sdhci_gl9750_ops = {
1113     .read_w         = sdhci_gli_readw,
1114     .read_b         = sdhci_gli_readb,
1115     .read_l                 = sdhci_gl9750_readl,
1116     .set_clock      = sdhci_gl9750_set_clock,
1117     .enable_dma     = sdhci_pci_enable_dma,
1118     .set_bus_width      = sdhci_set_bus_width,
1119     .reset          = sdhci_gl9750_reset,
1120     .set_uhs_signaling  = sdhci_set_uhs_signaling,
1121     .voltage_switch     = sdhci_gli_voltage_switch,
1122     .platform_execute_tuning = gl9750_execute_tuning,
1123 };
1124 
1125 const struct sdhci_pci_fixes sdhci_gl9750 = {
1126     .quirks     = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1127     .quirks2    = SDHCI_QUIRK2_BROKEN_DDR50,
1128     .probe_slot = gli_probe_slot_gl9750,
1129     .ops            = &sdhci_gl9750_ops,
1130 #ifdef CONFIG_PM_SLEEP
1131     .resume         = sdhci_pci_gli_resume,
1132 #endif
1133 };
1134 
1135 static const struct sdhci_ops sdhci_gl9763e_ops = {
1136     .set_clock      = sdhci_set_clock,
1137     .enable_dma     = sdhci_pci_enable_dma,
1138     .set_bus_width      = sdhci_set_bus_width,
1139     .reset          = sdhci_gl9763e_reset,
1140     .set_uhs_signaling  = sdhci_set_gl9763e_signaling,
1141     .voltage_switch     = sdhci_gli_voltage_switch,
1142     .irq                    = sdhci_gl9763e_cqhci_irq,
1143 };
1144 
1145 const struct sdhci_pci_fixes sdhci_gl9763e = {
1146     .quirks     = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1147     .probe_slot = gli_probe_slot_gl9763e,
1148     .ops            = &sdhci_gl9763e_ops,
1149 #ifdef CONFIG_PM_SLEEP
1150     .resume     = sdhci_cqhci_gli_resume,
1151     .suspend    = sdhci_cqhci_gli_suspend,
1152 #endif
1153 #ifdef CONFIG_PM
1154     .runtime_suspend = gl9763e_runtime_suspend,
1155     .runtime_resume  = gl9763e_runtime_resume,
1156     .allow_runtime_pm = true,
1157 #endif
1158     .add_host       = gl9763e_add_host,
1159 };
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