mmc/host/sdhci-pci-dwc-mshc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * SDHCI driver for Synopsys DWC_MSHC controller
0004  *
0005  * Copyright (C) 2018 Synopsys, Inc. (www.synopsys.com)
0006  *
0007  * Authors:
0008  *  Prabu Thangamuthu <prabu.t@synopsys.com>
0009  *  Manjunath M B <manjumb@synopsys.com>
0010  */
0011
0012 #include "sdhci.h"
0013 #include "sdhci-pci.h"
0014
0015 #define SDHCI_VENDOR_PTR_R  0xE8
0016
0017 /* Synopsys vendor specific registers */
0018 #define SDHC_GPIO_OUT       0x34
0019 #define SDHC_AT_CTRL_R      0x40
0020 #define SDHC_SW_TUNE_EN     0x00000010
0021
0022 /* MMCM DRP */
0023 #define SDHC_MMCM_DIV_REG   0x1020
0024 #define DIV_REG_100_MHZ     0x1145
0025 #define DIV_REG_200_MHZ     0x1083
0026 #define SDHC_MMCM_CLKFBOUT  0x1024
0027 #define CLKFBOUT_100_MHZ    0x0000
0028 #define CLKFBOUT_200_MHZ    0x0080
0029 #define SDHC_CCLK_MMCM_RST  0x00000001
0030
0031 static void sdhci_snps_set_clock(struct sdhci_host *host, unsigned int clock)
0032 {
0033     u16 clk;
0034     u32 reg, vendor_ptr;
0035
0036     vendor_ptr = sdhci_readw(host, SDHCI_VENDOR_PTR_R);
0037
0038     /* Disable software managed rx tuning */
0039     reg = sdhci_readl(host, (SDHC_AT_CTRL_R + vendor_ptr));
0040     reg &= ~SDHC_SW_TUNE_EN;
0041     sdhci_writel(host, reg, (SDHC_AT_CTRL_R + vendor_ptr));
0042
0043     if (clock <= 52000000) {
0044         sdhci_set_clock(host, clock);
0045     } else {
0046         /* Assert reset to MMCM */
0047         reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr));
0048         reg |= SDHC_CCLK_MMCM_RST;
0049         sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr));
0050
0051         /* Configure MMCM */
0052         if (clock == 100000000) {
0053             sdhci_writel(host, DIV_REG_100_MHZ, SDHC_MMCM_DIV_REG);
0054             sdhci_writel(host, CLKFBOUT_100_MHZ,
0055                     SDHC_MMCM_CLKFBOUT);
0056         } else {
0057             sdhci_writel(host, DIV_REG_200_MHZ, SDHC_MMCM_DIV_REG);
0058             sdhci_writel(host, CLKFBOUT_200_MHZ,
0059                     SDHC_MMCM_CLKFBOUT);
0060         }
0061
0062         /* De-assert reset to MMCM */
0063         reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr));
0064         reg &= ~SDHC_CCLK_MMCM_RST;
0065         sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr));
0066
0067         /* Enable clock */
0068         clk = SDHCI_PROG_CLOCK_MODE | SDHCI_CLOCK_INT_EN |
0069             SDHCI_CLOCK_CARD_EN;
0070         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
0071     }
0072 }
0073
0074 static const struct sdhci_ops sdhci_snps_ops = {
0075     .set_clock  = sdhci_snps_set_clock,
0076     .enable_dma = sdhci_pci_enable_dma,
0077     .set_bus_width  = sdhci_set_bus_width,
0078     .reset      = sdhci_reset,
0079     .set_uhs_signaling = sdhci_set_uhs_signaling,
0080 };
0081
0082 const struct sdhci_pci_fixes sdhci_snps = {
0083     .ops        = &sdhci_snps_ops,
0084 };