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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*  linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
0003  *
0004  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
0005  *
0006  * Thanks to the following companies for their support:
0007  *
0008  *     - JMicron (hardware and technical support)
0009  */
0010 
0011 #include <linux/bitfield.h>
0012 #include <linux/string.h>
0013 #include <linux/delay.h>
0014 #include <linux/highmem.h>
0015 #include <linux/module.h>
0016 #include <linux/pci.h>
0017 #include <linux/dma-mapping.h>
0018 #include <linux/slab.h>
0019 #include <linux/device.h>
0020 #include <linux/scatterlist.h>
0021 #include <linux/io.h>
0022 #include <linux/iopoll.h>
0023 #include <linux/gpio.h>
0024 #include <linux/pm_runtime.h>
0025 #include <linux/pm_qos.h>
0026 #include <linux/debugfs.h>
0027 #include <linux/acpi.h>
0028 #include <linux/dmi.h>
0029 
0030 #include <linux/mmc/host.h>
0031 #include <linux/mmc/mmc.h>
0032 #include <linux/mmc/slot-gpio.h>
0033 
0034 #ifdef CONFIG_X86
0035 #include <asm/iosf_mbi.h>
0036 #endif
0037 
0038 #include "cqhci.h"
0039 
0040 #include "sdhci.h"
0041 #include "sdhci-pci.h"
0042 
0043 static void sdhci_pci_hw_reset(struct sdhci_host *host);
0044 
0045 #ifdef CONFIG_PM_SLEEP
0046 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
0047 {
0048     mmc_pm_flag_t pm_flags = 0;
0049     bool cap_cd_wake = false;
0050     int i;
0051 
0052     for (i = 0; i < chip->num_slots; i++) {
0053         struct sdhci_pci_slot *slot = chip->slots[i];
0054 
0055         if (slot) {
0056             pm_flags |= slot->host->mmc->pm_flags;
0057             if (slot->host->mmc->caps & MMC_CAP_CD_WAKE)
0058                 cap_cd_wake = true;
0059         }
0060     }
0061 
0062     if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ))
0063         return device_wakeup_enable(&chip->pdev->dev);
0064     else if (!cap_cd_wake)
0065         return device_wakeup_disable(&chip->pdev->dev);
0066 
0067     return 0;
0068 }
0069 
0070 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
0071 {
0072     int i, ret;
0073 
0074     sdhci_pci_init_wakeup(chip);
0075 
0076     for (i = 0; i < chip->num_slots; i++) {
0077         struct sdhci_pci_slot *slot = chip->slots[i];
0078         struct sdhci_host *host;
0079 
0080         if (!slot)
0081             continue;
0082 
0083         host = slot->host;
0084 
0085         if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
0086             mmc_retune_needed(host->mmc);
0087 
0088         ret = sdhci_suspend_host(host);
0089         if (ret)
0090             goto err_pci_suspend;
0091 
0092         if (device_may_wakeup(&chip->pdev->dev))
0093             mmc_gpio_set_cd_wake(host->mmc, true);
0094     }
0095 
0096     return 0;
0097 
0098 err_pci_suspend:
0099     while (--i >= 0)
0100         sdhci_resume_host(chip->slots[i]->host);
0101     return ret;
0102 }
0103 
0104 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
0105 {
0106     struct sdhci_pci_slot *slot;
0107     int i, ret;
0108 
0109     for (i = 0; i < chip->num_slots; i++) {
0110         slot = chip->slots[i];
0111         if (!slot)
0112             continue;
0113 
0114         ret = sdhci_resume_host(slot->host);
0115         if (ret)
0116             return ret;
0117 
0118         mmc_gpio_set_cd_wake(slot->host->mmc, false);
0119     }
0120 
0121     return 0;
0122 }
0123 
0124 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
0125 {
0126     int ret;
0127 
0128     ret = cqhci_suspend(chip->slots[0]->host->mmc);
0129     if (ret)
0130         return ret;
0131 
0132     return sdhci_pci_suspend_host(chip);
0133 }
0134 
0135 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
0136 {
0137     int ret;
0138 
0139     ret = sdhci_pci_resume_host(chip);
0140     if (ret)
0141         return ret;
0142 
0143     return cqhci_resume(chip->slots[0]->host->mmc);
0144 }
0145 #endif
0146 
0147 #ifdef CONFIG_PM
0148 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
0149 {
0150     struct sdhci_pci_slot *slot;
0151     struct sdhci_host *host;
0152     int i, ret;
0153 
0154     for (i = 0; i < chip->num_slots; i++) {
0155         slot = chip->slots[i];
0156         if (!slot)
0157             continue;
0158 
0159         host = slot->host;
0160 
0161         ret = sdhci_runtime_suspend_host(host);
0162         if (ret)
0163             goto err_pci_runtime_suspend;
0164 
0165         if (chip->rpm_retune &&
0166             host->tuning_mode != SDHCI_TUNING_MODE_3)
0167             mmc_retune_needed(host->mmc);
0168     }
0169 
0170     return 0;
0171 
0172 err_pci_runtime_suspend:
0173     while (--i >= 0)
0174         sdhci_runtime_resume_host(chip->slots[i]->host, 0);
0175     return ret;
0176 }
0177 
0178 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
0179 {
0180     struct sdhci_pci_slot *slot;
0181     int i, ret;
0182 
0183     for (i = 0; i < chip->num_slots; i++) {
0184         slot = chip->slots[i];
0185         if (!slot)
0186             continue;
0187 
0188         ret = sdhci_runtime_resume_host(slot->host, 0);
0189         if (ret)
0190             return ret;
0191     }
0192 
0193     return 0;
0194 }
0195 
0196 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
0197 {
0198     int ret;
0199 
0200     ret = cqhci_suspend(chip->slots[0]->host->mmc);
0201     if (ret)
0202         return ret;
0203 
0204     return sdhci_pci_runtime_suspend_host(chip);
0205 }
0206 
0207 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
0208 {
0209     int ret;
0210 
0211     ret = sdhci_pci_runtime_resume_host(chip);
0212     if (ret)
0213         return ret;
0214 
0215     return cqhci_resume(chip->slots[0]->host->mmc);
0216 }
0217 #endif
0218 
0219 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
0220 {
0221     int cmd_error = 0;
0222     int data_error = 0;
0223 
0224     if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
0225         return intmask;
0226 
0227     cqhci_irq(host->mmc, intmask, cmd_error, data_error);
0228 
0229     return 0;
0230 }
0231 
0232 static void sdhci_pci_dumpregs(struct mmc_host *mmc)
0233 {
0234     sdhci_dumpregs(mmc_priv(mmc));
0235 }
0236 
0237 static void sdhci_cqhci_reset(struct sdhci_host *host, u8 mask)
0238 {
0239     if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) &&
0240         host->mmc->cqe_private)
0241         cqhci_deactivate(host->mmc);
0242     sdhci_reset(host, mask);
0243 }
0244 
0245 /*****************************************************************************\
0246  *                                                                           *
0247  * Hardware specific quirk handling                                          *
0248  *                                                                           *
0249 \*****************************************************************************/
0250 
0251 static int ricoh_probe(struct sdhci_pci_chip *chip)
0252 {
0253     if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
0254         chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
0255         chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
0256     return 0;
0257 }
0258 
0259 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
0260 {
0261     slot->host->caps =
0262         FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) |
0263         FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) |
0264         SDHCI_TIMEOUT_CLK_UNIT |
0265         SDHCI_CAN_VDD_330 |
0266         SDHCI_CAN_DO_HISPD |
0267         SDHCI_CAN_DO_SDMA;
0268     return 0;
0269 }
0270 
0271 #ifdef CONFIG_PM_SLEEP
0272 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
0273 {
0274     /* Apply a delay to allow controller to settle */
0275     /* Otherwise it becomes confused if card state changed
0276         during suspend */
0277     msleep(500);
0278     return sdhci_pci_resume_host(chip);
0279 }
0280 #endif
0281 
0282 static const struct sdhci_pci_fixes sdhci_ricoh = {
0283     .probe      = ricoh_probe,
0284     .quirks     = SDHCI_QUIRK_32BIT_DMA_ADDR |
0285               SDHCI_QUIRK_FORCE_DMA |
0286               SDHCI_QUIRK_CLOCK_BEFORE_RESET,
0287 };
0288 
0289 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
0290     .probe_slot = ricoh_mmc_probe_slot,
0291 #ifdef CONFIG_PM_SLEEP
0292     .resume     = ricoh_mmc_resume,
0293 #endif
0294     .quirks     = SDHCI_QUIRK_32BIT_DMA_ADDR |
0295               SDHCI_QUIRK_CLOCK_BEFORE_RESET |
0296               SDHCI_QUIRK_NO_CARD_NO_RESET |
0297               SDHCI_QUIRK_MISSING_CAPS
0298 };
0299 
0300 static const struct sdhci_pci_fixes sdhci_ene_712 = {
0301     .quirks     = SDHCI_QUIRK_SINGLE_POWER_WRITE |
0302               SDHCI_QUIRK_BROKEN_DMA,
0303 };
0304 
0305 static const struct sdhci_pci_fixes sdhci_ene_714 = {
0306     .quirks     = SDHCI_QUIRK_SINGLE_POWER_WRITE |
0307               SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
0308               SDHCI_QUIRK_BROKEN_DMA,
0309 };
0310 
0311 static const struct sdhci_pci_fixes sdhci_cafe = {
0312     .quirks     = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
0313               SDHCI_QUIRK_NO_BUSY_IRQ |
0314               SDHCI_QUIRK_BROKEN_CARD_DETECTION |
0315               SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
0316 };
0317 
0318 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
0319     .quirks     = SDHCI_QUIRK_NO_HISPD_BIT,
0320 };
0321 
0322 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
0323 {
0324     slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
0325     return 0;
0326 }
0327 
0328 /*
0329  * ADMA operation is disabled for Moorestown platform due to
0330  * hardware bugs.
0331  */
0332 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
0333 {
0334     /*
0335      * slots number is fixed here for MRST as SDIO3/5 are never used and
0336      * have hardware bugs.
0337      */
0338     chip->num_slots = 1;
0339     return 0;
0340 }
0341 
0342 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
0343 {
0344     slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
0345     return 0;
0346 }
0347 
0348 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
0349 {
0350     slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
0351     slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
0352     return 0;
0353 }
0354 
0355 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
0356 {
0357     slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
0358     return 0;
0359 }
0360 
0361 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
0362     .quirks     = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
0363     .probe_slot = mrst_hc_probe_slot,
0364 };
0365 
0366 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
0367     .quirks     = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
0368     .probe      = mrst_hc_probe,
0369 };
0370 
0371 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
0372     .quirks     = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
0373     .allow_runtime_pm = true,
0374     .own_cd_for_runtime_pm = true,
0375 };
0376 
0377 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
0378     .quirks     = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
0379     .quirks2    = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
0380     .allow_runtime_pm = true,
0381     .probe_slot = mfd_sdio_probe_slot,
0382 };
0383 
0384 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
0385     .quirks     = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
0386     .allow_runtime_pm = true,
0387     .probe_slot = mfd_emmc_probe_slot,
0388 };
0389 
0390 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
0391     .quirks     = SDHCI_QUIRK_BROKEN_ADMA,
0392     .probe_slot = pch_hc_probe_slot,
0393 };
0394 
0395 #ifdef CONFIG_X86
0396 
0397 #define BYT_IOSF_SCCEP          0x63
0398 #define BYT_IOSF_OCP_NETCTRL0       0x1078
0399 #define BYT_IOSF_OCP_TIMEOUT_BASE   GENMASK(10, 8)
0400 
0401 static void byt_ocp_setting(struct pci_dev *pdev)
0402 {
0403     u32 val = 0;
0404 
0405     if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC &&
0406         pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO &&
0407         pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD &&
0408         pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2)
0409         return;
0410 
0411     if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
0412               &val)) {
0413         dev_err(&pdev->dev, "%s read error\n", __func__);
0414         return;
0415     }
0416 
0417     if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
0418         return;
0419 
0420     val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
0421 
0422     if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
0423                val)) {
0424         dev_err(&pdev->dev, "%s write error\n", __func__);
0425         return;
0426     }
0427 
0428     dev_dbg(&pdev->dev, "%s completed\n", __func__);
0429 }
0430 
0431 #else
0432 
0433 static inline void byt_ocp_setting(struct pci_dev *pdev)
0434 {
0435 }
0436 
0437 #endif
0438 
0439 enum {
0440     INTEL_DSM_FNS       =  0,
0441     INTEL_DSM_V18_SWITCH    =  3,
0442     INTEL_DSM_V33_SWITCH    =  4,
0443     INTEL_DSM_DRV_STRENGTH  =  9,
0444     INTEL_DSM_D3_RETUNE = 10,
0445 };
0446 
0447 struct intel_host {
0448     u32 dsm_fns;
0449     int drv_strength;
0450     bool    d3_retune;
0451     bool    rpm_retune_ok;
0452     bool    needs_pwr_off;
0453     u32 glk_rx_ctrl1;
0454     u32 glk_tun_val;
0455     u32 active_ltr;
0456     u32 idle_ltr;
0457 };
0458 
0459 static const guid_t intel_dsm_guid =
0460     GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
0461           0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
0462 
0463 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
0464                unsigned int fn, u32 *result)
0465 {
0466     union acpi_object *obj;
0467     int err = 0;
0468     size_t len;
0469 
0470     obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
0471     if (!obj)
0472         return -EOPNOTSUPP;
0473 
0474     if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
0475         err = -EINVAL;
0476         goto out;
0477     }
0478 
0479     len = min_t(size_t, obj->buffer.length, 4);
0480 
0481     *result = 0;
0482     memcpy(result, obj->buffer.pointer, len);
0483 out:
0484     ACPI_FREE(obj);
0485 
0486     return err;
0487 }
0488 
0489 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
0490              unsigned int fn, u32 *result)
0491 {
0492     if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
0493         return -EOPNOTSUPP;
0494 
0495     return __intel_dsm(intel_host, dev, fn, result);
0496 }
0497 
0498 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
0499                struct mmc_host *mmc)
0500 {
0501     int err;
0502     u32 val;
0503 
0504     intel_host->d3_retune = true;
0505 
0506     err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
0507     if (err) {
0508         pr_debug("%s: DSM not supported, error %d\n",
0509              mmc_hostname(mmc), err);
0510         return;
0511     }
0512 
0513     pr_debug("%s: DSM function mask %#x\n",
0514          mmc_hostname(mmc), intel_host->dsm_fns);
0515 
0516     err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
0517     intel_host->drv_strength = err ? 0 : val;
0518 
0519     err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
0520     intel_host->d3_retune = err ? true : !!val;
0521 }
0522 
0523 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
0524 {
0525     u8 reg;
0526 
0527     reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
0528     reg |= 0x10;
0529     sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
0530     /* For eMMC, minimum is 1us but give it 9us for good measure */
0531     udelay(9);
0532     reg &= ~0x10;
0533     sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
0534     /* For eMMC, minimum is 200us but give it 300us for good measure */
0535     usleep_range(300, 1000);
0536 }
0537 
0538 static int intel_select_drive_strength(struct mmc_card *card,
0539                        unsigned int max_dtr, int host_drv,
0540                        int card_drv, int *drv_type)
0541 {
0542     struct sdhci_host *host = mmc_priv(card->host);
0543     struct sdhci_pci_slot *slot = sdhci_priv(host);
0544     struct intel_host *intel_host = sdhci_pci_priv(slot);
0545 
0546     if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv))
0547         return 0;
0548 
0549     return intel_host->drv_strength;
0550 }
0551 
0552 static int bxt_get_cd(struct mmc_host *mmc)
0553 {
0554     int gpio_cd = mmc_gpio_get_cd(mmc);
0555 
0556     if (!gpio_cd)
0557         return 0;
0558 
0559     return sdhci_get_cd_nogpio(mmc);
0560 }
0561 
0562 static int mrfld_get_cd(struct mmc_host *mmc)
0563 {
0564     return sdhci_get_cd_nogpio(mmc);
0565 }
0566 
0567 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
0568 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY  100
0569 
0570 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
0571                   unsigned short vdd)
0572 {
0573     struct sdhci_pci_slot *slot = sdhci_priv(host);
0574     struct intel_host *intel_host = sdhci_pci_priv(slot);
0575     int cntr;
0576     u8 reg;
0577 
0578     /*
0579      * Bus power may control card power, but a full reset still may not
0580      * reset the power, whereas a direct write to SDHCI_POWER_CONTROL can.
0581      * That might be needed to initialize correctly, if the card was left
0582      * powered on previously.
0583      */
0584     if (intel_host->needs_pwr_off) {
0585         intel_host->needs_pwr_off = false;
0586         if (mode != MMC_POWER_OFF) {
0587             sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
0588             usleep_range(10000, 12500);
0589         }
0590     }
0591 
0592     sdhci_set_power(host, mode, vdd);
0593 
0594     if (mode == MMC_POWER_OFF)
0595         return;
0596 
0597     /*
0598      * Bus power might not enable after D3 -> D0 transition due to the
0599      * present state not yet having propagated. Retry for up to 2ms.
0600      */
0601     for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
0602         reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
0603         if (reg & SDHCI_POWER_ON)
0604             break;
0605         udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
0606         reg |= SDHCI_POWER_ON;
0607         sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
0608     }
0609 }
0610 
0611 static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host,
0612                       unsigned int timing)
0613 {
0614     /* Set UHS timing to SDR25 for High Speed mode */
0615     if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS)
0616         timing = MMC_TIMING_UHS_SDR25;
0617     sdhci_set_uhs_signaling(host, timing);
0618 }
0619 
0620 #define INTEL_HS400_ES_REG 0x78
0621 #define INTEL_HS400_ES_BIT BIT(0)
0622 
0623 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
0624                     struct mmc_ios *ios)
0625 {
0626     struct sdhci_host *host = mmc_priv(mmc);
0627     u32 val;
0628 
0629     val = sdhci_readl(host, INTEL_HS400_ES_REG);
0630     if (ios->enhanced_strobe)
0631         val |= INTEL_HS400_ES_BIT;
0632     else
0633         val &= ~INTEL_HS400_ES_BIT;
0634     sdhci_writel(host, val, INTEL_HS400_ES_REG);
0635 }
0636 
0637 static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
0638                          struct mmc_ios *ios)
0639 {
0640     struct device *dev = mmc_dev(mmc);
0641     struct sdhci_host *host = mmc_priv(mmc);
0642     struct sdhci_pci_slot *slot = sdhci_priv(host);
0643     struct intel_host *intel_host = sdhci_pci_priv(slot);
0644     unsigned int fn;
0645     u32 result = 0;
0646     int err;
0647 
0648     err = sdhci_start_signal_voltage_switch(mmc, ios);
0649     if (err)
0650         return err;
0651 
0652     switch (ios->signal_voltage) {
0653     case MMC_SIGNAL_VOLTAGE_330:
0654         fn = INTEL_DSM_V33_SWITCH;
0655         break;
0656     case MMC_SIGNAL_VOLTAGE_180:
0657         fn = INTEL_DSM_V18_SWITCH;
0658         break;
0659     default:
0660         return 0;
0661     }
0662 
0663     err = intel_dsm(intel_host, dev, fn, &result);
0664     pr_debug("%s: %s DSM fn %u error %d result %u\n",
0665          mmc_hostname(mmc), __func__, fn, err, result);
0666 
0667     return 0;
0668 }
0669 
0670 static const struct sdhci_ops sdhci_intel_byt_ops = {
0671     .set_clock      = sdhci_set_clock,
0672     .set_power      = sdhci_intel_set_power,
0673     .enable_dma     = sdhci_pci_enable_dma,
0674     .set_bus_width      = sdhci_set_bus_width,
0675     .reset          = sdhci_reset,
0676     .set_uhs_signaling  = sdhci_intel_set_uhs_signaling,
0677     .hw_reset       = sdhci_pci_hw_reset,
0678 };
0679 
0680 static const struct sdhci_ops sdhci_intel_glk_ops = {
0681     .set_clock      = sdhci_set_clock,
0682     .set_power      = sdhci_intel_set_power,
0683     .enable_dma     = sdhci_pci_enable_dma,
0684     .set_bus_width      = sdhci_set_bus_width,
0685     .reset          = sdhci_cqhci_reset,
0686     .set_uhs_signaling  = sdhci_intel_set_uhs_signaling,
0687     .hw_reset       = sdhci_pci_hw_reset,
0688     .irq            = sdhci_cqhci_irq,
0689 };
0690 
0691 static void byt_read_dsm(struct sdhci_pci_slot *slot)
0692 {
0693     struct intel_host *intel_host = sdhci_pci_priv(slot);
0694     struct device *dev = &slot->chip->pdev->dev;
0695     struct mmc_host *mmc = slot->host->mmc;
0696 
0697     intel_dsm_init(intel_host, dev, mmc);
0698     slot->chip->rpm_retune = intel_host->d3_retune;
0699 }
0700 
0701 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
0702 {
0703     int err = sdhci_execute_tuning(mmc, opcode);
0704     struct sdhci_host *host = mmc_priv(mmc);
0705 
0706     if (err)
0707         return err;
0708 
0709     /*
0710      * Tuning can leave the IP in an active state (Buffer Read Enable bit
0711      * set) which prevents the entry to low power states (i.e. S0i3). Data
0712      * reset will clear it.
0713      */
0714     sdhci_reset(host, SDHCI_RESET_DATA);
0715 
0716     return 0;
0717 }
0718 
0719 #define INTEL_ACTIVELTR     0x804
0720 #define INTEL_IDLELTR       0x808
0721 
0722 #define INTEL_LTR_REQ       BIT(15)
0723 #define INTEL_LTR_SCALE_MASK    GENMASK(11, 10)
0724 #define INTEL_LTR_SCALE_1US (2 << 10)
0725 #define INTEL_LTR_SCALE_32US    (3 << 10)
0726 #define INTEL_LTR_VALUE_MASK    GENMASK(9, 0)
0727 
0728 static void intel_cache_ltr(struct sdhci_pci_slot *slot)
0729 {
0730     struct intel_host *intel_host = sdhci_pci_priv(slot);
0731     struct sdhci_host *host = slot->host;
0732 
0733     intel_host->active_ltr = readl(host->ioaddr + INTEL_ACTIVELTR);
0734     intel_host->idle_ltr = readl(host->ioaddr + INTEL_IDLELTR);
0735 }
0736 
0737 static void intel_ltr_set(struct device *dev, s32 val)
0738 {
0739     struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
0740     struct sdhci_pci_slot *slot = chip->slots[0];
0741     struct intel_host *intel_host = sdhci_pci_priv(slot);
0742     struct sdhci_host *host = slot->host;
0743     u32 ltr;
0744 
0745     pm_runtime_get_sync(dev);
0746 
0747     /*
0748      * Program latency tolerance (LTR) accordingly what has been asked
0749      * by the PM QoS layer or disable it in case we were passed
0750      * negative value or PM_QOS_LATENCY_ANY.
0751      */
0752     ltr = readl(host->ioaddr + INTEL_ACTIVELTR);
0753 
0754     if (val == PM_QOS_LATENCY_ANY || val < 0) {
0755         ltr &= ~INTEL_LTR_REQ;
0756     } else {
0757         ltr |= INTEL_LTR_REQ;
0758         ltr &= ~INTEL_LTR_SCALE_MASK;
0759         ltr &= ~INTEL_LTR_VALUE_MASK;
0760 
0761         if (val > INTEL_LTR_VALUE_MASK) {
0762             val >>= 5;
0763             if (val > INTEL_LTR_VALUE_MASK)
0764                 val = INTEL_LTR_VALUE_MASK;
0765             ltr |= INTEL_LTR_SCALE_32US | val;
0766         } else {
0767             ltr |= INTEL_LTR_SCALE_1US | val;
0768         }
0769     }
0770 
0771     if (ltr == intel_host->active_ltr)
0772         goto out;
0773 
0774     writel(ltr, host->ioaddr + INTEL_ACTIVELTR);
0775     writel(ltr, host->ioaddr + INTEL_IDLELTR);
0776 
0777     /* Cache the values into lpss structure */
0778     intel_cache_ltr(slot);
0779 out:
0780     pm_runtime_put_autosuspend(dev);
0781 }
0782 
0783 static bool intel_use_ltr(struct sdhci_pci_chip *chip)
0784 {
0785     switch (chip->pdev->device) {
0786     case PCI_DEVICE_ID_INTEL_BYT_EMMC:
0787     case PCI_DEVICE_ID_INTEL_BYT_EMMC2:
0788     case PCI_DEVICE_ID_INTEL_BYT_SDIO:
0789     case PCI_DEVICE_ID_INTEL_BYT_SD:
0790     case PCI_DEVICE_ID_INTEL_BSW_EMMC:
0791     case PCI_DEVICE_ID_INTEL_BSW_SDIO:
0792     case PCI_DEVICE_ID_INTEL_BSW_SD:
0793         return false;
0794     default:
0795         return true;
0796     }
0797 }
0798 
0799 static void intel_ltr_expose(struct sdhci_pci_chip *chip)
0800 {
0801     struct device *dev = &chip->pdev->dev;
0802 
0803     if (!intel_use_ltr(chip))
0804         return;
0805 
0806     dev->power.set_latency_tolerance = intel_ltr_set;
0807     dev_pm_qos_expose_latency_tolerance(dev);
0808 }
0809 
0810 static void intel_ltr_hide(struct sdhci_pci_chip *chip)
0811 {
0812     struct device *dev = &chip->pdev->dev;
0813 
0814     if (!intel_use_ltr(chip))
0815         return;
0816 
0817     dev_pm_qos_hide_latency_tolerance(dev);
0818     dev->power.set_latency_tolerance = NULL;
0819 }
0820 
0821 static void byt_probe_slot(struct sdhci_pci_slot *slot)
0822 {
0823     struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
0824     struct device *dev = &slot->chip->pdev->dev;
0825     struct mmc_host *mmc = slot->host->mmc;
0826 
0827     byt_read_dsm(slot);
0828 
0829     byt_ocp_setting(slot->chip->pdev);
0830 
0831     ops->execute_tuning = intel_execute_tuning;
0832     ops->start_signal_voltage_switch = intel_start_signal_voltage_switch;
0833 
0834     device_property_read_u32(dev, "max-frequency", &mmc->f_max);
0835 
0836     if (!mmc->slotno) {
0837         slot->chip->slots[mmc->slotno] = slot;
0838         intel_ltr_expose(slot->chip);
0839     }
0840 }
0841 
0842 static void byt_add_debugfs(struct sdhci_pci_slot *slot)
0843 {
0844     struct intel_host *intel_host = sdhci_pci_priv(slot);
0845     struct mmc_host *mmc = slot->host->mmc;
0846     struct dentry *dir = mmc->debugfs_root;
0847 
0848     if (!intel_use_ltr(slot->chip))
0849         return;
0850 
0851     debugfs_create_x32("active_ltr", 0444, dir, &intel_host->active_ltr);
0852     debugfs_create_x32("idle_ltr", 0444, dir, &intel_host->idle_ltr);
0853 
0854     intel_cache_ltr(slot);
0855 }
0856 
0857 static int byt_add_host(struct sdhci_pci_slot *slot)
0858 {
0859     int ret = sdhci_add_host(slot->host);
0860 
0861     if (!ret)
0862         byt_add_debugfs(slot);
0863     return ret;
0864 }
0865 
0866 static void byt_remove_slot(struct sdhci_pci_slot *slot, int dead)
0867 {
0868     struct mmc_host *mmc = slot->host->mmc;
0869 
0870     if (!mmc->slotno)
0871         intel_ltr_hide(slot->chip);
0872 }
0873 
0874 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
0875 {
0876     byt_probe_slot(slot);
0877     slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
0878                  MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
0879                  MMC_CAP_CMD_DURING_TFR |
0880                  MMC_CAP_WAIT_WHILE_BUSY;
0881     slot->hw_reset = sdhci_pci_int_hw_reset;
0882     if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
0883         slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
0884     slot->host->mmc_host_ops.select_drive_strength =
0885                         intel_select_drive_strength;
0886     return 0;
0887 }
0888 
0889 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot)
0890 {
0891     return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
0892            (dmi_match(DMI_BIOS_VENDOR, "LENOVO") ||
0893         dmi_match(DMI_SYS_VENDOR, "IRBIS"));
0894 }
0895 
0896 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
0897 {
0898     int ret = byt_emmc_probe_slot(slot);
0899 
0900     if (!glk_broken_cqhci(slot))
0901         slot->host->mmc->caps2 |= MMC_CAP2_CQE;
0902 
0903     if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
0904         slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES;
0905         slot->host->mmc_host_ops.hs400_enhanced_strobe =
0906                         intel_hs400_enhanced_strobe;
0907         slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
0908     }
0909 
0910     return ret;
0911 }
0912 
0913 static const struct cqhci_host_ops glk_cqhci_ops = {
0914     .enable     = sdhci_cqe_enable,
0915     .disable    = sdhci_cqe_disable,
0916     .dumpregs   = sdhci_pci_dumpregs,
0917 };
0918 
0919 static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
0920 {
0921     struct device *dev = &slot->chip->pdev->dev;
0922     struct sdhci_host *host = slot->host;
0923     struct cqhci_host *cq_host;
0924     bool dma64;
0925     int ret;
0926 
0927     ret = sdhci_setup_host(host);
0928     if (ret)
0929         return ret;
0930 
0931     cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
0932     if (!cq_host) {
0933         ret = -ENOMEM;
0934         goto cleanup;
0935     }
0936 
0937     cq_host->mmio = host->ioaddr + 0x200;
0938     cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
0939     cq_host->ops = &glk_cqhci_ops;
0940 
0941     dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
0942     if (dma64)
0943         cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
0944 
0945     ret = cqhci_init(cq_host, host->mmc, dma64);
0946     if (ret)
0947         goto cleanup;
0948 
0949     ret = __sdhci_add_host(host);
0950     if (ret)
0951         goto cleanup;
0952 
0953     byt_add_debugfs(slot);
0954 
0955     return 0;
0956 
0957 cleanup:
0958     sdhci_cleanup_host(host);
0959     return ret;
0960 }
0961 
0962 #ifdef CONFIG_PM
0963 #define GLK_RX_CTRL1    0x834
0964 #define GLK_TUN_VAL 0x840
0965 #define GLK_PATH_PLL    GENMASK(13, 8)
0966 #define GLK_DLY     GENMASK(6, 0)
0967 /* Workaround firmware failing to restore the tuning value */
0968 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp)
0969 {
0970     struct sdhci_pci_slot *slot = chip->slots[0];
0971     struct intel_host *intel_host = sdhci_pci_priv(slot);
0972     struct sdhci_host *host = slot->host;
0973     u32 glk_rx_ctrl1;
0974     u32 glk_tun_val;
0975     u32 dly;
0976 
0977     if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc))
0978         return;
0979 
0980     glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1);
0981     glk_tun_val = sdhci_readl(host, GLK_TUN_VAL);
0982 
0983     if (susp) {
0984         intel_host->glk_rx_ctrl1 = glk_rx_ctrl1;
0985         intel_host->glk_tun_val = glk_tun_val;
0986         return;
0987     }
0988 
0989     if (!intel_host->glk_tun_val)
0990         return;
0991 
0992     if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) {
0993         intel_host->rpm_retune_ok = true;
0994         return;
0995     }
0996 
0997     dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) +
0998                   (intel_host->glk_tun_val << 1));
0999     if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1))
1000         return;
1001 
1002     glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly;
1003     sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1);
1004 
1005     intel_host->rpm_retune_ok = true;
1006     chip->rpm_retune = true;
1007     mmc_retune_needed(host->mmc);
1008     pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc));
1009 }
1010 
1011 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp)
1012 {
1013     if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
1014         !chip->rpm_retune)
1015         glk_rpm_retune_wa(chip, susp);
1016 }
1017 
1018 static int glk_runtime_suspend(struct sdhci_pci_chip *chip)
1019 {
1020     glk_rpm_retune_chk(chip, true);
1021 
1022     return sdhci_cqhci_runtime_suspend(chip);
1023 }
1024 
1025 static int glk_runtime_resume(struct sdhci_pci_chip *chip)
1026 {
1027     glk_rpm_retune_chk(chip, false);
1028 
1029     return sdhci_cqhci_runtime_resume(chip);
1030 }
1031 #endif
1032 
1033 #ifdef CONFIG_ACPI
1034 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
1035 {
1036     acpi_status status;
1037     unsigned long long max_freq;
1038 
1039     status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
1040                        "MXFQ", NULL, &max_freq);
1041     if (ACPI_FAILURE(status)) {
1042         dev_err(&slot->chip->pdev->dev,
1043             "MXFQ not found in acpi table\n");
1044         return -EINVAL;
1045     }
1046 
1047     slot->host->mmc->f_max = max_freq * 1000000;
1048 
1049     return 0;
1050 }
1051 #else
1052 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
1053 {
1054     return 0;
1055 }
1056 #endif
1057 
1058 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
1059 {
1060     int err;
1061 
1062     byt_probe_slot(slot);
1063 
1064     err = ni_set_max_freq(slot);
1065     if (err)
1066         return err;
1067 
1068     slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
1069                  MMC_CAP_WAIT_WHILE_BUSY;
1070     return 0;
1071 }
1072 
1073 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
1074 {
1075     byt_probe_slot(slot);
1076     slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
1077                  MMC_CAP_WAIT_WHILE_BUSY;
1078     return 0;
1079 }
1080 
1081 static void byt_needs_pwr_off(struct sdhci_pci_slot *slot)
1082 {
1083     struct intel_host *intel_host = sdhci_pci_priv(slot);
1084     u8 reg = sdhci_readb(slot->host, SDHCI_POWER_CONTROL);
1085 
1086     intel_host->needs_pwr_off = reg  & SDHCI_POWER_ON;
1087 }
1088 
1089 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
1090 {
1091     byt_probe_slot(slot);
1092     slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
1093                  MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
1094     slot->cd_idx = 0;
1095     slot->cd_override_level = true;
1096     if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
1097         slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
1098         slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
1099         slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
1100         slot->host->mmc_host_ops.get_cd = bxt_get_cd;
1101 
1102     if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI &&
1103         slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3)
1104         slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V;
1105 
1106     byt_needs_pwr_off(slot);
1107 
1108     return 0;
1109 }
1110 
1111 #ifdef CONFIG_PM_SLEEP
1112 
1113 static int byt_resume(struct sdhci_pci_chip *chip)
1114 {
1115     byt_ocp_setting(chip->pdev);
1116 
1117     return sdhci_pci_resume_host(chip);
1118 }
1119 
1120 #endif
1121 
1122 #ifdef CONFIG_PM
1123 
1124 static int byt_runtime_resume(struct sdhci_pci_chip *chip)
1125 {
1126     byt_ocp_setting(chip->pdev);
1127 
1128     return sdhci_pci_runtime_resume_host(chip);
1129 }
1130 
1131 #endif
1132 
1133 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
1134 #ifdef CONFIG_PM_SLEEP
1135     .resume     = byt_resume,
1136 #endif
1137 #ifdef CONFIG_PM
1138     .runtime_resume = byt_runtime_resume,
1139 #endif
1140     .allow_runtime_pm = true,
1141     .probe_slot = byt_emmc_probe_slot,
1142     .add_host   = byt_add_host,
1143     .remove_slot    = byt_remove_slot,
1144     .quirks     = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1145               SDHCI_QUIRK_NO_LED,
1146     .quirks2    = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1147               SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1148               SDHCI_QUIRK2_STOP_WITH_TC,
1149     .ops        = &sdhci_intel_byt_ops,
1150     .priv_size  = sizeof(struct intel_host),
1151 };
1152 
1153 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
1154     .allow_runtime_pm   = true,
1155     .probe_slot     = glk_emmc_probe_slot,
1156     .add_host       = glk_emmc_add_host,
1157     .remove_slot        = byt_remove_slot,
1158 #ifdef CONFIG_PM_SLEEP
1159     .suspend        = sdhci_cqhci_suspend,
1160     .resume         = sdhci_cqhci_resume,
1161 #endif
1162 #ifdef CONFIG_PM
1163     .runtime_suspend    = glk_runtime_suspend,
1164     .runtime_resume     = glk_runtime_resume,
1165 #endif
1166     .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1167                   SDHCI_QUIRK_NO_LED,
1168     .quirks2        = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1169                   SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1170                   SDHCI_QUIRK2_STOP_WITH_TC,
1171     .ops            = &sdhci_intel_glk_ops,
1172     .priv_size      = sizeof(struct intel_host),
1173 };
1174 
1175 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
1176 #ifdef CONFIG_PM_SLEEP
1177     .resume     = byt_resume,
1178 #endif
1179 #ifdef CONFIG_PM
1180     .runtime_resume = byt_runtime_resume,
1181 #endif
1182     .quirks     = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1183               SDHCI_QUIRK_NO_LED,
1184     .quirks2    = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1185               SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1186     .allow_runtime_pm = true,
1187     .probe_slot = ni_byt_sdio_probe_slot,
1188     .add_host   = byt_add_host,
1189     .remove_slot    = byt_remove_slot,
1190     .ops        = &sdhci_intel_byt_ops,
1191     .priv_size  = sizeof(struct intel_host),
1192 };
1193 
1194 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
1195 #ifdef CONFIG_PM_SLEEP
1196     .resume     = byt_resume,
1197 #endif
1198 #ifdef CONFIG_PM
1199     .runtime_resume = byt_runtime_resume,
1200 #endif
1201     .quirks     = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1202               SDHCI_QUIRK_NO_LED,
1203     .quirks2    = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1204             SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1205     .allow_runtime_pm = true,
1206     .probe_slot = byt_sdio_probe_slot,
1207     .add_host   = byt_add_host,
1208     .remove_slot    = byt_remove_slot,
1209     .ops        = &sdhci_intel_byt_ops,
1210     .priv_size  = sizeof(struct intel_host),
1211 };
1212 
1213 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
1214 #ifdef CONFIG_PM_SLEEP
1215     .resume     = byt_resume,
1216 #endif
1217 #ifdef CONFIG_PM
1218     .runtime_resume = byt_runtime_resume,
1219 #endif
1220     .quirks     = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1221               SDHCI_QUIRK_NO_LED,
1222     .quirks2    = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1223               SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1224               SDHCI_QUIRK2_STOP_WITH_TC,
1225     .allow_runtime_pm = true,
1226     .own_cd_for_runtime_pm = true,
1227     .probe_slot = byt_sd_probe_slot,
1228     .add_host   = byt_add_host,
1229     .remove_slot    = byt_remove_slot,
1230     .ops        = &sdhci_intel_byt_ops,
1231     .priv_size  = sizeof(struct intel_host),
1232 };
1233 
1234 /* Define Host controllers for Intel Merrifield platform */
1235 #define INTEL_MRFLD_EMMC_0  0
1236 #define INTEL_MRFLD_EMMC_1  1
1237 #define INTEL_MRFLD_SD      2
1238 #define INTEL_MRFLD_SDIO    3
1239 
1240 #ifdef CONFIG_ACPI
1241 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
1242 {
1243     struct acpi_device *device;
1244 
1245     device = ACPI_COMPANION(&slot->chip->pdev->dev);
1246     if (device)
1247         acpi_device_fix_up_power_extended(device);
1248 }
1249 #else
1250 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
1251 #endif
1252 
1253 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
1254 {
1255     unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
1256 
1257     switch (func) {
1258     case INTEL_MRFLD_EMMC_0:
1259     case INTEL_MRFLD_EMMC_1:
1260         slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1261                      MMC_CAP_8_BIT_DATA |
1262                      MMC_CAP_1_8V_DDR;
1263         break;
1264     case INTEL_MRFLD_SD:
1265         slot->cd_idx = 0;
1266         slot->cd_override_level = true;
1267         /*
1268          * There are two PCB designs of SD card slot with the opposite
1269          * card detection sense. Quirk this out by ignoring GPIO state
1270          * completely in the custom ->get_cd() callback.
1271          */
1272         slot->host->mmc_host_ops.get_cd = mrfld_get_cd;
1273         slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1274         break;
1275     case INTEL_MRFLD_SDIO:
1276         /* Advertise 2.0v for compatibility with the SDIO card's OCR */
1277         slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
1278         slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1279                      MMC_CAP_POWER_OFF_CARD;
1280         break;
1281     default:
1282         return -ENODEV;
1283     }
1284 
1285     intel_mrfld_mmc_fix_up_power_slot(slot);
1286     return 0;
1287 }
1288 
1289 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
1290     .quirks     = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1291     .quirks2    = SDHCI_QUIRK2_BROKEN_HS200 |
1292             SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1293     .allow_runtime_pm = true,
1294     .probe_slot = intel_mrfld_mmc_probe_slot,
1295 };
1296 
1297 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
1298 {
1299     u8 scratch;
1300     int ret;
1301 
1302     ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
1303     if (ret)
1304         return ret;
1305 
1306     /*
1307      * Turn PMOS on [bit 0], set over current detection to 2.4 V
1308      * [bit 1:2] and enable over current debouncing [bit 6].
1309      */
1310     if (on)
1311         scratch |= 0x47;
1312     else
1313         scratch &= ~0x47;
1314 
1315     return pci_write_config_byte(chip->pdev, 0xAE, scratch);
1316 }
1317 
1318 static int jmicron_probe(struct sdhci_pci_chip *chip)
1319 {
1320     int ret;
1321     u16 mmcdev = 0;
1322 
1323     if (chip->pdev->revision == 0) {
1324         chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
1325               SDHCI_QUIRK_32BIT_DMA_SIZE |
1326               SDHCI_QUIRK_32BIT_ADMA_SIZE |
1327               SDHCI_QUIRK_RESET_AFTER_REQUEST |
1328               SDHCI_QUIRK_BROKEN_SMALL_PIO;
1329     }
1330 
1331     /*
1332      * JMicron chips can have two interfaces to the same hardware
1333      * in order to work around limitations in Microsoft's driver.
1334      * We need to make sure we only bind to one of them.
1335      *
1336      * This code assumes two things:
1337      *
1338      * 1. The PCI code adds subfunctions in order.
1339      *
1340      * 2. The MMC interface has a lower subfunction number
1341      *    than the SD interface.
1342      */
1343     if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
1344         mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
1345     else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
1346         mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
1347 
1348     if (mmcdev) {
1349         struct pci_dev *sd_dev;
1350 
1351         sd_dev = NULL;
1352         while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
1353                         mmcdev, sd_dev)) != NULL) {
1354             if ((PCI_SLOT(chip->pdev->devfn) ==
1355                 PCI_SLOT(sd_dev->devfn)) &&
1356                 (chip->pdev->bus == sd_dev->bus))
1357                 break;
1358         }
1359 
1360         if (sd_dev) {
1361             pci_dev_put(sd_dev);
1362             dev_info(&chip->pdev->dev, "Refusing to bind to "
1363                 "secondary interface.\n");
1364             return -ENODEV;
1365         }
1366     }
1367 
1368     /*
1369      * JMicron chips need a bit of a nudge to enable the power
1370      * output pins.
1371      */
1372     ret = jmicron_pmos(chip, 1);
1373     if (ret) {
1374         dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1375         return ret;
1376     }
1377 
1378     /* quirk for unsable RO-detection on JM388 chips */
1379     if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1380         chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1381         chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1382 
1383     return 0;
1384 }
1385 
1386 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1387 {
1388     u8 scratch;
1389 
1390     scratch = readb(host->ioaddr + 0xC0);
1391 
1392     if (on)
1393         scratch |= 0x01;
1394     else
1395         scratch &= ~0x01;
1396 
1397     writeb(scratch, host->ioaddr + 0xC0);
1398 }
1399 
1400 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1401 {
1402     if (slot->chip->pdev->revision == 0) {
1403         u16 version;
1404 
1405         version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1406         version = (version & SDHCI_VENDOR_VER_MASK) >>
1407             SDHCI_VENDOR_VER_SHIFT;
1408 
1409         /*
1410          * Older versions of the chip have lots of nasty glitches
1411          * in the ADMA engine. It's best just to avoid it
1412          * completely.
1413          */
1414         if (version < 0xAC)
1415             slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1416     }
1417 
1418     /* JM388 MMC doesn't support 1.8V while SD supports it */
1419     if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1420         slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1421             MMC_VDD_29_30 | MMC_VDD_30_31 |
1422             MMC_VDD_165_195; /* allow 1.8V */
1423         slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1424             MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1425     }
1426 
1427     /*
1428      * The secondary interface requires a bit set to get the
1429      * interrupts.
1430      */
1431     if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1432         slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1433         jmicron_enable_mmc(slot->host, 1);
1434 
1435     slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1436 
1437     return 0;
1438 }
1439 
1440 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
1441 {
1442     if (dead)
1443         return;
1444 
1445     if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1446         slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1447         jmicron_enable_mmc(slot->host, 0);
1448 }
1449 
1450 #ifdef CONFIG_PM_SLEEP
1451 static int jmicron_suspend(struct sdhci_pci_chip *chip)
1452 {
1453     int i, ret;
1454 
1455     ret = sdhci_pci_suspend_host(chip);
1456     if (ret)
1457         return ret;
1458 
1459     if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1460         chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1461         for (i = 0; i < chip->num_slots; i++)
1462             jmicron_enable_mmc(chip->slots[i]->host, 0);
1463     }
1464 
1465     return 0;
1466 }
1467 
1468 static int jmicron_resume(struct sdhci_pci_chip *chip)
1469 {
1470     int ret, i;
1471 
1472     if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1473         chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1474         for (i = 0; i < chip->num_slots; i++)
1475             jmicron_enable_mmc(chip->slots[i]->host, 1);
1476     }
1477 
1478     ret = jmicron_pmos(chip, 1);
1479     if (ret) {
1480         dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1481         return ret;
1482     }
1483 
1484     return sdhci_pci_resume_host(chip);
1485 }
1486 #endif
1487 
1488 static const struct sdhci_pci_fixes sdhci_jmicron = {
1489     .probe      = jmicron_probe,
1490 
1491     .probe_slot = jmicron_probe_slot,
1492     .remove_slot    = jmicron_remove_slot,
1493 
1494 #ifdef CONFIG_PM_SLEEP
1495     .suspend    = jmicron_suspend,
1496     .resume     = jmicron_resume,
1497 #endif
1498 };
1499 
1500 /* SysKonnect CardBus2SDIO extra registers */
1501 #define SYSKT_CTRL      0x200
1502 #define SYSKT_RDFIFO_STAT   0x204
1503 #define SYSKT_WRFIFO_STAT   0x208
1504 #define SYSKT_POWER_DATA    0x20c
1505 #define   SYSKT_POWER_330   0xef
1506 #define   SYSKT_POWER_300   0xf8
1507 #define   SYSKT_POWER_184   0xcc
1508 #define SYSKT_POWER_CMD     0x20d
1509 #define   SYSKT_POWER_START (1 << 7)
1510 #define SYSKT_POWER_STATUS  0x20e
1511 #define   SYSKT_POWER_STATUS_OK (1 << 0)
1512 #define SYSKT_BOARD_REV     0x210
1513 #define SYSKT_CHIP_REV      0x211
1514 #define SYSKT_CONF_DATA     0x212
1515 #define   SYSKT_CONF_DATA_1V8   (1 << 2)
1516 #define   SYSKT_CONF_DATA_2V5   (1 << 1)
1517 #define   SYSKT_CONF_DATA_3V3   (1 << 0)
1518 
1519 static int syskt_probe(struct sdhci_pci_chip *chip)
1520 {
1521     if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1522         chip->pdev->class &= ~0x0000FF;
1523         chip->pdev->class |= PCI_SDHCI_IFDMA;
1524     }
1525     return 0;
1526 }
1527 
1528 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1529 {
1530     int tm, ps;
1531 
1532     u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1533     u8  chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1534     dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1535                      "board rev %d.%d, chip rev %d.%d\n",
1536                      board_rev >> 4, board_rev & 0xf,
1537                      chip_rev >> 4,  chip_rev & 0xf);
1538     if (chip_rev >= 0x20)
1539         slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1540 
1541     writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1542     writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1543     udelay(50);
1544     tm = 10;  /* Wait max 1 ms */
1545     do {
1546         ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1547         if (ps & SYSKT_POWER_STATUS_OK)
1548             break;
1549         udelay(100);
1550     } while (--tm);
1551     if (!tm) {
1552         dev_err(&slot->chip->pdev->dev,
1553             "power regulator never stabilized");
1554         writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1555         return -ENODEV;
1556     }
1557 
1558     return 0;
1559 }
1560 
1561 static const struct sdhci_pci_fixes sdhci_syskt = {
1562     .quirks     = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1563     .probe      = syskt_probe,
1564     .probe_slot = syskt_probe_slot,
1565 };
1566 
1567 static int via_probe(struct sdhci_pci_chip *chip)
1568 {
1569     if (chip->pdev->revision == 0x10)
1570         chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1571 
1572     return 0;
1573 }
1574 
1575 static const struct sdhci_pci_fixes sdhci_via = {
1576     .probe      = via_probe,
1577 };
1578 
1579 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1580 {
1581     slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1582     return 0;
1583 }
1584 
1585 static const struct sdhci_pci_fixes sdhci_rtsx = {
1586     .quirks2    = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1587             SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1588             SDHCI_QUIRK2_BROKEN_DDR50,
1589     .probe_slot = rtsx_probe_slot,
1590 };
1591 
1592 /*AMD chipset generation*/
1593 enum amd_chipset_gen {
1594     AMD_CHIPSET_BEFORE_ML,
1595     AMD_CHIPSET_CZ,
1596     AMD_CHIPSET_NL,
1597     AMD_CHIPSET_UNKNOWN,
1598 };
1599 
1600 /* AMD registers */
1601 #define AMD_SD_AUTO_PATTERN     0xB8
1602 #define AMD_MSLEEP_DURATION     4
1603 #define AMD_SD_MISC_CONTROL     0xD0
1604 #define AMD_MAX_TUNE_VALUE      0x0B
1605 #define AMD_AUTO_TUNE_SEL       0x10800
1606 #define AMD_FIFO_PTR            0x30
1607 #define AMD_BIT_MASK            0x1F
1608 
1609 static void amd_tuning_reset(struct sdhci_host *host)
1610 {
1611     unsigned int val;
1612 
1613     val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1614     val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1615     sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1616 
1617     val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1618     val &= ~SDHCI_CTRL_EXEC_TUNING;
1619     sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1620 }
1621 
1622 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1623 {
1624     unsigned int val;
1625 
1626     pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1627     val &= ~AMD_BIT_MASK;
1628     val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1629     pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1630 }
1631 
1632 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1633 {
1634     unsigned int val;
1635 
1636     pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1637     val |= AMD_FIFO_PTR;
1638     pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1639 }
1640 
1641 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode)
1642 {
1643     struct sdhci_pci_slot *slot = sdhci_priv(host);
1644     struct pci_dev *pdev = slot->chip->pdev;
1645     u8 valid_win = 0;
1646     u8 valid_win_max = 0;
1647     u8 valid_win_end = 0;
1648     u8 ctrl, tune_around;
1649 
1650     amd_tuning_reset(host);
1651 
1652     for (tune_around = 0; tune_around < 12; tune_around++) {
1653         amd_config_tuning_phase(pdev, tune_around);
1654 
1655         if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1656             valid_win = 0;
1657             msleep(AMD_MSLEEP_DURATION);
1658             ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1659             sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1660         } else if (++valid_win > valid_win_max) {
1661             valid_win_max = valid_win;
1662             valid_win_end = tune_around;
1663         }
1664     }
1665 
1666     if (!valid_win_max) {
1667         dev_err(&pdev->dev, "no tuning point found\n");
1668         return -EIO;
1669     }
1670 
1671     amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1672 
1673     amd_enable_manual_tuning(pdev);
1674 
1675     host->mmc->retune_period = 0;
1676 
1677     return 0;
1678 }
1679 
1680 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode)
1681 {
1682     struct sdhci_host *host = mmc_priv(mmc);
1683 
1684     /* AMD requires custom HS200 tuning */
1685     if (host->timing == MMC_TIMING_MMC_HS200)
1686         return amd_execute_tuning_hs200(host, opcode);
1687 
1688     /* Otherwise perform standard SDHCI tuning */
1689     return sdhci_execute_tuning(mmc, opcode);
1690 }
1691 
1692 static int amd_probe_slot(struct sdhci_pci_slot *slot)
1693 {
1694     struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
1695 
1696     ops->execute_tuning = amd_execute_tuning;
1697 
1698     return 0;
1699 }
1700 
1701 static int amd_probe(struct sdhci_pci_chip *chip)
1702 {
1703     struct pci_dev  *smbus_dev;
1704     enum amd_chipset_gen gen;
1705 
1706     smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1707             PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1708     if (smbus_dev) {
1709         gen = AMD_CHIPSET_BEFORE_ML;
1710     } else {
1711         smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1712                 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1713         if (smbus_dev) {
1714             if (smbus_dev->revision < 0x51)
1715                 gen = AMD_CHIPSET_CZ;
1716             else
1717                 gen = AMD_CHIPSET_NL;
1718         } else {
1719             gen = AMD_CHIPSET_UNKNOWN;
1720         }
1721     }
1722 
1723     if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1724         chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1725 
1726     return 0;
1727 }
1728 
1729 static u32 sdhci_read_present_state(struct sdhci_host *host)
1730 {
1731     return sdhci_readl(host, SDHCI_PRESENT_STATE);
1732 }
1733 
1734 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
1735 {
1736     struct sdhci_pci_slot *slot = sdhci_priv(host);
1737     struct pci_dev *pdev = slot->chip->pdev;
1738     u32 present_state;
1739 
1740     /*
1741      * SDHC 0x7906 requires a hard reset to clear all internal state.
1742      * Otherwise it can get into a bad state where the DATA lines are always
1743      * read as zeros.
1744      */
1745     if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) {
1746         pci_clear_master(pdev);
1747 
1748         pci_save_state(pdev);
1749 
1750         pci_set_power_state(pdev, PCI_D3cold);
1751         pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc),
1752             pdev->current_state);
1753         pci_set_power_state(pdev, PCI_D0);
1754 
1755         pci_restore_state(pdev);
1756 
1757         /*
1758          * SDHCI_RESET_ALL says the card detect logic should not be
1759          * reset, but since we need to reset the entire controller
1760          * we should wait until the card detect logic has stabilized.
1761          *
1762          * This normally takes about 40ms.
1763          */
1764         readx_poll_timeout(
1765             sdhci_read_present_state,
1766             host,
1767             present_state,
1768             present_state & SDHCI_CD_STABLE,
1769             10000,
1770             100000
1771         );
1772     }
1773 
1774     return sdhci_reset(host, mask);
1775 }
1776 
1777 static const struct sdhci_ops amd_sdhci_pci_ops = {
1778     .set_clock          = sdhci_set_clock,
1779     .enable_dma         = sdhci_pci_enable_dma,
1780     .set_bus_width          = sdhci_set_bus_width,
1781     .reset              = amd_sdhci_reset,
1782     .set_uhs_signaling      = sdhci_set_uhs_signaling,
1783 };
1784 
1785 static const struct sdhci_pci_fixes sdhci_amd = {
1786     .probe      = amd_probe,
1787     .ops        = &amd_sdhci_pci_ops,
1788     .probe_slot = amd_probe_slot,
1789 };
1790 
1791 static const struct pci_device_id pci_ids[] = {
1792     SDHCI_PCI_DEVICE(RICOH, R5C822,  ricoh),
1793     SDHCI_PCI_DEVICE(RICOH, R5C843,  ricoh_mmc),
1794     SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1795     SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1796     SDHCI_PCI_DEVICE(ENE, CB712_SD,   ene_712),
1797     SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1798     SDHCI_PCI_DEVICE(ENE, CB714_SD,   ene_714),
1799     SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1800     SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1801     SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD,  jmicron),
1802     SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1803     SDHCI_PCI_DEVICE(JMICRON, JMB388_SD,  jmicron),
1804     SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1805     SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1806     SDHCI_PCI_DEVICE(VIA, 95D0, via),
1807     SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1808     SDHCI_PCI_DEVICE(INTEL, QRK_SD,    intel_qrk),
1809     SDHCI_PCI_DEVICE(INTEL, MRST_SD0,  intel_mrst_hc0),
1810     SDHCI_PCI_DEVICE(INTEL, MRST_SD1,  intel_mrst_hc1_hc2),
1811     SDHCI_PCI_DEVICE(INTEL, MRST_SD2,  intel_mrst_hc1_hc2),
1812     SDHCI_PCI_DEVICE(INTEL, MFD_SD,    intel_mfd_sd),
1813     SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1814     SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1815     SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1816     SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1817     SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1818     SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1819     SDHCI_PCI_DEVICE(INTEL, BYT_EMMC,  intel_byt_emmc),
1820     SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1821     SDHCI_PCI_DEVICE(INTEL, BYT_SDIO,  intel_byt_sdio),
1822     SDHCI_PCI_DEVICE(INTEL, BYT_SD,    intel_byt_sd),
1823     SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1824     SDHCI_PCI_DEVICE(INTEL, BSW_EMMC,  intel_byt_emmc),
1825     SDHCI_PCI_DEVICE(INTEL, BSW_SDIO,  intel_byt_sdio),
1826     SDHCI_PCI_DEVICE(INTEL, BSW_SD,    intel_byt_sd),
1827     SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1828     SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1829     SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1830     SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1831     SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1832     SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1833     SDHCI_PCI_DEVICE(INTEL, SPT_EMMC,  intel_byt_emmc),
1834     SDHCI_PCI_DEVICE(INTEL, SPT_SDIO,  intel_byt_sdio),
1835     SDHCI_PCI_DEVICE(INTEL, SPT_SD,    intel_byt_sd),
1836     SDHCI_PCI_DEVICE(INTEL, DNV_EMMC,  intel_byt_emmc),
1837     SDHCI_PCI_DEVICE(INTEL, CDF_EMMC,  intel_glk_emmc),
1838     SDHCI_PCI_DEVICE(INTEL, BXT_EMMC,  intel_byt_emmc),
1839     SDHCI_PCI_DEVICE(INTEL, BXT_SDIO,  intel_byt_sdio),
1840     SDHCI_PCI_DEVICE(INTEL, BXT_SD,    intel_byt_sd),
1841     SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1842     SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1843     SDHCI_PCI_DEVICE(INTEL, BXTM_SD,   intel_byt_sd),
1844     SDHCI_PCI_DEVICE(INTEL, APL_EMMC,  intel_byt_emmc),
1845     SDHCI_PCI_DEVICE(INTEL, APL_SDIO,  intel_byt_sdio),
1846     SDHCI_PCI_DEVICE(INTEL, APL_SD,    intel_byt_sd),
1847     SDHCI_PCI_DEVICE(INTEL, GLK_EMMC,  intel_glk_emmc),
1848     SDHCI_PCI_DEVICE(INTEL, GLK_SDIO,  intel_byt_sdio),
1849     SDHCI_PCI_DEVICE(INTEL, GLK_SD,    intel_byt_sd),
1850     SDHCI_PCI_DEVICE(INTEL, CNP_EMMC,  intel_glk_emmc),
1851     SDHCI_PCI_DEVICE(INTEL, CNP_SD,    intel_byt_sd),
1852     SDHCI_PCI_DEVICE(INTEL, CNPH_SD,   intel_byt_sd),
1853     SDHCI_PCI_DEVICE(INTEL, ICP_EMMC,  intel_glk_emmc),
1854     SDHCI_PCI_DEVICE(INTEL, ICP_SD,    intel_byt_sd),
1855     SDHCI_PCI_DEVICE(INTEL, EHL_EMMC,  intel_glk_emmc),
1856     SDHCI_PCI_DEVICE(INTEL, EHL_SD,    intel_byt_sd),
1857     SDHCI_PCI_DEVICE(INTEL, CML_EMMC,  intel_glk_emmc),
1858     SDHCI_PCI_DEVICE(INTEL, CML_SD,    intel_byt_sd),
1859     SDHCI_PCI_DEVICE(INTEL, CMLH_SD,   intel_byt_sd),
1860     SDHCI_PCI_DEVICE(INTEL, JSL_EMMC,  intel_glk_emmc),
1861     SDHCI_PCI_DEVICE(INTEL, JSL_SD,    intel_byt_sd),
1862     SDHCI_PCI_DEVICE(INTEL, LKF_EMMC,  intel_glk_emmc),
1863     SDHCI_PCI_DEVICE(INTEL, LKF_SD,    intel_byt_sd),
1864     SDHCI_PCI_DEVICE(INTEL, ADL_EMMC,  intel_glk_emmc),
1865     SDHCI_PCI_DEVICE(O2, 8120,     o2),
1866     SDHCI_PCI_DEVICE(O2, 8220,     o2),
1867     SDHCI_PCI_DEVICE(O2, 8221,     o2),
1868     SDHCI_PCI_DEVICE(O2, 8320,     o2),
1869     SDHCI_PCI_DEVICE(O2, 8321,     o2),
1870     SDHCI_PCI_DEVICE(O2, FUJIN2,   o2),
1871     SDHCI_PCI_DEVICE(O2, SDS0,     o2),
1872     SDHCI_PCI_DEVICE(O2, SDS1,     o2),
1873     SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1874     SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1875     SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
1876     SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
1877     SDHCI_PCI_DEVICE(GLI, 9750, gl9750),
1878     SDHCI_PCI_DEVICE(GLI, 9755, gl9755),
1879     SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e),
1880     SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1881     /* Generic SD host controller */
1882     {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1883     { /* end: all zeroes */ },
1884 };
1885 
1886 MODULE_DEVICE_TABLE(pci, pci_ids);
1887 
1888 /*****************************************************************************\
1889  *                                                                           *
1890  * SDHCI core callbacks                                                      *
1891  *                                                                           *
1892 \*****************************************************************************/
1893 
1894 int sdhci_pci_enable_dma(struct sdhci_host *host)
1895 {
1896     struct sdhci_pci_slot *slot;
1897     struct pci_dev *pdev;
1898 
1899     slot = sdhci_priv(host);
1900     pdev = slot->chip->pdev;
1901 
1902     if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1903         ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1904         (host->flags & SDHCI_USE_SDMA)) {
1905         dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1906             "doesn't fully claim to support it.\n");
1907     }
1908 
1909     pci_set_master(pdev);
1910 
1911     return 0;
1912 }
1913 
1914 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1915 {
1916     struct sdhci_pci_slot *slot = sdhci_priv(host);
1917 
1918     if (slot->hw_reset)
1919         slot->hw_reset(host);
1920 }
1921 
1922 static const struct sdhci_ops sdhci_pci_ops = {
1923     .set_clock  = sdhci_set_clock,
1924     .enable_dma = sdhci_pci_enable_dma,
1925     .set_bus_width  = sdhci_set_bus_width,
1926     .reset      = sdhci_reset,
1927     .set_uhs_signaling = sdhci_set_uhs_signaling,
1928     .hw_reset       = sdhci_pci_hw_reset,
1929 };
1930 
1931 /*****************************************************************************\
1932  *                                                                           *
1933  * Suspend/resume                                                            *
1934  *                                                                           *
1935 \*****************************************************************************/
1936 
1937 #ifdef CONFIG_PM_SLEEP
1938 static int sdhci_pci_suspend(struct device *dev)
1939 {
1940     struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
1941 
1942     if (!chip)
1943         return 0;
1944 
1945     if (chip->fixes && chip->fixes->suspend)
1946         return chip->fixes->suspend(chip);
1947 
1948     return sdhci_pci_suspend_host(chip);
1949 }
1950 
1951 static int sdhci_pci_resume(struct device *dev)
1952 {
1953     struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
1954 
1955     if (!chip)
1956         return 0;
1957 
1958     if (chip->fixes && chip->fixes->resume)
1959         return chip->fixes->resume(chip);
1960 
1961     return sdhci_pci_resume_host(chip);
1962 }
1963 #endif
1964 
1965 #ifdef CONFIG_PM
1966 static int sdhci_pci_runtime_suspend(struct device *dev)
1967 {
1968     struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
1969 
1970     if (!chip)
1971         return 0;
1972 
1973     if (chip->fixes && chip->fixes->runtime_suspend)
1974         return chip->fixes->runtime_suspend(chip);
1975 
1976     return sdhci_pci_runtime_suspend_host(chip);
1977 }
1978 
1979 static int sdhci_pci_runtime_resume(struct device *dev)
1980 {
1981     struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
1982 
1983     if (!chip)
1984         return 0;
1985 
1986     if (chip->fixes && chip->fixes->runtime_resume)
1987         return chip->fixes->runtime_resume(chip);
1988 
1989     return sdhci_pci_runtime_resume_host(chip);
1990 }
1991 #endif
1992 
1993 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1994     SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1995     SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1996             sdhci_pci_runtime_resume, NULL)
1997 };
1998 
1999 /*****************************************************************************\
2000  *                                                                           *
2001  * Device probing/removal                                                    *
2002  *                                                                           *
2003 \*****************************************************************************/
2004 
2005 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
2006     struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
2007     int slotno)
2008 {
2009     struct sdhci_pci_slot *slot;
2010     struct sdhci_host *host;
2011     int ret, bar = first_bar + slotno;
2012     size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
2013 
2014     if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
2015         dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
2016         return ERR_PTR(-ENODEV);
2017     }
2018 
2019     if (pci_resource_len(pdev, bar) < 0x100) {
2020         dev_err(&pdev->dev, "Invalid iomem size. You may "
2021             "experience problems.\n");
2022     }
2023 
2024     if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
2025         dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
2026         return ERR_PTR(-ENODEV);
2027     }
2028 
2029     if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
2030         dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
2031         return ERR_PTR(-ENODEV);
2032     }
2033 
2034     host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
2035     if (IS_ERR(host)) {
2036         dev_err(&pdev->dev, "cannot allocate host\n");
2037         return ERR_CAST(host);
2038     }
2039 
2040     slot = sdhci_priv(host);
2041 
2042     slot->chip = chip;
2043     slot->host = host;
2044     slot->cd_idx = -1;
2045 
2046     host->hw_name = "PCI";
2047     host->ops = chip->fixes && chip->fixes->ops ?
2048             chip->fixes->ops :
2049             &sdhci_pci_ops;
2050     host->quirks = chip->quirks;
2051     host->quirks2 = chip->quirks2;
2052 
2053     host->irq = pdev->irq;
2054 
2055     ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
2056     if (ret) {
2057         dev_err(&pdev->dev, "cannot request region\n");
2058         goto cleanup;
2059     }
2060 
2061     host->ioaddr = pcim_iomap_table(pdev)[bar];
2062 
2063     if (chip->fixes && chip->fixes->probe_slot) {
2064         ret = chip->fixes->probe_slot(slot);
2065         if (ret)
2066             goto cleanup;
2067     }
2068 
2069     host->mmc->pm_caps = MMC_PM_KEEP_POWER;
2070     host->mmc->slotno = slotno;
2071     host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2072 
2073     if (device_can_wakeup(&pdev->dev))
2074         host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
2075 
2076     if (host->mmc->caps & MMC_CAP_CD_WAKE)
2077         device_init_wakeup(&pdev->dev, true);
2078 
2079     if (slot->cd_idx >= 0) {
2080         ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx,
2081                        slot->cd_override_level, 0);
2082         if (ret && ret != -EPROBE_DEFER)
2083             ret = mmc_gpiod_request_cd(host->mmc, NULL,
2084                            slot->cd_idx,
2085                            slot->cd_override_level,
2086                            0);
2087         if (ret == -EPROBE_DEFER)
2088             goto remove;
2089 
2090         if (ret) {
2091             dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
2092             slot->cd_idx = -1;
2093         }
2094     }
2095 
2096     if (chip->fixes && chip->fixes->add_host)
2097         ret = chip->fixes->add_host(slot);
2098     else
2099         ret = sdhci_add_host(host);
2100     if (ret)
2101         goto remove;
2102 
2103     /*
2104      * Check if the chip needs a separate GPIO for card detect to wake up
2105      * from runtime suspend.  If it is not there, don't allow runtime PM.
2106      */
2107     if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && slot->cd_idx < 0)
2108         chip->allow_runtime_pm = false;
2109 
2110     return slot;
2111 
2112 remove:
2113     if (chip->fixes && chip->fixes->remove_slot)
2114         chip->fixes->remove_slot(slot, 0);
2115 
2116 cleanup:
2117     sdhci_free_host(host);
2118 
2119     return ERR_PTR(ret);
2120 }
2121 
2122 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
2123 {
2124     int dead;
2125     u32 scratch;
2126 
2127     dead = 0;
2128     scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
2129     if (scratch == (u32)-1)
2130         dead = 1;
2131 
2132     sdhci_remove_host(slot->host, dead);
2133 
2134     if (slot->chip->fixes && slot->chip->fixes->remove_slot)
2135         slot->chip->fixes->remove_slot(slot, dead);
2136 
2137     sdhci_free_host(slot->host);
2138 }
2139 
2140 static void sdhci_pci_runtime_pm_allow(struct device *dev)
2141 {
2142     pm_suspend_ignore_children(dev, 1);
2143     pm_runtime_set_autosuspend_delay(dev, 50);
2144     pm_runtime_use_autosuspend(dev);
2145     pm_runtime_allow(dev);
2146     /* Stay active until mmc core scans for a card */
2147     pm_runtime_put_noidle(dev);
2148 }
2149 
2150 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
2151 {
2152     pm_runtime_forbid(dev);
2153     pm_runtime_get_noresume(dev);
2154 }
2155 
2156 static int sdhci_pci_probe(struct pci_dev *pdev,
2157                      const struct pci_device_id *ent)
2158 {
2159     struct sdhci_pci_chip *chip;
2160     struct sdhci_pci_slot *slot;
2161 
2162     u8 slots, first_bar;
2163     int ret, i;
2164 
2165     BUG_ON(pdev == NULL);
2166     BUG_ON(ent == NULL);
2167 
2168     dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
2169          (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
2170 
2171     ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
2172     if (ret)
2173         return ret;
2174 
2175     slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
2176     dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
2177 
2178     BUG_ON(slots > MAX_SLOTS);
2179 
2180     ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
2181     if (ret)
2182         return ret;
2183 
2184     first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
2185 
2186     if (first_bar > 5) {
2187         dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
2188         return -ENODEV;
2189     }
2190 
2191     ret = pcim_enable_device(pdev);
2192     if (ret)
2193         return ret;
2194 
2195     chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
2196     if (!chip)
2197         return -ENOMEM;
2198 
2199     chip->pdev = pdev;
2200     chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
2201     if (chip->fixes) {
2202         chip->quirks = chip->fixes->quirks;
2203         chip->quirks2 = chip->fixes->quirks2;
2204         chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
2205     }
2206     chip->num_slots = slots;
2207     chip->pm_retune = true;
2208     chip->rpm_retune = true;
2209 
2210     pci_set_drvdata(pdev, chip);
2211 
2212     if (chip->fixes && chip->fixes->probe) {
2213         ret = chip->fixes->probe(chip);
2214         if (ret)
2215             return ret;
2216     }
2217 
2218     slots = chip->num_slots;    /* Quirk may have changed this */
2219 
2220     for (i = 0; i < slots; i++) {
2221         slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
2222         if (IS_ERR(slot)) {
2223             for (i--; i >= 0; i--)
2224                 sdhci_pci_remove_slot(chip->slots[i]);
2225             return PTR_ERR(slot);
2226         }
2227 
2228         chip->slots[i] = slot;
2229     }
2230 
2231     if (chip->allow_runtime_pm)
2232         sdhci_pci_runtime_pm_allow(&pdev->dev);
2233 
2234     return 0;
2235 }
2236 
2237 static void sdhci_pci_remove(struct pci_dev *pdev)
2238 {
2239     int i;
2240     struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
2241 
2242     if (chip->allow_runtime_pm)
2243         sdhci_pci_runtime_pm_forbid(&pdev->dev);
2244 
2245     for (i = 0; i < chip->num_slots; i++)
2246         sdhci_pci_remove_slot(chip->slots[i]);
2247 }
2248 
2249 static struct pci_driver sdhci_driver = {
2250     .name =     "sdhci-pci",
2251     .id_table = pci_ids,
2252     .probe =    sdhci_pci_probe,
2253     .remove =   sdhci_pci_remove,
2254     .driver =   {
2255         .pm =   &sdhci_pci_pm_ops
2256     },
2257 };
2258 
2259 module_pci_driver(sdhci_driver);
2260 
2261 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2262 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
2263 MODULE_LICENSE("GPL");
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