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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /**
0003  * SDHCI Controller driver for TI's OMAP SoCs
0004  *
0005  * Copyright (C) 2017 Texas Instruments
0006  * Author: Kishon Vijay Abraham I <kishon@ti.com>
0007  */
0008 
0009 #include <linux/delay.h>
0010 #include <linux/mmc/mmc.h>
0011 #include <linux/mmc/slot-gpio.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/of_device.h>
0015 #include <linux/of_irq.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/pm_wakeirq.h>
0019 #include <linux/regulator/consumer.h>
0020 #include <linux/pinctrl/consumer.h>
0021 #include <linux/sys_soc.h>
0022 #include <linux/thermal.h>
0023 
0024 #include "sdhci-pltfm.h"
0025 
0026 /*
0027  * Note that the register offsets used here are from omap_regs
0028  * base which is 0x100 for omap4 and later, and 0 for omap3 and
0029  * earlier.
0030  */
0031 #define SDHCI_OMAP_SYSCONFIG    0x10
0032 
0033 #define SDHCI_OMAP_CON      0x2c
0034 #define CON_DW8         BIT(5)
0035 #define CON_DMA_MASTER      BIT(20)
0036 #define CON_DDR         BIT(19)
0037 #define CON_CLKEXTFREE      BIT(16)
0038 #define CON_PADEN       BIT(15)
0039 #define CON_CTPL        BIT(11)
0040 #define CON_INIT        BIT(1)
0041 #define CON_OD          BIT(0)
0042 
0043 #define SDHCI_OMAP_DLL      0x34
0044 #define DLL_SWT         BIT(20)
0045 #define DLL_FORCE_SR_C_SHIFT    13
0046 #define DLL_FORCE_SR_C_MASK (0x7f << DLL_FORCE_SR_C_SHIFT)
0047 #define DLL_FORCE_VALUE     BIT(12)
0048 #define DLL_CALIB       BIT(1)
0049 
0050 #define SDHCI_OMAP_CMD      0x10c
0051 
0052 #define SDHCI_OMAP_PSTATE   0x124
0053 #define PSTATE_DLEV_DAT0    BIT(20)
0054 #define PSTATE_DATI     BIT(1)
0055 
0056 #define SDHCI_OMAP_HCTL     0x128
0057 #define HCTL_SDBP       BIT(8)
0058 #define HCTL_SDVS_SHIFT     9
0059 #define HCTL_SDVS_MASK      (0x7 << HCTL_SDVS_SHIFT)
0060 #define HCTL_SDVS_33        (0x7 << HCTL_SDVS_SHIFT)
0061 #define HCTL_SDVS_30        (0x6 << HCTL_SDVS_SHIFT)
0062 #define HCTL_SDVS_18        (0x5 << HCTL_SDVS_SHIFT)
0063 
0064 #define SDHCI_OMAP_SYSCTL   0x12c
0065 #define SYSCTL_CEN      BIT(2)
0066 #define SYSCTL_CLKD_SHIFT   6
0067 #define SYSCTL_CLKD_MASK    0x3ff
0068 
0069 #define SDHCI_OMAP_STAT     0x130
0070 
0071 #define SDHCI_OMAP_IE       0x134
0072 #define INT_CC_EN       BIT(0)
0073 
0074 #define SDHCI_OMAP_ISE      0x138
0075 
0076 #define SDHCI_OMAP_AC12     0x13c
0077 #define AC12_V1V8_SIGEN     BIT(19)
0078 #define AC12_SCLK_SEL       BIT(23)
0079 
0080 #define SDHCI_OMAP_CAPA     0x140
0081 #define CAPA_VS33       BIT(24)
0082 #define CAPA_VS30       BIT(25)
0083 #define CAPA_VS18       BIT(26)
0084 
0085 #define SDHCI_OMAP_CAPA2    0x144
0086 #define CAPA2_TSDR50        BIT(13)
0087 
0088 #define SDHCI_OMAP_TIMEOUT  1       /* 1 msec */
0089 
0090 #define SYSCTL_CLKD_MAX     0x3FF
0091 
0092 #define IOV_1V8         1800000     /* 180000 uV */
0093 #define IOV_3V0         3000000     /* 300000 uV */
0094 #define IOV_3V3         3300000     /* 330000 uV */
0095 
0096 #define MAX_PHASE_DELAY     0x7C
0097 
0098 /* sdhci-omap controller flags */
0099 #define SDHCI_OMAP_REQUIRE_IODELAY  BIT(0)
0100 #define SDHCI_OMAP_SPECIAL_RESET    BIT(1)
0101 
0102 struct sdhci_omap_data {
0103     int omap_offset;    /* Offset for omap regs from base */
0104     u32 offset;     /* Offset for SDHCI regs from base */
0105     u8 flags;
0106 };
0107 
0108 struct sdhci_omap_host {
0109     char            *version;
0110     void __iomem        *base;
0111     struct device       *dev;
0112     struct  regulator   *pbias;
0113     bool            pbias_enabled;
0114     struct sdhci_host   *host;
0115     u8          bus_mode;
0116     u8          power_mode;
0117     u8          timing;
0118     u8          flags;
0119 
0120     struct pinctrl      *pinctrl;
0121     struct pinctrl_state    **pinctrl_state;
0122     int         wakeirq;
0123     bool            is_tuning;
0124 
0125     /* Offset for omap specific registers from base */
0126     int         omap_offset;
0127 
0128     /* Omap specific context save */
0129     u32         con;
0130     u32         hctl;
0131     u32         sysctl;
0132     u32         capa;
0133     u32         ie;
0134     u32         ise;
0135 };
0136 
0137 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
0138 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host);
0139 
0140 static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
0141                    unsigned int offset)
0142 {
0143     return readl(host->base + host->omap_offset + offset);
0144 }
0145 
0146 static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
0147                      unsigned int offset, u32 data)
0148 {
0149     writel(data, host->base + host->omap_offset + offset);
0150 }
0151 
0152 static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
0153                 bool power_on, unsigned int iov)
0154 {
0155     int ret;
0156     struct device *dev = omap_host->dev;
0157 
0158     if (IS_ERR(omap_host->pbias))
0159         return 0;
0160 
0161     if (power_on) {
0162         ret = regulator_set_voltage(omap_host->pbias, iov, iov);
0163         if (ret) {
0164             dev_err(dev, "pbias set voltage failed\n");
0165             return ret;
0166         }
0167 
0168         if (omap_host->pbias_enabled)
0169             return 0;
0170 
0171         ret = regulator_enable(omap_host->pbias);
0172         if (ret) {
0173             dev_err(dev, "pbias reg enable fail\n");
0174             return ret;
0175         }
0176 
0177         omap_host->pbias_enabled = true;
0178     } else {
0179         if (!omap_host->pbias_enabled)
0180             return 0;
0181 
0182         ret = regulator_disable(omap_host->pbias);
0183         if (ret) {
0184             dev_err(dev, "pbias reg disable fail\n");
0185             return ret;
0186         }
0187         omap_host->pbias_enabled = false;
0188     }
0189 
0190     return 0;
0191 }
0192 
0193 static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
0194                  unsigned int iov_pbias)
0195 {
0196     int ret;
0197     struct sdhci_host *host = omap_host->host;
0198     struct mmc_host *mmc = host->mmc;
0199 
0200     ret = sdhci_omap_set_pbias(omap_host, false, 0);
0201     if (ret)
0202         return ret;
0203 
0204     if (!IS_ERR(mmc->supply.vqmmc)) {
0205         /* Pick the right voltage to allow 3.0V for 3.3V nominal PBIAS */
0206         ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios);
0207         if (ret < 0) {
0208             dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
0209             return ret;
0210         }
0211     }
0212 
0213     ret = sdhci_omap_set_pbias(omap_host, true, iov_pbias);
0214     if (ret)
0215         return ret;
0216 
0217     return 0;
0218 }
0219 
0220 static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
0221                       unsigned char signal_voltage)
0222 {
0223     u32 reg, capa;
0224     ktime_t timeout;
0225 
0226     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
0227     reg &= ~HCTL_SDVS_MASK;
0228 
0229     switch (signal_voltage) {
0230     case MMC_SIGNAL_VOLTAGE_330:
0231         capa = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
0232         if (capa & CAPA_VS33)
0233             reg |= HCTL_SDVS_33;
0234         else if (capa & CAPA_VS30)
0235             reg |= HCTL_SDVS_30;
0236         else
0237             dev_warn(omap_host->dev, "misconfigured CAPA: %08x\n",
0238                  capa);
0239         break;
0240     case MMC_SIGNAL_VOLTAGE_180:
0241     default:
0242         reg |= HCTL_SDVS_18;
0243         break;
0244     }
0245 
0246     sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
0247 
0248     reg |= HCTL_SDBP;
0249     sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
0250 
0251     /* wait 1ms */
0252     timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
0253     while (1) {
0254         bool timedout = ktime_after(ktime_get(), timeout);
0255 
0256         if (sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)
0257             break;
0258         if (WARN_ON(timedout))
0259             return;
0260         usleep_range(5, 10);
0261     }
0262 }
0263 
0264 static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable)
0265 {
0266     struct sdhci_host *host = mmc_priv(mmc);
0267     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0268     struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
0269     u32 reg;
0270 
0271     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
0272     if (enable)
0273         reg |= (CON_CTPL | CON_CLKEXTFREE);
0274     else
0275         reg &= ~(CON_CTPL | CON_CLKEXTFREE);
0276     sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
0277 
0278     sdhci_enable_sdio_irq(mmc, enable);
0279 }
0280 
0281 static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
0282                       int count)
0283 {
0284     int i;
0285     u32 reg;
0286 
0287     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
0288     reg |= DLL_FORCE_VALUE;
0289     reg &= ~DLL_FORCE_SR_C_MASK;
0290     reg |= (count << DLL_FORCE_SR_C_SHIFT);
0291     sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
0292 
0293     reg |= DLL_CALIB;
0294     sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
0295     for (i = 0; i < 1000; i++) {
0296         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
0297         if (reg & DLL_CALIB)
0298             break;
0299     }
0300     reg &= ~DLL_CALIB;
0301     sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
0302 }
0303 
0304 static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
0305 {
0306     u32 reg;
0307 
0308     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
0309     reg &= ~AC12_SCLK_SEL;
0310     sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
0311 
0312     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
0313     reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
0314     sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
0315 }
0316 
0317 static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
0318 {
0319     struct sdhci_host *host = mmc_priv(mmc);
0320     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0321     struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
0322     struct thermal_zone_device *thermal_dev;
0323     struct device *dev = omap_host->dev;
0324     struct mmc_ios *ios = &mmc->ios;
0325     u32 start_window = 0, max_window = 0;
0326     bool single_point_failure = false;
0327     bool dcrc_was_enabled = false;
0328     u8 cur_match, prev_match = 0;
0329     u32 length = 0, max_len = 0;
0330     u32 phase_delay = 0;
0331     int temperature;
0332     int ret = 0;
0333     u32 reg;
0334     int i;
0335 
0336     /* clock tuning is not needed for upto 52MHz */
0337     if (ios->clock <= 52000000)
0338         return 0;
0339 
0340     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
0341     if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
0342         return 0;
0343 
0344     thermal_dev = thermal_zone_get_zone_by_name("cpu_thermal");
0345     if (IS_ERR(thermal_dev)) {
0346         dev_err(dev, "Unable to get thermal zone for tuning\n");
0347         return PTR_ERR(thermal_dev);
0348     }
0349 
0350     ret = thermal_zone_get_temp(thermal_dev, &temperature);
0351     if (ret)
0352         return ret;
0353 
0354     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
0355     reg |= DLL_SWT;
0356     sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
0357 
0358     /*
0359      * OMAP5/DRA74X/DRA72x Errata i802:
0360      * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
0361      * during the tuning procedure. So disable it during the
0362      * tuning procedure.
0363      */
0364     if (host->ier & SDHCI_INT_DATA_CRC) {
0365         host->ier &= ~SDHCI_INT_DATA_CRC;
0366         dcrc_was_enabled = true;
0367     }
0368 
0369     omap_host->is_tuning = true;
0370 
0371     /*
0372      * Stage 1: Search for a maximum pass window ignoring any
0373      * any single point failures. If the tuning value ends up
0374      * near it, move away from it in stage 2 below
0375      */
0376     while (phase_delay <= MAX_PHASE_DELAY) {
0377         sdhci_omap_set_dll(omap_host, phase_delay);
0378 
0379         cur_match = !mmc_send_tuning(mmc, opcode, NULL);
0380         if (cur_match) {
0381             if (prev_match) {
0382                 length++;
0383             } else if (single_point_failure) {
0384                 /* ignore single point failure */
0385                 length++;
0386             } else {
0387                 start_window = phase_delay;
0388                 length = 1;
0389             }
0390         } else {
0391             single_point_failure = prev_match;
0392         }
0393 
0394         if (length > max_len) {
0395             max_window = start_window;
0396             max_len = length;
0397         }
0398 
0399         prev_match = cur_match;
0400         phase_delay += 4;
0401     }
0402 
0403     if (!max_len) {
0404         dev_err(dev, "Unable to find match\n");
0405         ret = -EIO;
0406         goto tuning_error;
0407     }
0408 
0409     /*
0410      * Assign tuning value as a ratio of maximum pass window based
0411      * on temperature
0412      */
0413     if (temperature < -20000)
0414         phase_delay = min(max_window + 4 * (max_len - 1) - 24,
0415                   max_window +
0416                   DIV_ROUND_UP(13 * max_len, 16) * 4);
0417     else if (temperature < 20000)
0418         phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
0419     else if (temperature < 40000)
0420         phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
0421     else if (temperature < 70000)
0422         phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
0423     else if (temperature < 90000)
0424         phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
0425     else if (temperature < 120000)
0426         phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
0427     else
0428         phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
0429 
0430     /*
0431      * Stage 2: Search for a single point failure near the chosen tuning
0432      * value in two steps. First in the +3 to +10 range and then in the
0433      * +2 to -10 range. If found, move away from it in the appropriate
0434      * direction by the appropriate amount depending on the temperature.
0435      */
0436     for (i = 3; i <= 10; i++) {
0437         sdhci_omap_set_dll(omap_host, phase_delay + i);
0438 
0439         if (mmc_send_tuning(mmc, opcode, NULL)) {
0440             if (temperature < 10000)
0441                 phase_delay += i + 6;
0442             else if (temperature < 20000)
0443                 phase_delay += i - 12;
0444             else if (temperature < 70000)
0445                 phase_delay += i - 8;
0446             else
0447                 phase_delay += i - 6;
0448 
0449             goto single_failure_found;
0450         }
0451     }
0452 
0453     for (i = 2; i >= -10; i--) {
0454         sdhci_omap_set_dll(omap_host, phase_delay + i);
0455 
0456         if (mmc_send_tuning(mmc, opcode, NULL)) {
0457             if (temperature < 10000)
0458                 phase_delay += i + 12;
0459             else if (temperature < 20000)
0460                 phase_delay += i + 8;
0461             else if (temperature < 70000)
0462                 phase_delay += i + 8;
0463             else if (temperature < 90000)
0464                 phase_delay += i + 10;
0465             else
0466                 phase_delay += i + 12;
0467 
0468             goto single_failure_found;
0469         }
0470     }
0471 
0472 single_failure_found:
0473     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
0474     if (!(reg & AC12_SCLK_SEL)) {
0475         ret = -EIO;
0476         goto tuning_error;
0477     }
0478 
0479     sdhci_omap_set_dll(omap_host, phase_delay);
0480 
0481     omap_host->is_tuning = false;
0482 
0483     goto ret;
0484 
0485 tuning_error:
0486     omap_host->is_tuning = false;
0487     dev_err(dev, "Tuning failed\n");
0488     sdhci_omap_disable_tuning(omap_host);
0489 
0490 ret:
0491     sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
0492     /* Reenable forbidden interrupt */
0493     if (dcrc_was_enabled)
0494         host->ier |= SDHCI_INT_DATA_CRC;
0495     sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
0496     sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
0497     return ret;
0498 }
0499 
0500 static int sdhci_omap_card_busy(struct mmc_host *mmc)
0501 {
0502     u32 reg, ac12;
0503     int ret = false;
0504     struct sdhci_host *host = mmc_priv(mmc);
0505     struct sdhci_pltfm_host *pltfm_host;
0506     struct sdhci_omap_host *omap_host;
0507     u32 ier = host->ier;
0508 
0509     pltfm_host = sdhci_priv(host);
0510     omap_host = sdhci_pltfm_priv(pltfm_host);
0511 
0512     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
0513     ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
0514     reg &= ~CON_CLKEXTFREE;
0515     if (ac12 & AC12_V1V8_SIGEN)
0516         reg |= CON_CLKEXTFREE;
0517     reg |= CON_PADEN;
0518     sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
0519 
0520     disable_irq(host->irq);
0521     ier |= SDHCI_INT_CARD_INT;
0522     sdhci_writel(host, ier, SDHCI_INT_ENABLE);
0523     sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
0524 
0525     /*
0526      * Delay is required for PSTATE to correctly reflect
0527      * DLEV/CLEV values after PADEN is set.
0528      */
0529     usleep_range(50, 100);
0530     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
0531     if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0))
0532         ret = true;
0533 
0534     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
0535     reg &= ~(CON_CLKEXTFREE | CON_PADEN);
0536     sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
0537 
0538     sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
0539     sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
0540     enable_irq(host->irq);
0541 
0542     return ret;
0543 }
0544 
0545 static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
0546                           struct mmc_ios *ios)
0547 {
0548     u32 reg;
0549     int ret;
0550     unsigned int iov;
0551     struct sdhci_host *host = mmc_priv(mmc);
0552     struct sdhci_pltfm_host *pltfm_host;
0553     struct sdhci_omap_host *omap_host;
0554     struct device *dev;
0555 
0556     pltfm_host = sdhci_priv(host);
0557     omap_host = sdhci_pltfm_priv(pltfm_host);
0558     dev = omap_host->dev;
0559 
0560     if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
0561         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
0562         if (!(reg & (CAPA_VS30 | CAPA_VS33)))
0563             return -EOPNOTSUPP;
0564 
0565         if (reg & CAPA_VS30)
0566             iov = IOV_3V0;
0567         else
0568             iov = IOV_3V3;
0569 
0570         sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
0571 
0572         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
0573         reg &= ~AC12_V1V8_SIGEN;
0574         sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
0575 
0576     } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
0577         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
0578         if (!(reg & CAPA_VS18))
0579             return -EOPNOTSUPP;
0580 
0581         iov = IOV_1V8;
0582 
0583         sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
0584 
0585         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
0586         reg |= AC12_V1V8_SIGEN;
0587         sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
0588     } else {
0589         return -EOPNOTSUPP;
0590     }
0591 
0592     ret = sdhci_omap_enable_iov(omap_host, iov);
0593     if (ret) {
0594         dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
0595         return ret;
0596     }
0597 
0598     dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
0599     return 0;
0600 }
0601 
0602 static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
0603 {
0604     int ret;
0605     struct pinctrl_state *pinctrl_state;
0606     struct device *dev = omap_host->dev;
0607 
0608     if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
0609         return;
0610 
0611     if (omap_host->timing == timing)
0612         return;
0613 
0614     sdhci_omap_stop_clock(omap_host);
0615 
0616     pinctrl_state = omap_host->pinctrl_state[timing];
0617     ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
0618     if (ret) {
0619         dev_err(dev, "failed to select pinctrl state\n");
0620         return;
0621     }
0622 
0623     sdhci_omap_start_clock(omap_host);
0624     omap_host->timing = timing;
0625 }
0626 
0627 static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
0628                       u8 power_mode)
0629 {
0630     if (omap_host->bus_mode == MMC_POWER_OFF)
0631         sdhci_omap_disable_tuning(omap_host);
0632     omap_host->power_mode = power_mode;
0633 }
0634 
0635 static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
0636                     unsigned int mode)
0637 {
0638     u32 reg;
0639 
0640     if (omap_host->bus_mode == mode)
0641         return;
0642 
0643     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
0644     if (mode == MMC_BUSMODE_OPENDRAIN)
0645         reg |= CON_OD;
0646     else
0647         reg &= ~CON_OD;
0648     sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
0649 
0650     omap_host->bus_mode = mode;
0651 }
0652 
0653 static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
0654 {
0655     struct sdhci_host *host = mmc_priv(mmc);
0656     struct sdhci_pltfm_host *pltfm_host;
0657     struct sdhci_omap_host *omap_host;
0658 
0659     pltfm_host = sdhci_priv(host);
0660     omap_host = sdhci_pltfm_priv(pltfm_host);
0661 
0662     sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
0663     sdhci_omap_set_timing(omap_host, ios->timing);
0664     sdhci_set_ios(mmc, ios);
0665     sdhci_omap_set_power_mode(omap_host, ios->power_mode);
0666 }
0667 
0668 static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
0669                    unsigned int clock)
0670 {
0671     u16 dsor;
0672 
0673     dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
0674     if (dsor > SYSCTL_CLKD_MAX)
0675         dsor = SYSCTL_CLKD_MAX;
0676 
0677     return dsor;
0678 }
0679 
0680 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
0681 {
0682     u32 reg;
0683 
0684     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
0685     reg |= SYSCTL_CEN;
0686     sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
0687 }
0688 
0689 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
0690 {
0691     u32 reg;
0692 
0693     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
0694     reg &= ~SYSCTL_CEN;
0695     sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
0696 }
0697 
0698 static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
0699 {
0700     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0701     struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
0702     unsigned long clkdiv;
0703 
0704     sdhci_omap_stop_clock(omap_host);
0705 
0706     if (!clock)
0707         return;
0708 
0709     clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
0710     clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
0711     sdhci_enable_clk(host, clkdiv);
0712 
0713     sdhci_omap_start_clock(omap_host);
0714 }
0715 
0716 static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
0717               unsigned short vdd)
0718 {
0719     struct mmc_host *mmc = host->mmc;
0720 
0721     if (!IS_ERR(mmc->supply.vmmc))
0722         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
0723 }
0724 
0725 /*
0726  * MMCHS_HL_HWINFO has the MADMA_EN bit set if the controller instance
0727  * is connected to L3 interconnect and is bus master capable. Note that
0728  * the MMCHS_HL_HWINFO register is in the module registers before the
0729  * omap registers and sdhci registers. The offset can vary for omap
0730  * registers depending on the SoC. Do not use sdhci_omap_readl() here.
0731  */
0732 static bool sdhci_omap_has_adma(struct sdhci_omap_host *omap_host, int offset)
0733 {
0734     /* MMCHS_HL_HWINFO register is only available on omap4 and later */
0735     if (offset < 0x200)
0736         return false;
0737 
0738     return readl(omap_host->base + 4) & 1;
0739 }
0740 
0741 static int sdhci_omap_enable_dma(struct sdhci_host *host)
0742 {
0743     u32 reg;
0744     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0745     struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
0746 
0747     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
0748     reg &= ~CON_DMA_MASTER;
0749     /* Switch to DMA slave mode when using external DMA */
0750     if (!host->use_external_dma)
0751         reg |= CON_DMA_MASTER;
0752 
0753     sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
0754 
0755     return 0;
0756 }
0757 
0758 static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
0759 {
0760     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0761 
0762     return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
0763 }
0764 
0765 static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
0766 {
0767     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0768     struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
0769     u32 reg;
0770 
0771     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
0772     if (width == MMC_BUS_WIDTH_8)
0773         reg |= CON_DW8;
0774     else
0775         reg &= ~CON_DW8;
0776     sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
0777 
0778     sdhci_set_bus_width(host, width);
0779 }
0780 
0781 static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
0782 {
0783     u32 reg;
0784     ktime_t timeout;
0785     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0786     struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
0787 
0788     if (omap_host->power_mode == power_mode)
0789         return;
0790 
0791     if (power_mode != MMC_POWER_ON)
0792         return;
0793 
0794     disable_irq(host->irq);
0795 
0796     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
0797     reg |= CON_INIT;
0798     sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
0799     sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
0800 
0801     /* wait 1ms */
0802     timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
0803     while (1) {
0804         bool timedout = ktime_after(ktime_get(), timeout);
0805 
0806         if (sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)
0807             break;
0808         if (WARN_ON(timedout))
0809             return;
0810         usleep_range(5, 10);
0811     }
0812 
0813     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
0814     reg &= ~CON_INIT;
0815     sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
0816     sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
0817 
0818     enable_irq(host->irq);
0819 }
0820 
0821 static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
0822                      unsigned int timing)
0823 {
0824     u32 reg;
0825     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0826     struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
0827 
0828     sdhci_omap_stop_clock(omap_host);
0829 
0830     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
0831     if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
0832         reg |= CON_DDR;
0833     else
0834         reg &= ~CON_DDR;
0835     sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
0836 
0837     sdhci_set_uhs_signaling(host, timing);
0838     sdhci_omap_start_clock(omap_host);
0839 }
0840 
0841 #define MMC_TIMEOUT_US      20000       /* 20000 micro Sec */
0842 static void sdhci_omap_reset(struct sdhci_host *host, u8 mask)
0843 {
0844     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0845     struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
0846     unsigned long limit = MMC_TIMEOUT_US;
0847     unsigned long i = 0;
0848     u32 sysc;
0849 
0850     /* Save target module sysconfig configured by SoC PM layer */
0851     if (mask & SDHCI_RESET_ALL)
0852         sysc = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCONFIG);
0853 
0854     /* Don't reset data lines during tuning operation */
0855     if (omap_host->is_tuning)
0856         mask &= ~SDHCI_RESET_DATA;
0857 
0858     if (omap_host->flags & SDHCI_OMAP_SPECIAL_RESET) {
0859         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
0860         while ((!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) &&
0861                (i++ < limit))
0862             udelay(1);
0863         i = 0;
0864         while ((sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) &&
0865                (i++ < limit))
0866             udelay(1);
0867 
0868         if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)
0869             dev_err(mmc_dev(host->mmc),
0870                 "Timeout waiting on controller reset in %s\n",
0871                 __func__);
0872 
0873         goto restore_sysc;
0874     }
0875 
0876     sdhci_reset(host, mask);
0877 
0878 restore_sysc:
0879     if (mask & SDHCI_RESET_ALL)
0880         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCONFIG, sysc);
0881 }
0882 
0883 #define CMD_ERR_MASK (SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX |\
0884               SDHCI_INT_TIMEOUT)
0885 #define CMD_MASK (CMD_ERR_MASK | SDHCI_INT_RESPONSE)
0886 
0887 static u32 sdhci_omap_irq(struct sdhci_host *host, u32 intmask)
0888 {
0889     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0890     struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
0891 
0892     if (omap_host->is_tuning && host->cmd && !host->data_early &&
0893         (intmask & CMD_ERR_MASK)) {
0894 
0895         /*
0896          * Since we are not resetting data lines during tuning
0897          * operation, data error or data complete interrupts
0898          * might still arrive. Mark this request as a failure
0899          * but still wait for the data interrupt
0900          */
0901         if (intmask & SDHCI_INT_TIMEOUT)
0902             host->cmd->error = -ETIMEDOUT;
0903         else
0904             host->cmd->error = -EILSEQ;
0905 
0906         host->cmd = NULL;
0907 
0908         /*
0909          * Sometimes command error interrupts and command complete
0910          * interrupt will arrive together. Clear all command related
0911          * interrupts here.
0912          */
0913         sdhci_writel(host, intmask & CMD_MASK, SDHCI_INT_STATUS);
0914         intmask &= ~CMD_MASK;
0915     }
0916 
0917     return intmask;
0918 }
0919 
0920 static void sdhci_omap_set_timeout(struct sdhci_host *host,
0921                    struct mmc_command *cmd)
0922 {
0923     if (cmd->opcode == MMC_ERASE)
0924         sdhci_set_data_timeout_irq(host, false);
0925 
0926     __sdhci_set_timeout(host, cmd);
0927 }
0928 
0929 static struct sdhci_ops sdhci_omap_ops = {
0930     .set_clock = sdhci_omap_set_clock,
0931     .set_power = sdhci_omap_set_power,
0932     .enable_dma = sdhci_omap_enable_dma,
0933     .get_max_clock = sdhci_pltfm_clk_get_max_clock,
0934     .get_min_clock = sdhci_omap_get_min_clock,
0935     .set_bus_width = sdhci_omap_set_bus_width,
0936     .platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
0937     .reset = sdhci_omap_reset,
0938     .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
0939     .irq = sdhci_omap_irq,
0940     .set_timeout = sdhci_omap_set_timeout,
0941 };
0942 
0943 static unsigned int sdhci_omap_regulator_get_caps(struct device *dev,
0944                           const char *name)
0945 {
0946     struct regulator *reg;
0947     unsigned int caps = 0;
0948 
0949     reg = regulator_get(dev, name);
0950     if (IS_ERR(reg))
0951         return ~0U;
0952 
0953     if (regulator_is_supported_voltage(reg, 1700000, 1950000))
0954         caps |= SDHCI_CAN_VDD_180;
0955     if (regulator_is_supported_voltage(reg, 2700000, 3150000))
0956         caps |= SDHCI_CAN_VDD_300;
0957     if (regulator_is_supported_voltage(reg, 3150000, 3600000))
0958         caps |= SDHCI_CAN_VDD_330;
0959 
0960     regulator_put(reg);
0961 
0962     return caps;
0963 }
0964 
0965 static int sdhci_omap_set_capabilities(struct sdhci_host *host)
0966 {
0967     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0968     struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
0969     struct device *dev = omap_host->dev;
0970     const u32 mask = SDHCI_CAN_VDD_180 | SDHCI_CAN_VDD_300 | SDHCI_CAN_VDD_330;
0971     unsigned int pbias, vqmmc, caps = 0;
0972     u32 reg;
0973 
0974     pbias = sdhci_omap_regulator_get_caps(dev, "pbias");
0975     vqmmc = sdhci_omap_regulator_get_caps(dev, "vqmmc");
0976     caps = pbias & vqmmc;
0977 
0978     if (pbias != ~0U && vqmmc == ~0U)
0979         dev_warn(dev, "vqmmc regulator missing for pbias\n");
0980     else if (caps == ~0U)
0981         return 0;
0982 
0983     /*
0984      * Quirk handling to allow 3.0V vqmmc with a valid 3.3V PBIAS. This is
0985      * needed for 3.0V ldo9_reg on omap5 at least.
0986      */
0987     if (pbias != ~0U && (pbias & SDHCI_CAN_VDD_330) &&
0988         (vqmmc & SDHCI_CAN_VDD_300))
0989         caps |= SDHCI_CAN_VDD_330;
0990 
0991     /* voltage capabilities might be set by boot loader, clear it */
0992     reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
0993     reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
0994 
0995     if (caps & SDHCI_CAN_VDD_180)
0996         reg |= CAPA_VS18;
0997 
0998     if (caps & SDHCI_CAN_VDD_300)
0999         reg |= CAPA_VS30;
1000 
1001     if (caps & SDHCI_CAN_VDD_330)
1002         reg |= CAPA_VS33;
1003 
1004     sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
1005 
1006     host->caps &= ~mask;
1007     host->caps |= caps;
1008 
1009     return 0;
1010 }
1011 
1012 static const struct sdhci_pltfm_data sdhci_omap_pdata = {
1013     .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1014           SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1015           SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1016           SDHCI_QUIRK_NO_HISPD_BIT |
1017           SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
1018     .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
1019            SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1020            SDHCI_QUIRK2_RSP_136_HAS_CRC |
1021            SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
1022     .ops = &sdhci_omap_ops,
1023 };
1024 
1025 static const struct sdhci_omap_data omap2430_data = {
1026     .omap_offset = 0,
1027     .offset = 0x100,
1028 };
1029 
1030 static const struct sdhci_omap_data omap3_data = {
1031     .omap_offset = 0,
1032     .offset = 0x100,
1033 };
1034 
1035 static const struct sdhci_omap_data omap4_data = {
1036     .omap_offset = 0x100,
1037     .offset = 0x200,
1038     .flags = SDHCI_OMAP_SPECIAL_RESET,
1039 };
1040 
1041 static const struct sdhci_omap_data omap5_data = {
1042     .omap_offset = 0x100,
1043     .offset = 0x200,
1044     .flags = SDHCI_OMAP_SPECIAL_RESET,
1045 };
1046 
1047 static const struct sdhci_omap_data k2g_data = {
1048     .omap_offset = 0x100,
1049     .offset = 0x200,
1050 };
1051 
1052 static const struct sdhci_omap_data am335_data = {
1053     .omap_offset = 0x100,
1054     .offset = 0x200,
1055     .flags = SDHCI_OMAP_SPECIAL_RESET,
1056 };
1057 
1058 static const struct sdhci_omap_data am437_data = {
1059     .omap_offset = 0x100,
1060     .offset = 0x200,
1061     .flags = SDHCI_OMAP_SPECIAL_RESET,
1062 };
1063 
1064 static const struct sdhci_omap_data dra7_data = {
1065     .omap_offset = 0x100,
1066     .offset = 0x200,
1067     .flags  = SDHCI_OMAP_REQUIRE_IODELAY,
1068 };
1069 
1070 static const struct of_device_id omap_sdhci_match[] = {
1071     { .compatible = "ti,omap2430-sdhci", .data = &omap2430_data },
1072     { .compatible = "ti,omap3-sdhci", .data = &omap3_data },
1073     { .compatible = "ti,omap4-sdhci", .data = &omap4_data },
1074     { .compatible = "ti,omap5-sdhci", .data = &omap5_data },
1075     { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
1076     { .compatible = "ti,k2g-sdhci", .data = &k2g_data },
1077     { .compatible = "ti,am335-sdhci", .data = &am335_data },
1078     { .compatible = "ti,am437-sdhci", .data = &am437_data },
1079     {},
1080 };
1081 MODULE_DEVICE_TABLE(of, omap_sdhci_match);
1082 
1083 static struct pinctrl_state
1084 *sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
1085                   u32 *caps, u32 capmask)
1086 {
1087     struct device *dev = omap_host->dev;
1088     char *version = omap_host->version;
1089     struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
1090     char str[20];
1091 
1092     if (!(*caps & capmask))
1093         goto ret;
1094 
1095     if (version) {
1096         snprintf(str, 20, "%s-%s", mode, version);
1097         pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
1098     }
1099 
1100     if (IS_ERR(pinctrl_state))
1101         pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
1102 
1103     if (IS_ERR(pinctrl_state)) {
1104         dev_err(dev, "no pinctrl state for %s mode", mode);
1105         *caps &= ~capmask;
1106     }
1107 
1108 ret:
1109     return pinctrl_state;
1110 }
1111 
1112 static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
1113                            *omap_host)
1114 {
1115     struct device *dev = omap_host->dev;
1116     struct sdhci_host *host = omap_host->host;
1117     struct mmc_host *mmc = host->mmc;
1118     u32 *caps = &mmc->caps;
1119     u32 *caps2 = &mmc->caps2;
1120     struct pinctrl_state *state;
1121     struct pinctrl_state **pinctrl_state;
1122 
1123     if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
1124         return 0;
1125 
1126     pinctrl_state = devm_kcalloc(dev,
1127                      MMC_TIMING_MMC_HS200 + 1,
1128                      sizeof(*pinctrl_state),
1129                      GFP_KERNEL);
1130     if (!pinctrl_state)
1131         return -ENOMEM;
1132 
1133     omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
1134     if (IS_ERR(omap_host->pinctrl)) {
1135         dev_err(dev, "Cannot get pinctrl\n");
1136         return PTR_ERR(omap_host->pinctrl);
1137     }
1138 
1139     state = pinctrl_lookup_state(omap_host->pinctrl, "default");
1140     if (IS_ERR(state)) {
1141         dev_err(dev, "no pinctrl state for default mode\n");
1142         return PTR_ERR(state);
1143     }
1144     pinctrl_state[MMC_TIMING_LEGACY] = state;
1145 
1146     state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
1147                          MMC_CAP_UHS_SDR104);
1148     if (!IS_ERR(state))
1149         pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
1150 
1151     state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
1152                          MMC_CAP_UHS_DDR50);
1153     if (!IS_ERR(state))
1154         pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
1155 
1156     state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
1157                          MMC_CAP_UHS_SDR50);
1158     if (!IS_ERR(state))
1159         pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
1160 
1161     state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
1162                          MMC_CAP_UHS_SDR25);
1163     if (!IS_ERR(state))
1164         pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
1165 
1166     state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
1167                          MMC_CAP_UHS_SDR12);
1168     if (!IS_ERR(state))
1169         pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
1170 
1171     state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
1172                          MMC_CAP_1_8V_DDR);
1173     if (!IS_ERR(state)) {
1174         pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1175     } else {
1176         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
1177                              caps,
1178                              MMC_CAP_3_3V_DDR);
1179         if (!IS_ERR(state))
1180             pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1181     }
1182 
1183     state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1184                          MMC_CAP_SD_HIGHSPEED);
1185     if (!IS_ERR(state))
1186         pinctrl_state[MMC_TIMING_SD_HS] = state;
1187 
1188     state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1189                          MMC_CAP_MMC_HIGHSPEED);
1190     if (!IS_ERR(state))
1191         pinctrl_state[MMC_TIMING_MMC_HS] = state;
1192 
1193     state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
1194                          MMC_CAP2_HS200_1_8V_SDR);
1195     if (!IS_ERR(state))
1196         pinctrl_state[MMC_TIMING_MMC_HS200] = state;
1197 
1198     omap_host->pinctrl_state = pinctrl_state;
1199 
1200     return 0;
1201 }
1202 
1203 static const struct soc_device_attribute sdhci_omap_soc_devices[] = {
1204     {
1205         .machine = "DRA7[45]*",
1206         .revision = "ES1.[01]",
1207     },
1208     {
1209         /* sentinel */
1210     }
1211 };
1212 
1213 static int sdhci_omap_probe(struct platform_device *pdev)
1214 {
1215     int ret;
1216     u32 offset;
1217     struct device *dev = &pdev->dev;
1218     struct sdhci_host *host;
1219     struct sdhci_pltfm_host *pltfm_host;
1220     struct sdhci_omap_host *omap_host;
1221     struct mmc_host *mmc;
1222     const struct sdhci_omap_data *data;
1223     const struct soc_device_attribute *soc;
1224     struct resource *regs;
1225 
1226     data = of_device_get_match_data(&pdev->dev);
1227     if (!data) {
1228         dev_err(dev, "no sdhci omap data\n");
1229         return -EINVAL;
1230     }
1231     offset = data->offset;
1232 
1233     regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1234     if (!regs)
1235         return -ENXIO;
1236 
1237     host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
1238                 sizeof(*omap_host));
1239     if (IS_ERR(host)) {
1240         dev_err(dev, "Failed sdhci_pltfm_init\n");
1241         return PTR_ERR(host);
1242     }
1243 
1244     pltfm_host = sdhci_priv(host);
1245     omap_host = sdhci_pltfm_priv(pltfm_host);
1246     omap_host->host = host;
1247     omap_host->base = host->ioaddr;
1248     omap_host->dev = dev;
1249     omap_host->power_mode = MMC_POWER_UNDEFINED;
1250     omap_host->timing = MMC_TIMING_LEGACY;
1251     omap_host->flags = data->flags;
1252     omap_host->omap_offset = data->omap_offset;
1253     omap_host->con = -EINVAL; /* Prevent invalid restore on first resume */
1254     host->ioaddr += offset;
1255     host->mapbase = regs->start + offset;
1256 
1257     mmc = host->mmc;
1258     sdhci_get_of_property(pdev);
1259     ret = mmc_of_parse(mmc);
1260     if (ret)
1261         goto err_pltfm_free;
1262 
1263     soc = soc_device_match(sdhci_omap_soc_devices);
1264     if (soc) {
1265         omap_host->version = "rev11";
1266         if (!strcmp(dev_name(dev), "4809c000.mmc"))
1267             mmc->f_max = 96000000;
1268         if (!strcmp(dev_name(dev), "480b4000.mmc"))
1269             mmc->f_max = 48000000;
1270         if (!strcmp(dev_name(dev), "480ad000.mmc"))
1271             mmc->f_max = 48000000;
1272     }
1273 
1274     if (!mmc_can_gpio_ro(mmc))
1275         mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
1276 
1277     pltfm_host->clk = devm_clk_get(dev, "fck");
1278     if (IS_ERR(pltfm_host->clk)) {
1279         ret = PTR_ERR(pltfm_host->clk);
1280         goto err_pltfm_free;
1281     }
1282 
1283     ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
1284     if (ret) {
1285         dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
1286         goto err_pltfm_free;
1287     }
1288 
1289     omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
1290     if (IS_ERR(omap_host->pbias)) {
1291         ret = PTR_ERR(omap_host->pbias);
1292         if (ret != -ENODEV)
1293             goto err_pltfm_free;
1294         dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
1295     }
1296     omap_host->pbias_enabled = false;
1297 
1298     /*
1299      * omap_device_pm_domain has callbacks to enable the main
1300      * functional clock, interface clock and also configure the
1301      * SYSCONFIG register to clear any boot loader set voltage
1302      * capabilities before calling sdhci_setup_host(). The
1303      * callback will be invoked as part of pm_runtime_get_sync.
1304      */
1305     pm_runtime_use_autosuspend(dev);
1306     pm_runtime_set_autosuspend_delay(dev, 50);
1307     pm_runtime_enable(dev);
1308     ret = pm_runtime_resume_and_get(dev);
1309     if (ret) {
1310         dev_err(dev, "pm_runtime_get_sync failed\n");
1311         goto err_rpm_disable;
1312     }
1313 
1314     ret = sdhci_omap_set_capabilities(host);
1315     if (ret) {
1316         dev_err(dev, "failed to set system capabilities\n");
1317         goto err_rpm_put;
1318     }
1319 
1320     host->mmc_host_ops.start_signal_voltage_switch =
1321                     sdhci_omap_start_signal_voltage_switch;
1322     host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
1323     host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
1324     host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
1325     host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq;
1326 
1327     /*
1328      * Switch to external DMA only if there is the "dmas" property and
1329      * ADMA is not available on the controller instance.
1330      */
1331     if (device_property_present(dev, "dmas") &&
1332         !sdhci_omap_has_adma(omap_host, offset))
1333         sdhci_switch_external_dma(host, true);
1334 
1335     if (device_property_read_bool(dev, "ti,non-removable")) {
1336         dev_warn_once(dev, "using old ti,non-removable property\n");
1337         mmc->caps |= MMC_CAP_NONREMOVABLE;
1338     }
1339 
1340     /* R1B responses is required to properly manage HW busy detection. */
1341     mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
1342 
1343     /* Allow card power off and runtime PM for eMMC/SD card devices */
1344     mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_AGGRESSIVE_PM;
1345 
1346     ret = sdhci_setup_host(host);
1347     if (ret)
1348         goto err_rpm_put;
1349 
1350     ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
1351     if (ret)
1352         goto err_cleanup_host;
1353 
1354     ret = __sdhci_add_host(host);
1355     if (ret)
1356         goto err_cleanup_host;
1357 
1358     /*
1359      * SDIO devices can use the dat1 pin as a wake-up interrupt. Some
1360      * devices like wl1xxx, use an out-of-band GPIO interrupt instead.
1361      */
1362     omap_host->wakeirq = of_irq_get_byname(dev->of_node, "wakeup");
1363     if (omap_host->wakeirq == -EPROBE_DEFER) {
1364         ret = -EPROBE_DEFER;
1365         goto err_cleanup_host;
1366     }
1367     if (omap_host->wakeirq > 0) {
1368         device_init_wakeup(dev, true);
1369         ret = dev_pm_set_dedicated_wake_irq(dev, omap_host->wakeirq);
1370         if (ret) {
1371             device_init_wakeup(dev, false);
1372             goto err_cleanup_host;
1373         }
1374         host->mmc->pm_caps |= MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1375     }
1376 
1377     pm_runtime_mark_last_busy(dev);
1378     pm_runtime_put_autosuspend(dev);
1379 
1380     return 0;
1381 
1382 err_cleanup_host:
1383     sdhci_cleanup_host(host);
1384 
1385 err_rpm_put:
1386     pm_runtime_mark_last_busy(dev);
1387     pm_runtime_put_autosuspend(dev);
1388 err_rpm_disable:
1389     pm_runtime_dont_use_autosuspend(dev);
1390     pm_runtime_disable(dev);
1391 
1392 err_pltfm_free:
1393     sdhci_pltfm_free(pdev);
1394     return ret;
1395 }
1396 
1397 static int sdhci_omap_remove(struct platform_device *pdev)
1398 {
1399     struct device *dev = &pdev->dev;
1400     struct sdhci_host *host = platform_get_drvdata(pdev);
1401 
1402     pm_runtime_get_sync(dev);
1403     sdhci_remove_host(host, true);
1404     device_init_wakeup(dev, false);
1405     dev_pm_clear_wake_irq(dev);
1406     pm_runtime_dont_use_autosuspend(dev);
1407     pm_runtime_put_sync(dev);
1408     /* Ensure device gets disabled despite userspace sysfs config */
1409     pm_runtime_force_suspend(dev);
1410     sdhci_pltfm_free(pdev);
1411 
1412     return 0;
1413 }
1414 
1415 #ifdef CONFIG_PM
1416 static void __maybe_unused sdhci_omap_context_save(struct sdhci_omap_host *omap_host)
1417 {
1418     omap_host->con = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
1419     omap_host->hctl = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
1420     omap_host->sysctl = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
1421     omap_host->capa = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
1422     omap_host->ie = sdhci_omap_readl(omap_host, SDHCI_OMAP_IE);
1423     omap_host->ise = sdhci_omap_readl(omap_host, SDHCI_OMAP_ISE);
1424 }
1425 
1426 /* Order matters here, HCTL must be restored in two phases */
1427 static void __maybe_unused sdhci_omap_context_restore(struct sdhci_omap_host *omap_host)
1428 {
1429     sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, omap_host->hctl);
1430     sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, omap_host->capa);
1431     sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, omap_host->hctl);
1432 
1433     sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, omap_host->sysctl);
1434     sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, omap_host->con);
1435     sdhci_omap_writel(omap_host, SDHCI_OMAP_IE, omap_host->ie);
1436     sdhci_omap_writel(omap_host, SDHCI_OMAP_ISE, omap_host->ise);
1437 }
1438 
1439 static int __maybe_unused sdhci_omap_runtime_suspend(struct device *dev)
1440 {
1441     struct sdhci_host *host = dev_get_drvdata(dev);
1442     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1443     struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
1444 
1445     if (omap_host->con != -EINVAL)
1446         sdhci_runtime_suspend_host(host);
1447 
1448     sdhci_omap_context_save(omap_host);
1449 
1450     pinctrl_pm_select_idle_state(dev);
1451 
1452     return 0;
1453 }
1454 
1455 static int __maybe_unused sdhci_omap_runtime_resume(struct device *dev)
1456 {
1457     struct sdhci_host *host = dev_get_drvdata(dev);
1458     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1459     struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
1460 
1461     pinctrl_pm_select_default_state(dev);
1462 
1463     if (omap_host->con != -EINVAL) {
1464         sdhci_omap_context_restore(omap_host);
1465         sdhci_runtime_resume_host(host, 0);
1466     }
1467 
1468     return 0;
1469 }
1470 #endif
1471 
1472 static const struct dev_pm_ops sdhci_omap_dev_pm_ops = {
1473     SET_RUNTIME_PM_OPS(sdhci_omap_runtime_suspend,
1474                sdhci_omap_runtime_resume, NULL)
1475     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1476                 pm_runtime_force_resume)
1477 };
1478 
1479 static struct platform_driver sdhci_omap_driver = {
1480     .probe = sdhci_omap_probe,
1481     .remove = sdhci_omap_remove,
1482     .driver = {
1483            .name = "sdhci-omap",
1484            .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1485            .pm = &sdhci_omap_dev_pm_ops,
1486            .of_match_table = omap_sdhci_match,
1487           },
1488 };
1489 
1490 module_platform_driver(sdhci_omap_driver);
1491 
1492 MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
1493 MODULE_AUTHOR("Texas Instruments Inc.");
1494 MODULE_LICENSE("GPL v2");
1495 MODULE_ALIAS("platform:sdhci_omap");
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