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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Freescale eSDHC controller driver.
0004  *
0005  * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
0006  * Copyright (c) 2009 MontaVista Software, Inc.
0007  * Copyright 2020 NXP
0008  *
0009  * Authors: Xiaobo Xie <X.Xie@freescale.com>
0010  *      Anton Vorontsov <avorontsov@ru.mvista.com>
0011  */
0012 
0013 #include <linux/err.h>
0014 #include <linux/io.h>
0015 #include <linux/of.h>
0016 #include <linux/of_address.h>
0017 #include <linux/delay.h>
0018 #include <linux/module.h>
0019 #include <linux/sys_soc.h>
0020 #include <linux/clk.h>
0021 #include <linux/ktime.h>
0022 #include <linux/dma-mapping.h>
0023 #include <linux/iopoll.h>
0024 #include <linux/mmc/host.h>
0025 #include <linux/mmc/mmc.h>
0026 #include "sdhci-pltfm.h"
0027 #include "sdhci-esdhc.h"
0028 
0029 #define VENDOR_V_22 0x12
0030 #define VENDOR_V_23 0x13
0031 
0032 #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1)
0033 
0034 struct esdhc_clk_fixup {
0035     const unsigned int sd_dflt_max_clk;
0036     const unsigned int max_clk[MMC_TIMING_NUM];
0037 };
0038 
0039 static const struct esdhc_clk_fixup ls1021a_esdhc_clk = {
0040     .sd_dflt_max_clk = 25000000,
0041     .max_clk[MMC_TIMING_MMC_HS] = 46500000,
0042     .max_clk[MMC_TIMING_SD_HS] = 46500000,
0043 };
0044 
0045 static const struct esdhc_clk_fixup ls1046a_esdhc_clk = {
0046     .sd_dflt_max_clk = 25000000,
0047     .max_clk[MMC_TIMING_UHS_SDR104] = 167000000,
0048     .max_clk[MMC_TIMING_MMC_HS200] = 167000000,
0049 };
0050 
0051 static const struct esdhc_clk_fixup ls1012a_esdhc_clk = {
0052     .sd_dflt_max_clk = 25000000,
0053     .max_clk[MMC_TIMING_UHS_SDR104] = 125000000,
0054     .max_clk[MMC_TIMING_MMC_HS200] = 125000000,
0055 };
0056 
0057 static const struct esdhc_clk_fixup p1010_esdhc_clk = {
0058     .sd_dflt_max_clk = 20000000,
0059     .max_clk[MMC_TIMING_LEGACY] = 20000000,
0060     .max_clk[MMC_TIMING_MMC_HS] = 42000000,
0061     .max_clk[MMC_TIMING_SD_HS] = 40000000,
0062 };
0063 
0064 static const struct of_device_id sdhci_esdhc_of_match[] = {
0065     { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
0066     { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
0067     { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
0068     { .compatible = "fsl,p1010-esdhc",   .data = &p1010_esdhc_clk},
0069     { .compatible = "fsl,mpc8379-esdhc" },
0070     { .compatible = "fsl,mpc8536-esdhc" },
0071     { .compatible = "fsl,esdhc" },
0072     { }
0073 };
0074 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
0075 
0076 struct sdhci_esdhc {
0077     u8 vendor_ver;
0078     u8 spec_ver;
0079     bool quirk_incorrect_hostver;
0080     bool quirk_limited_clk_division;
0081     bool quirk_unreliable_pulse_detection;
0082     bool quirk_tuning_erratum_type1;
0083     bool quirk_tuning_erratum_type2;
0084     bool quirk_ignore_data_inhibit;
0085     bool quirk_delay_before_data_reset;
0086     bool quirk_trans_complete_erratum;
0087     bool in_sw_tuning;
0088     unsigned int peripheral_clock;
0089     const struct esdhc_clk_fixup *clk_fixup;
0090     u32 div_ratio;
0091 };
0092 
0093 /**
0094  * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
0095  *             to make it compatible with SD spec.
0096  *
0097  * @host: pointer to sdhci_host
0098  * @spec_reg: SD spec register address
0099  * @value: 32bit eSDHC register value on spec_reg address
0100  *
0101  * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
0102  * registers are 32 bits. There are differences in register size, register
0103  * address, register function, bit position and function between eSDHC spec
0104  * and SD spec.
0105  *
0106  * Return a fixed up register value
0107  */
0108 static u32 esdhc_readl_fixup(struct sdhci_host *host,
0109                      int spec_reg, u32 value)
0110 {
0111     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0112     struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
0113     u32 ret;
0114 
0115     /*
0116      * The bit of ADMA flag in eSDHC is not compatible with standard
0117      * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
0118      * supported by eSDHC.
0119      * And for many FSL eSDHC controller, the reset value of field
0120      * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA,
0121      * only these vendor version is greater than 2.2/0x12 support ADMA.
0122      */
0123     if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
0124         if (esdhc->vendor_ver > VENDOR_V_22) {
0125             ret = value | SDHCI_CAN_DO_ADMA2;
0126             return ret;
0127         }
0128     }
0129     /*
0130      * The DAT[3:0] line signal levels and the CMD line signal level are
0131      * not compatible with standard SDHC register. The line signal levels
0132      * DAT[7:0] are at bits 31:24 and the command line signal level is at
0133      * bit 23. All other bits are the same as in the standard SDHC
0134      * register.
0135      */
0136     if (spec_reg == SDHCI_PRESENT_STATE) {
0137         ret = value & 0x000fffff;
0138         ret |= (value >> 4) & SDHCI_DATA_LVL_MASK;
0139         ret |= (value << 1) & SDHCI_CMD_LVL;
0140         return ret;
0141     }
0142 
0143     /*
0144      * DTS properties of mmc host are used to enable each speed mode
0145      * according to soc and board capability. So clean up
0146      * SDR50/SDR104/DDR50 support bits here.
0147      */
0148     if (spec_reg == SDHCI_CAPABILITIES_1) {
0149         ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
0150                 SDHCI_SUPPORT_DDR50);
0151         return ret;
0152     }
0153 
0154     /*
0155      * Some controllers have unreliable Data Line Active
0156      * bit for commands with busy signal. This affects
0157      * Command Inhibit (data) bit. Just ignore it since
0158      * MMC core driver has already polled card status
0159      * with CMD13 after any command with busy siganl.
0160      */
0161     if ((spec_reg == SDHCI_PRESENT_STATE) &&
0162     (esdhc->quirk_ignore_data_inhibit == true)) {
0163         ret = value & ~SDHCI_DATA_INHIBIT;
0164         return ret;
0165     }
0166 
0167     ret = value;
0168     return ret;
0169 }
0170 
0171 static u16 esdhc_readw_fixup(struct sdhci_host *host,
0172                      int spec_reg, u32 value)
0173 {
0174     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0175     struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
0176     u16 ret;
0177     int shift = (spec_reg & 0x2) * 8;
0178 
0179     if (spec_reg == SDHCI_TRANSFER_MODE)
0180         return pltfm_host->xfer_mode_shadow;
0181 
0182     if (spec_reg == SDHCI_HOST_VERSION)
0183         ret = value & 0xffff;
0184     else
0185         ret = (value >> shift) & 0xffff;
0186     /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect
0187      * vendor version and spec version information.
0188      */
0189     if ((spec_reg == SDHCI_HOST_VERSION) &&
0190         (esdhc->quirk_incorrect_hostver))
0191         ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
0192     return ret;
0193 }
0194 
0195 static u8 esdhc_readb_fixup(struct sdhci_host *host,
0196                      int spec_reg, u32 value)
0197 {
0198     u8 ret;
0199     u8 dma_bits;
0200     int shift = (spec_reg & 0x3) * 8;
0201 
0202     ret = (value >> shift) & 0xff;
0203 
0204     /*
0205      * "DMA select" locates at offset 0x28 in SD specification, but on
0206      * P5020 or P3041, it locates at 0x29.
0207      */
0208     if (spec_reg == SDHCI_HOST_CONTROL) {
0209         /* DMA select is 22,23 bits in Protocol Control Register */
0210         dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
0211         /* fixup the result */
0212         ret &= ~SDHCI_CTRL_DMA_MASK;
0213         ret |= dma_bits;
0214     }
0215     return ret;
0216 }
0217 
0218 /**
0219  * esdhc_write*_fixup - Fixup the SD spec register value so that it could be
0220  *          written into eSDHC register.
0221  *
0222  * @host: pointer to sdhci_host
0223  * @spec_reg: SD spec register address
0224  * @value: 8/16/32bit SD spec register value that would be written
0225  * @old_value: 32bit eSDHC register value on spec_reg address
0226  *
0227  * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
0228  * registers are 32 bits. There are differences in register size, register
0229  * address, register function, bit position and function between eSDHC spec
0230  * and SD spec.
0231  *
0232  * Return a fixed up register value
0233  */
0234 static u32 esdhc_writel_fixup(struct sdhci_host *host,
0235                      int spec_reg, u32 value, u32 old_value)
0236 {
0237     u32 ret;
0238 
0239     /*
0240      * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
0241      * when SYSCTL[RSTD] is set for some special operations.
0242      * No any impact on other operation.
0243      */
0244     if (spec_reg == SDHCI_INT_ENABLE)
0245         ret = value | SDHCI_INT_BLK_GAP;
0246     else
0247         ret = value;
0248 
0249     return ret;
0250 }
0251 
0252 static u32 esdhc_writew_fixup(struct sdhci_host *host,
0253                      int spec_reg, u16 value, u32 old_value)
0254 {
0255     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0256     int shift = (spec_reg & 0x2) * 8;
0257     u32 ret;
0258 
0259     switch (spec_reg) {
0260     case SDHCI_TRANSFER_MODE:
0261         /*
0262          * Postpone this write, we must do it together with a
0263          * command write that is down below. Return old value.
0264          */
0265         pltfm_host->xfer_mode_shadow = value;
0266         return old_value;
0267     case SDHCI_COMMAND:
0268         ret = (value << 16) | pltfm_host->xfer_mode_shadow;
0269         return ret;
0270     }
0271 
0272     ret = old_value & (~(0xffff << shift));
0273     ret |= (value << shift);
0274 
0275     if (spec_reg == SDHCI_BLOCK_SIZE) {
0276         /*
0277          * Two last DMA bits are reserved, and first one is used for
0278          * non-standard blksz of 4096 bytes that we don't support
0279          * yet. So clear the DMA boundary bits.
0280          */
0281         ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0));
0282     }
0283     return ret;
0284 }
0285 
0286 static u32 esdhc_writeb_fixup(struct sdhci_host *host,
0287                      int spec_reg, u8 value, u32 old_value)
0288 {
0289     u32 ret;
0290     u32 dma_bits;
0291     u8 tmp;
0292     int shift = (spec_reg & 0x3) * 8;
0293 
0294     /*
0295      * eSDHC doesn't have a standard power control register, so we do
0296      * nothing here to avoid incorrect operation.
0297      */
0298     if (spec_reg == SDHCI_POWER_CONTROL)
0299         return old_value;
0300     /*
0301      * "DMA select" location is offset 0x28 in SD specification, but on
0302      * P5020 or P3041, it's located at 0x29.
0303      */
0304     if (spec_reg == SDHCI_HOST_CONTROL) {
0305         /*
0306          * If host control register is not standard, exit
0307          * this function
0308          */
0309         if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
0310             return old_value;
0311 
0312         /* DMA select is 22,23 bits in Protocol Control Register */
0313         dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
0314         ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits;
0315         tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
0316               (old_value & SDHCI_CTRL_DMA_MASK);
0317         ret = (ret & (~0xff)) | tmp;
0318 
0319         /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */
0320         ret &= ~ESDHC_HOST_CONTROL_RES;
0321         return ret;
0322     }
0323 
0324     ret = (old_value & (~(0xff << shift))) | (value << shift);
0325     return ret;
0326 }
0327 
0328 static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
0329 {
0330     u32 ret;
0331     u32 value;
0332 
0333     if (reg == SDHCI_CAPABILITIES_1)
0334         value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1);
0335     else
0336         value = ioread32be(host->ioaddr + reg);
0337 
0338     ret = esdhc_readl_fixup(host, reg, value);
0339 
0340     return ret;
0341 }
0342 
0343 static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
0344 {
0345     u32 ret;
0346     u32 value;
0347 
0348     if (reg == SDHCI_CAPABILITIES_1)
0349         value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1);
0350     else
0351         value = ioread32(host->ioaddr + reg);
0352 
0353     ret = esdhc_readl_fixup(host, reg, value);
0354 
0355     return ret;
0356 }
0357 
0358 static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
0359 {
0360     u16 ret;
0361     u32 value;
0362     int base = reg & ~0x3;
0363 
0364     value = ioread32be(host->ioaddr + base);
0365     ret = esdhc_readw_fixup(host, reg, value);
0366     return ret;
0367 }
0368 
0369 static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
0370 {
0371     u16 ret;
0372     u32 value;
0373     int base = reg & ~0x3;
0374 
0375     value = ioread32(host->ioaddr + base);
0376     ret = esdhc_readw_fixup(host, reg, value);
0377     return ret;
0378 }
0379 
0380 static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
0381 {
0382     u8 ret;
0383     u32 value;
0384     int base = reg & ~0x3;
0385 
0386     value = ioread32be(host->ioaddr + base);
0387     ret = esdhc_readb_fixup(host, reg, value);
0388     return ret;
0389 }
0390 
0391 static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
0392 {
0393     u8 ret;
0394     u32 value;
0395     int base = reg & ~0x3;
0396 
0397     value = ioread32(host->ioaddr + base);
0398     ret = esdhc_readb_fixup(host, reg, value);
0399     return ret;
0400 }
0401 
0402 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
0403 {
0404     u32 value;
0405 
0406     value = esdhc_writel_fixup(host, reg, val, 0);
0407     iowrite32be(value, host->ioaddr + reg);
0408 }
0409 
0410 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
0411 {
0412     u32 value;
0413 
0414     value = esdhc_writel_fixup(host, reg, val, 0);
0415     iowrite32(value, host->ioaddr + reg);
0416 }
0417 
0418 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
0419 {
0420     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0421     struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
0422     int base = reg & ~0x3;
0423     u32 value;
0424     u32 ret;
0425 
0426     value = ioread32be(host->ioaddr + base);
0427     ret = esdhc_writew_fixup(host, reg, val, value);
0428     if (reg != SDHCI_TRANSFER_MODE)
0429         iowrite32be(ret, host->ioaddr + base);
0430 
0431     /* Starting SW tuning requires ESDHC_SMPCLKSEL to be set
0432      * 1us later after ESDHC_EXTN is set.
0433      */
0434     if (base == ESDHC_SYSTEM_CONTROL_2) {
0435         if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) &&
0436             esdhc->in_sw_tuning) {
0437             udelay(1);
0438             ret |= ESDHC_SMPCLKSEL;
0439             iowrite32be(ret, host->ioaddr + base);
0440         }
0441     }
0442 }
0443 
0444 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
0445 {
0446     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0447     struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
0448     int base = reg & ~0x3;
0449     u32 value;
0450     u32 ret;
0451 
0452     value = ioread32(host->ioaddr + base);
0453     ret = esdhc_writew_fixup(host, reg, val, value);
0454     if (reg != SDHCI_TRANSFER_MODE)
0455         iowrite32(ret, host->ioaddr + base);
0456 
0457     /* Starting SW tuning requires ESDHC_SMPCLKSEL to be set
0458      * 1us later after ESDHC_EXTN is set.
0459      */
0460     if (base == ESDHC_SYSTEM_CONTROL_2) {
0461         if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) &&
0462             esdhc->in_sw_tuning) {
0463             udelay(1);
0464             ret |= ESDHC_SMPCLKSEL;
0465             iowrite32(ret, host->ioaddr + base);
0466         }
0467     }
0468 }
0469 
0470 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
0471 {
0472     int base = reg & ~0x3;
0473     u32 value;
0474     u32 ret;
0475 
0476     value = ioread32be(host->ioaddr + base);
0477     ret = esdhc_writeb_fixup(host, reg, val, value);
0478     iowrite32be(ret, host->ioaddr + base);
0479 }
0480 
0481 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
0482 {
0483     int base = reg & ~0x3;
0484     u32 value;
0485     u32 ret;
0486 
0487     value = ioread32(host->ioaddr + base);
0488     ret = esdhc_writeb_fixup(host, reg, val, value);
0489     iowrite32(ret, host->ioaddr + base);
0490 }
0491 
0492 /*
0493  * For Abort or Suspend after Stop at Block Gap, ignore the ADMA
0494  * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
0495  * and Block Gap Event(IRQSTAT[BGE]) are also set.
0496  * For Continue, apply soft reset for data(SYSCTL[RSTD]);
0497  * and re-issue the entire read transaction from beginning.
0498  */
0499 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
0500 {
0501     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0502     struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
0503     bool applicable;
0504     dma_addr_t dmastart;
0505     dma_addr_t dmanow;
0506 
0507     applicable = (intmask & SDHCI_INT_DATA_END) &&
0508              (intmask & SDHCI_INT_BLK_GAP) &&
0509              (esdhc->vendor_ver == VENDOR_V_23);
0510     if (!applicable)
0511         return;
0512 
0513     host->data->error = 0;
0514     dmastart = sg_dma_address(host->data->sg);
0515     dmanow = dmastart + host->data->bytes_xfered;
0516     /*
0517      * Force update to the next DMA block boundary.
0518      */
0519     dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
0520         SDHCI_DEFAULT_BOUNDARY_SIZE;
0521     host->data->bytes_xfered = dmanow - dmastart;
0522     sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
0523 }
0524 
0525 static int esdhc_of_enable_dma(struct sdhci_host *host)
0526 {
0527     int ret;
0528     u32 value;
0529     struct device *dev = mmc_dev(host->mmc);
0530 
0531     if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") ||
0532         of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) {
0533         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
0534         if (ret)
0535             return ret;
0536     }
0537 
0538     value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
0539 
0540     if (of_dma_is_coherent(dev->of_node))
0541         value |= ESDHC_DMA_SNOOP;
0542     else
0543         value &= ~ESDHC_DMA_SNOOP;
0544 
0545     sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
0546     return 0;
0547 }
0548 
0549 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
0550 {
0551     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0552     struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
0553 
0554     if (esdhc->peripheral_clock)
0555         return esdhc->peripheral_clock;
0556     else
0557         return pltfm_host->clock;
0558 }
0559 
0560 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
0561 {
0562     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0563     struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
0564     unsigned int clock;
0565 
0566     if (esdhc->peripheral_clock)
0567         clock = esdhc->peripheral_clock;
0568     else
0569         clock = pltfm_host->clock;
0570     return clock / 256 / 16;
0571 }
0572 
0573 static void esdhc_clock_enable(struct sdhci_host *host, bool enable)
0574 {
0575     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0576     struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
0577     ktime_t timeout;
0578     u32 val, clk_en;
0579 
0580     clk_en = ESDHC_CLOCK_SDCLKEN;
0581 
0582     /*
0583      * IPGEN/HCKEN/PEREN bits exist on eSDHC whose vendor version
0584      * is 2.2 or lower.
0585      */
0586     if (esdhc->vendor_ver <= VENDOR_V_22)
0587         clk_en |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
0588                ESDHC_CLOCK_PEREN);
0589 
0590     val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
0591 
0592     if (enable)
0593         val |= clk_en;
0594     else
0595         val &= ~clk_en;
0596 
0597     sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);
0598 
0599     /*
0600      * Wait max 20 ms. If vendor version is 2.2 or lower, do not
0601      * wait clock stable bit which does not exist.
0602      */
0603     timeout = ktime_add_ms(ktime_get(), 20);
0604     while (esdhc->vendor_ver > VENDOR_V_22) {
0605         bool timedout = ktime_after(ktime_get(), timeout);
0606 
0607         if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
0608             break;
0609         if (timedout) {
0610             pr_err("%s: Internal clock never stabilised.\n",
0611                 mmc_hostname(host->mmc));
0612             break;
0613         }
0614         usleep_range(10, 20);
0615     }
0616 }
0617 
0618 static void esdhc_flush_async_fifo(struct sdhci_host *host)
0619 {
0620     ktime_t timeout;
0621     u32 val;
0622 
0623     val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
0624     val |= ESDHC_FLUSH_ASYNC_FIFO;
0625     sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
0626 
0627     /* Wait max 20 ms */
0628     timeout = ktime_add_ms(ktime_get(), 20);
0629     while (1) {
0630         bool timedout = ktime_after(ktime_get(), timeout);
0631 
0632         if (!(sdhci_readl(host, ESDHC_DMA_SYSCTL) &
0633               ESDHC_FLUSH_ASYNC_FIFO))
0634             break;
0635         if (timedout) {
0636             pr_err("%s: flushing asynchronous FIFO timeout.\n",
0637                 mmc_hostname(host->mmc));
0638             break;
0639         }
0640         usleep_range(10, 20);
0641     }
0642 }
0643 
0644 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
0645 {
0646     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0647     struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
0648     unsigned int pre_div = 1, div = 1;
0649     unsigned int clock_fixup = 0;
0650     ktime_t timeout;
0651     u32 temp;
0652 
0653     if (clock == 0) {
0654         host->mmc->actual_clock = 0;
0655         esdhc_clock_enable(host, false);
0656         return;
0657     }
0658 
0659     /* Start pre_div at 2 for vendor version < 2.3. */
0660     if (esdhc->vendor_ver < VENDOR_V_23)
0661         pre_div = 2;
0662 
0663     /* Fix clock value. */
0664     if (host->mmc->card && mmc_card_sd(host->mmc->card) &&
0665         esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY)
0666         clock_fixup = esdhc->clk_fixup->sd_dflt_max_clk;
0667     else if (esdhc->clk_fixup)
0668         clock_fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];
0669 
0670     if (clock_fixup == 0 || clock < clock_fixup)
0671         clock_fixup = clock;
0672 
0673     /* Calculate pre_div and div. */
0674     while (host->max_clk / pre_div / 16 > clock_fixup && pre_div < 256)
0675         pre_div *= 2;
0676 
0677     while (host->max_clk / pre_div / div > clock_fixup && div < 16)
0678         div++;
0679 
0680     esdhc->div_ratio = pre_div * div;
0681 
0682     /* Limit clock division for HS400 200MHz clock for quirk. */
0683     if (esdhc->quirk_limited_clk_division &&
0684         clock == MMC_HS200_MAX_DTR &&
0685         (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 ||
0686          host->flags & SDHCI_HS400_TUNING)) {
0687         if (esdhc->div_ratio <= 4) {
0688             pre_div = 4;
0689             div = 1;
0690         } else if (esdhc->div_ratio <= 8) {
0691             pre_div = 4;
0692             div = 2;
0693         } else if (esdhc->div_ratio <= 12) {
0694             pre_div = 4;
0695             div = 3;
0696         } else {
0697             pr_warn("%s: using unsupported clock division.\n",
0698                 mmc_hostname(host->mmc));
0699         }
0700         esdhc->div_ratio = pre_div * div;
0701     }
0702 
0703     host->mmc->actual_clock = host->max_clk / esdhc->div_ratio;
0704 
0705     dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
0706         clock, host->mmc->actual_clock);
0707 
0708     /* Set clock division into register. */
0709     pre_div >>= 1;
0710     div--;
0711 
0712     esdhc_clock_enable(host, false);
0713 
0714     temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
0715     temp &= ~ESDHC_CLOCK_MASK;
0716     temp |= ((div << ESDHC_DIVIDER_SHIFT) |
0717         (pre_div << ESDHC_PREDIV_SHIFT));
0718     sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
0719 
0720     /*
0721      * Wait max 20 ms. If vendor version is 2.2 or lower, do not
0722      * wait clock stable bit which does not exist.
0723      */
0724     timeout = ktime_add_ms(ktime_get(), 20);
0725     while (esdhc->vendor_ver > VENDOR_V_22) {
0726         bool timedout = ktime_after(ktime_get(), timeout);
0727 
0728         if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
0729             break;
0730         if (timedout) {
0731             pr_err("%s: Internal clock never stabilised.\n",
0732                 mmc_hostname(host->mmc));
0733             break;
0734         }
0735         usleep_range(10, 20);
0736     }
0737 
0738     /* Additional setting for HS400. */
0739     if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
0740         clock == MMC_HS200_MAX_DTR) {
0741         temp = sdhci_readl(host, ESDHC_TBCTL);
0742         sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL);
0743         temp = sdhci_readl(host, ESDHC_SDCLKCTL);
0744         sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL);
0745         esdhc_clock_enable(host, true);
0746 
0747         temp = sdhci_readl(host, ESDHC_DLLCFG0);
0748         temp |= ESDHC_DLL_ENABLE;
0749         if (host->mmc->actual_clock == MMC_HS200_MAX_DTR)
0750             temp |= ESDHC_DLL_FREQ_SEL;
0751         sdhci_writel(host, temp, ESDHC_DLLCFG0);
0752 
0753         temp |= ESDHC_DLL_RESET;
0754         sdhci_writel(host, temp, ESDHC_DLLCFG0);
0755         udelay(1);
0756         temp &= ~ESDHC_DLL_RESET;
0757         sdhci_writel(host, temp, ESDHC_DLLCFG0);
0758 
0759         /* Wait max 20 ms */
0760         if (read_poll_timeout(sdhci_readl, temp,
0761                       temp & ESDHC_DLL_STS_SLV_LOCK,
0762                       10, 20000, false,
0763                       host, ESDHC_DLLSTAT0))
0764             pr_err("%s: timeout for delay chain lock.\n",
0765                    mmc_hostname(host->mmc));
0766 
0767         temp = sdhci_readl(host, ESDHC_TBCTL);
0768         sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL);
0769 
0770         esdhc_clock_enable(host, false);
0771         esdhc_flush_async_fifo(host);
0772     }
0773     esdhc_clock_enable(host, true);
0774 }
0775 
0776 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
0777 {
0778     u32 ctrl;
0779 
0780     ctrl = sdhci_readl(host, ESDHC_PROCTL);
0781     ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK);
0782     switch (width) {
0783     case MMC_BUS_WIDTH_8:
0784         ctrl |= ESDHC_CTRL_8BITBUS;
0785         break;
0786 
0787     case MMC_BUS_WIDTH_4:
0788         ctrl |= ESDHC_CTRL_4BITBUS;
0789         break;
0790 
0791     default:
0792         break;
0793     }
0794 
0795     sdhci_writel(host, ctrl, ESDHC_PROCTL);
0796 }
0797 
0798 static void esdhc_reset(struct sdhci_host *host, u8 mask)
0799 {
0800     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0801     struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
0802     u32 val, bus_width = 0;
0803 
0804     /*
0805      * Add delay to make sure all the DMA transfers are finished
0806      * for quirk.
0807      */
0808     if (esdhc->quirk_delay_before_data_reset &&
0809         (mask & SDHCI_RESET_DATA) &&
0810         (host->flags & SDHCI_REQ_USE_DMA))
0811         mdelay(5);
0812 
0813     /*
0814      * Save bus-width for eSDHC whose vendor version is 2.2
0815      * or lower for data reset.
0816      */
0817     if ((mask & SDHCI_RESET_DATA) &&
0818         (esdhc->vendor_ver <= VENDOR_V_22)) {
0819         val = sdhci_readl(host, ESDHC_PROCTL);
0820         bus_width = val & ESDHC_CTRL_BUSWIDTH_MASK;
0821     }
0822 
0823     sdhci_reset(host, mask);
0824 
0825     /*
0826      * Restore bus-width setting and interrupt registers for eSDHC
0827      * whose vendor version is 2.2 or lower for data reset.
0828      */
0829     if ((mask & SDHCI_RESET_DATA) &&
0830         (esdhc->vendor_ver <= VENDOR_V_22)) {
0831         val = sdhci_readl(host, ESDHC_PROCTL);
0832         val &= ~ESDHC_CTRL_BUSWIDTH_MASK;
0833         val |= bus_width;
0834         sdhci_writel(host, val, ESDHC_PROCTL);
0835 
0836         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
0837         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
0838     }
0839 
0840     /*
0841      * Some bits have to be cleaned manually for eSDHC whose spec
0842      * version is higher than 3.0 for all reset.
0843      */
0844     if ((mask & SDHCI_RESET_ALL) &&
0845         (esdhc->spec_ver >= SDHCI_SPEC_300)) {
0846         val = sdhci_readl(host, ESDHC_TBCTL);
0847         val &= ~ESDHC_TB_EN;
0848         sdhci_writel(host, val, ESDHC_TBCTL);
0849 
0850         /*
0851          * Initialize eSDHC_DLLCFG1[DLL_PD_PULSE_STRETCH_SEL] to
0852          * 0 for quirk.
0853          */
0854         if (esdhc->quirk_unreliable_pulse_detection) {
0855             val = sdhci_readl(host, ESDHC_DLLCFG1);
0856             val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL;
0857             sdhci_writel(host, val, ESDHC_DLLCFG1);
0858         }
0859     }
0860 }
0861 
0862 /* The SCFG, Supplemental Configuration Unit, provides SoC specific
0863  * configuration and status registers for the device. There is a
0864  * SDHC IO VSEL control register on SCFG for some platforms. It's
0865  * used to support SDHC IO voltage switching.
0866  */
0867 static const struct of_device_id scfg_device_ids[] = {
0868     { .compatible = "fsl,t1040-scfg", },
0869     { .compatible = "fsl,ls1012a-scfg", },
0870     { .compatible = "fsl,ls1046a-scfg", },
0871     {}
0872 };
0873 
0874 /* SDHC IO VSEL control register definition */
0875 #define SCFG_SDHCIOVSELCR   0x408
0876 #define SDHCIOVSELCR_TGLEN  0x80000000
0877 #define SDHCIOVSELCR_VSELVAL    0x60000000
0878 #define SDHCIOVSELCR_SDHC_VS    0x00000001
0879 
0880 static int esdhc_signal_voltage_switch(struct mmc_host *mmc,
0881                        struct mmc_ios *ios)
0882 {
0883     struct sdhci_host *host = mmc_priv(mmc);
0884     struct device_node *scfg_node;
0885     void __iomem *scfg_base = NULL;
0886     u32 sdhciovselcr;
0887     u32 val;
0888 
0889     /*
0890      * Signal Voltage Switching is only applicable for Host Controllers
0891      * v3.00 and above.
0892      */
0893     if (host->version < SDHCI_SPEC_300)
0894         return 0;
0895 
0896     val = sdhci_readl(host, ESDHC_PROCTL);
0897 
0898     switch (ios->signal_voltage) {
0899     case MMC_SIGNAL_VOLTAGE_330:
0900         val &= ~ESDHC_VOLT_SEL;
0901         sdhci_writel(host, val, ESDHC_PROCTL);
0902         return 0;
0903     case MMC_SIGNAL_VOLTAGE_180:
0904         scfg_node = of_find_matching_node(NULL, scfg_device_ids);
0905         if (scfg_node)
0906             scfg_base = of_iomap(scfg_node, 0);
0907         of_node_put(scfg_node);
0908         if (scfg_base) {
0909             sdhciovselcr = SDHCIOVSELCR_TGLEN |
0910                        SDHCIOVSELCR_VSELVAL;
0911             iowrite32be(sdhciovselcr,
0912                 scfg_base + SCFG_SDHCIOVSELCR);
0913 
0914             val |= ESDHC_VOLT_SEL;
0915             sdhci_writel(host, val, ESDHC_PROCTL);
0916             mdelay(5);
0917 
0918             sdhciovselcr = SDHCIOVSELCR_TGLEN |
0919                        SDHCIOVSELCR_SDHC_VS;
0920             iowrite32be(sdhciovselcr,
0921                 scfg_base + SCFG_SDHCIOVSELCR);
0922             iounmap(scfg_base);
0923         } else {
0924             val |= ESDHC_VOLT_SEL;
0925             sdhci_writel(host, val, ESDHC_PROCTL);
0926         }
0927         return 0;
0928     default:
0929         return 0;
0930     }
0931 }
0932 
0933 static struct soc_device_attribute soc_tuning_erratum_type1[] = {
0934     { .family = "QorIQ T1023", },
0935     { .family = "QorIQ T1040", },
0936     { .family = "QorIQ T2080", },
0937     { .family = "QorIQ LS1021A", },
0938     { /* sentinel */ }
0939 };
0940 
0941 static struct soc_device_attribute soc_tuning_erratum_type2[] = {
0942     { .family = "QorIQ LS1012A", },
0943     { .family = "QorIQ LS1043A", },
0944     { .family = "QorIQ LS1046A", },
0945     { .family = "QorIQ LS1080A", },
0946     { .family = "QorIQ LS2080A", },
0947     { .family = "QorIQ LA1575A", },
0948     { /* sentinel */ }
0949 };
0950 
0951 static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable)
0952 {
0953     u32 val;
0954 
0955     esdhc_clock_enable(host, false);
0956     esdhc_flush_async_fifo(host);
0957 
0958     val = sdhci_readl(host, ESDHC_TBCTL);
0959     if (enable)
0960         val |= ESDHC_TB_EN;
0961     else
0962         val &= ~ESDHC_TB_EN;
0963     sdhci_writel(host, val, ESDHC_TBCTL);
0964 
0965     esdhc_clock_enable(host, true);
0966 }
0967 
0968 static void esdhc_tuning_window_ptr(struct sdhci_host *host, u8 *window_start,
0969                     u8 *window_end)
0970 {
0971     u32 val;
0972 
0973     /* Write TBCTL[11:8]=4'h8 */
0974     val = sdhci_readl(host, ESDHC_TBCTL);
0975     val &= ~(0xf << 8);
0976     val |= 8 << 8;
0977     sdhci_writel(host, val, ESDHC_TBCTL);
0978 
0979     mdelay(1);
0980 
0981     /* Read TBCTL[31:0] register and rewrite again */
0982     val = sdhci_readl(host, ESDHC_TBCTL);
0983     sdhci_writel(host, val, ESDHC_TBCTL);
0984 
0985     mdelay(1);
0986 
0987     /* Read the TBSTAT[31:0] register twice */
0988     val = sdhci_readl(host, ESDHC_TBSTAT);
0989     val = sdhci_readl(host, ESDHC_TBSTAT);
0990 
0991     *window_end = val & 0xff;
0992     *window_start = (val >> 8) & 0xff;
0993 }
0994 
0995 static void esdhc_prepare_sw_tuning(struct sdhci_host *host, u8 *window_start,
0996                     u8 *window_end)
0997 {
0998     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0999     struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
1000     u8 start_ptr, end_ptr;
1001 
1002     if (esdhc->quirk_tuning_erratum_type1) {
1003         *window_start = 5 * esdhc->div_ratio;
1004         *window_end = 3 * esdhc->div_ratio;
1005         return;
1006     }
1007 
1008     esdhc_tuning_window_ptr(host, &start_ptr, &end_ptr);
1009 
1010     /* Reset data lines by setting ESDHCCTL[RSTD] */
1011     sdhci_reset(host, SDHCI_RESET_DATA);
1012     /* Write 32'hFFFF_FFFF to IRQSTAT register */
1013     sdhci_writel(host, 0xFFFFFFFF, SDHCI_INT_STATUS);
1014 
1015     /* If TBSTAT[15:8]-TBSTAT[7:0] > (4 * div_ratio) + 2
1016      * or TBSTAT[7:0]-TBSTAT[15:8] > (4 * div_ratio) + 2,
1017      * then program TBPTR[TB_WNDW_END_PTR] = 4 * div_ratio
1018      * and program TBPTR[TB_WNDW_START_PTR] = 8 * div_ratio.
1019      */
1020 
1021     if (abs(start_ptr - end_ptr) > (4 * esdhc->div_ratio + 2)) {
1022         *window_start = 8 * esdhc->div_ratio;
1023         *window_end = 4 * esdhc->div_ratio;
1024     } else {
1025         *window_start = 5 * esdhc->div_ratio;
1026         *window_end = 3 * esdhc->div_ratio;
1027     }
1028 }
1029 
1030 static int esdhc_execute_sw_tuning(struct mmc_host *mmc, u32 opcode,
1031                    u8 window_start, u8 window_end)
1032 {
1033     struct sdhci_host *host = mmc_priv(mmc);
1034     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1035     struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
1036     u32 val;
1037     int ret;
1038 
1039     /* Program TBPTR[TB_WNDW_END_PTR] and TBPTR[TB_WNDW_START_PTR] */
1040     val = ((u32)window_start << ESDHC_WNDW_STRT_PTR_SHIFT) &
1041           ESDHC_WNDW_STRT_PTR_MASK;
1042     val |= window_end & ESDHC_WNDW_END_PTR_MASK;
1043     sdhci_writel(host, val, ESDHC_TBPTR);
1044 
1045     /* Program the software tuning mode by setting TBCTL[TB_MODE]=2'h3 */
1046     val = sdhci_readl(host, ESDHC_TBCTL);
1047     val &= ~ESDHC_TB_MODE_MASK;
1048     val |= ESDHC_TB_MODE_SW;
1049     sdhci_writel(host, val, ESDHC_TBCTL);
1050 
1051     esdhc->in_sw_tuning = true;
1052     ret = sdhci_execute_tuning(mmc, opcode);
1053     esdhc->in_sw_tuning = false;
1054     return ret;
1055 }
1056 
1057 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1058 {
1059     struct sdhci_host *host = mmc_priv(mmc);
1060     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1061     struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
1062     u8 window_start, window_end;
1063     int ret, retries = 1;
1064     bool hs400_tuning;
1065     unsigned int clk;
1066     u32 val;
1067 
1068     /* For tuning mode, the sd clock divisor value
1069      * must be larger than 3 according to reference manual.
1070      */
1071     clk = esdhc->peripheral_clock / 3;
1072     if (host->clock > clk)
1073         esdhc_of_set_clock(host, clk);
1074 
1075     esdhc_tuning_block_enable(host, true);
1076 
1077     /*
1078      * The eSDHC controller takes the data timeout value into account
1079      * during tuning. If the SD card is too slow sending the response, the
1080      * timer will expire and a "Buffer Read Ready" interrupt without data
1081      * is triggered. This leads to tuning errors.
1082      *
1083      * Just set the timeout to the maximum value because the core will
1084      * already take care of it in sdhci_send_tuning().
1085      */
1086     sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
1087 
1088     hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1089 
1090     do {
1091         if (esdhc->quirk_limited_clk_division &&
1092             hs400_tuning)
1093             esdhc_of_set_clock(host, host->clock);
1094 
1095         /* Do HW tuning */
1096         val = sdhci_readl(host, ESDHC_TBCTL);
1097         val &= ~ESDHC_TB_MODE_MASK;
1098         val |= ESDHC_TB_MODE_3;
1099         sdhci_writel(host, val, ESDHC_TBCTL);
1100 
1101         ret = sdhci_execute_tuning(mmc, opcode);
1102         if (ret)
1103             break;
1104 
1105         /* For type2 affected platforms of the tuning erratum,
1106          * tuning may succeed although eSDHC might not have
1107          * tuned properly. Need to check tuning window.
1108          */
1109         if (esdhc->quirk_tuning_erratum_type2 &&
1110             !host->tuning_err) {
1111             esdhc_tuning_window_ptr(host, &window_start,
1112                         &window_end);
1113             if (abs(window_start - window_end) >
1114                 (4 * esdhc->div_ratio + 2))
1115                 host->tuning_err = -EAGAIN;
1116         }
1117 
1118         /* If HW tuning fails and triggers erratum,
1119          * try workaround.
1120          */
1121         ret = host->tuning_err;
1122         if (ret == -EAGAIN &&
1123             (esdhc->quirk_tuning_erratum_type1 ||
1124              esdhc->quirk_tuning_erratum_type2)) {
1125             /* Recover HS400 tuning flag */
1126             if (hs400_tuning)
1127                 host->flags |= SDHCI_HS400_TUNING;
1128             pr_info("%s: Hold on to use fixed sampling clock. Try SW tuning!\n",
1129                 mmc_hostname(mmc));
1130             /* Do SW tuning */
1131             esdhc_prepare_sw_tuning(host, &window_start,
1132                         &window_end);
1133             ret = esdhc_execute_sw_tuning(mmc, opcode,
1134                               window_start,
1135                               window_end);
1136             if (ret)
1137                 break;
1138 
1139             /* Retry both HW/SW tuning with reduced clock. */
1140             ret = host->tuning_err;
1141             if (ret == -EAGAIN && retries) {
1142                 /* Recover HS400 tuning flag */
1143                 if (hs400_tuning)
1144                     host->flags |= SDHCI_HS400_TUNING;
1145 
1146                 clk = host->max_clk / (esdhc->div_ratio + 1);
1147                 esdhc_of_set_clock(host, clk);
1148                 pr_info("%s: Hold on to use fixed sampling clock. Try tuning with reduced clock!\n",
1149                     mmc_hostname(mmc));
1150             } else {
1151                 break;
1152             }
1153         } else {
1154             break;
1155         }
1156     } while (retries--);
1157 
1158     if (ret) {
1159         esdhc_tuning_block_enable(host, false);
1160     } else if (hs400_tuning) {
1161         val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
1162         val |= ESDHC_FLW_CTL_BG;
1163         sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
1164     }
1165 
1166     return ret;
1167 }
1168 
1169 static void esdhc_set_uhs_signaling(struct sdhci_host *host,
1170                    unsigned int timing)
1171 {
1172     u32 val;
1173 
1174     /*
1175      * There are specific registers setting for HS400 mode.
1176      * Clean all of them if controller is in HS400 mode to
1177      * exit HS400 mode before re-setting any speed mode.
1178      */
1179     val = sdhci_readl(host, ESDHC_TBCTL);
1180     if (val & ESDHC_HS400_MODE) {
1181         val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
1182         val &= ~ESDHC_FLW_CTL_BG;
1183         sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
1184 
1185         val = sdhci_readl(host, ESDHC_SDCLKCTL);
1186         val &= ~ESDHC_CMD_CLK_CTL;
1187         sdhci_writel(host, val, ESDHC_SDCLKCTL);
1188 
1189         esdhc_clock_enable(host, false);
1190         val = sdhci_readl(host, ESDHC_TBCTL);
1191         val &= ~ESDHC_HS400_MODE;
1192         sdhci_writel(host, val, ESDHC_TBCTL);
1193         esdhc_clock_enable(host, true);
1194 
1195         val = sdhci_readl(host, ESDHC_DLLCFG0);
1196         val &= ~(ESDHC_DLL_ENABLE | ESDHC_DLL_FREQ_SEL);
1197         sdhci_writel(host, val, ESDHC_DLLCFG0);
1198 
1199         val = sdhci_readl(host, ESDHC_TBCTL);
1200         val &= ~ESDHC_HS400_WNDW_ADJUST;
1201         sdhci_writel(host, val, ESDHC_TBCTL);
1202 
1203         esdhc_tuning_block_enable(host, false);
1204     }
1205 
1206     if (timing == MMC_TIMING_MMC_HS400)
1207         esdhc_tuning_block_enable(host, true);
1208     else
1209         sdhci_set_uhs_signaling(host, timing);
1210 }
1211 
1212 static u32 esdhc_irq(struct sdhci_host *host, u32 intmask)
1213 {
1214     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1215     struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
1216     u32 command;
1217 
1218     if (esdhc->quirk_trans_complete_erratum) {
1219         command = SDHCI_GET_CMD(sdhci_readw(host,
1220                     SDHCI_COMMAND));
1221         if (command == MMC_WRITE_MULTIPLE_BLOCK &&
1222                 sdhci_readw(host, SDHCI_BLOCK_COUNT) &&
1223                 intmask & SDHCI_INT_DATA_END) {
1224             intmask &= ~SDHCI_INT_DATA_END;
1225             sdhci_writel(host, SDHCI_INT_DATA_END,
1226                     SDHCI_INT_STATUS);
1227         }
1228     }
1229     return intmask;
1230 }
1231 
1232 #ifdef CONFIG_PM_SLEEP
1233 static u32 esdhc_proctl;
1234 static int esdhc_of_suspend(struct device *dev)
1235 {
1236     struct sdhci_host *host = dev_get_drvdata(dev);
1237 
1238     esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
1239 
1240     if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1241         mmc_retune_needed(host->mmc);
1242 
1243     return sdhci_suspend_host(host);
1244 }
1245 
1246 static int esdhc_of_resume(struct device *dev)
1247 {
1248     struct sdhci_host *host = dev_get_drvdata(dev);
1249     int ret = sdhci_resume_host(host);
1250 
1251     if (ret == 0) {
1252         /* Isn't this already done by sdhci_resume_host() ? --rmk */
1253         esdhc_of_enable_dma(host);
1254         sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
1255     }
1256     return ret;
1257 }
1258 #endif
1259 
1260 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops,
1261             esdhc_of_suspend,
1262             esdhc_of_resume);
1263 
1264 static const struct sdhci_ops sdhci_esdhc_be_ops = {
1265     .read_l = esdhc_be_readl,
1266     .read_w = esdhc_be_readw,
1267     .read_b = esdhc_be_readb,
1268     .write_l = esdhc_be_writel,
1269     .write_w = esdhc_be_writew,
1270     .write_b = esdhc_be_writeb,
1271     .set_clock = esdhc_of_set_clock,
1272     .enable_dma = esdhc_of_enable_dma,
1273     .get_max_clock = esdhc_of_get_max_clock,
1274     .get_min_clock = esdhc_of_get_min_clock,
1275     .adma_workaround = esdhc_of_adma_workaround,
1276     .set_bus_width = esdhc_pltfm_set_bus_width,
1277     .reset = esdhc_reset,
1278     .set_uhs_signaling = esdhc_set_uhs_signaling,
1279     .irq = esdhc_irq,
1280 };
1281 
1282 static const struct sdhci_ops sdhci_esdhc_le_ops = {
1283     .read_l = esdhc_le_readl,
1284     .read_w = esdhc_le_readw,
1285     .read_b = esdhc_le_readb,
1286     .write_l = esdhc_le_writel,
1287     .write_w = esdhc_le_writew,
1288     .write_b = esdhc_le_writeb,
1289     .set_clock = esdhc_of_set_clock,
1290     .enable_dma = esdhc_of_enable_dma,
1291     .get_max_clock = esdhc_of_get_max_clock,
1292     .get_min_clock = esdhc_of_get_min_clock,
1293     .adma_workaround = esdhc_of_adma_workaround,
1294     .set_bus_width = esdhc_pltfm_set_bus_width,
1295     .reset = esdhc_reset,
1296     .set_uhs_signaling = esdhc_set_uhs_signaling,
1297     .irq = esdhc_irq,
1298 };
1299 
1300 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
1301     .quirks = ESDHC_DEFAULT_QUIRKS |
1302 #ifdef CONFIG_PPC
1303           SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1304 #endif
1305           SDHCI_QUIRK_NO_CARD_NO_RESET |
1306           SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1307     .ops = &sdhci_esdhc_be_ops,
1308 };
1309 
1310 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
1311     .quirks = ESDHC_DEFAULT_QUIRKS |
1312           SDHCI_QUIRK_NO_CARD_NO_RESET |
1313           SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1314     .ops = &sdhci_esdhc_le_ops,
1315 };
1316 
1317 static struct soc_device_attribute soc_incorrect_hostver[] = {
1318     { .family = "QorIQ T4240", .revision = "1.0", },
1319     { .family = "QorIQ T4240", .revision = "2.0", },
1320     { /* sentinel */ }
1321 };
1322 
1323 static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = {
1324     { .family = "QorIQ LX2160A", .revision = "1.0", },
1325     { .family = "QorIQ LX2160A", .revision = "2.0", },
1326     { .family = "QorIQ LS1028A", .revision = "1.0", },
1327     { /* sentinel */ }
1328 };
1329 
1330 static struct soc_device_attribute soc_unreliable_pulse_detection[] = {
1331     { .family = "QorIQ LX2160A", .revision = "1.0", },
1332     { .family = "QorIQ LX2160A", .revision = "2.0", },
1333     { .family = "QorIQ LS1028A", .revision = "1.0", },
1334     { /* sentinel */ }
1335 };
1336 
1337 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
1338 {
1339     const struct of_device_id *match;
1340     struct sdhci_pltfm_host *pltfm_host;
1341     struct sdhci_esdhc *esdhc;
1342     struct device_node *np;
1343     struct clk *clk;
1344     u32 val;
1345     u16 host_ver;
1346 
1347     pltfm_host = sdhci_priv(host);
1348     esdhc = sdhci_pltfm_priv(pltfm_host);
1349 
1350     host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
1351     esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
1352                  SDHCI_VENDOR_VER_SHIFT;
1353     esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
1354     if (soc_device_match(soc_incorrect_hostver))
1355         esdhc->quirk_incorrect_hostver = true;
1356     else
1357         esdhc->quirk_incorrect_hostver = false;
1358 
1359     if (soc_device_match(soc_fixup_sdhc_clkdivs))
1360         esdhc->quirk_limited_clk_division = true;
1361     else
1362         esdhc->quirk_limited_clk_division = false;
1363 
1364     if (soc_device_match(soc_unreliable_pulse_detection))
1365         esdhc->quirk_unreliable_pulse_detection = true;
1366     else
1367         esdhc->quirk_unreliable_pulse_detection = false;
1368 
1369     match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node);
1370     if (match)
1371         esdhc->clk_fixup = match->data;
1372     np = pdev->dev.of_node;
1373 
1374     if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
1375         esdhc->quirk_delay_before_data_reset = true;
1376         esdhc->quirk_trans_complete_erratum = true;
1377     }
1378 
1379     clk = of_clk_get(np, 0);
1380     if (!IS_ERR(clk)) {
1381         /*
1382          * esdhc->peripheral_clock would be assigned with a value
1383          * which is eSDHC base clock when use periperal clock.
1384          * For some platforms, the clock value got by common clk
1385          * API is peripheral clock while the eSDHC base clock is
1386          * 1/2 peripheral clock.
1387          */
1388         if (of_device_is_compatible(np, "fsl,ls1046a-esdhc") ||
1389             of_device_is_compatible(np, "fsl,ls1028a-esdhc") ||
1390             of_device_is_compatible(np, "fsl,ls1088a-esdhc"))
1391             esdhc->peripheral_clock = clk_get_rate(clk) / 2;
1392         else
1393             esdhc->peripheral_clock = clk_get_rate(clk);
1394 
1395         clk_put(clk);
1396     }
1397 
1398     esdhc_clock_enable(host, false);
1399     val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
1400     /*
1401      * This bit is not able to be reset by SDHCI_RESET_ALL. Need to
1402      * initialize it as 1 or 0 once, to override the different value
1403      * which may be configured in bootloader.
1404      */
1405     if (esdhc->peripheral_clock)
1406         val |= ESDHC_PERIPHERAL_CLK_SEL;
1407     else
1408         val &= ~ESDHC_PERIPHERAL_CLK_SEL;
1409     sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
1410     esdhc_clock_enable(host, true);
1411 }
1412 
1413 static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc)
1414 {
1415     esdhc_tuning_block_enable(mmc_priv(mmc), false);
1416     return 0;
1417 }
1418 
1419 static int sdhci_esdhc_probe(struct platform_device *pdev)
1420 {
1421     struct sdhci_host *host;
1422     struct device_node *np, *tp;
1423     struct sdhci_pltfm_host *pltfm_host;
1424     struct sdhci_esdhc *esdhc;
1425     int ret;
1426 
1427     np = pdev->dev.of_node;
1428 
1429     if (of_property_read_bool(np, "little-endian"))
1430         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata,
1431                     sizeof(struct sdhci_esdhc));
1432     else
1433         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata,
1434                     sizeof(struct sdhci_esdhc));
1435 
1436     if (IS_ERR(host))
1437         return PTR_ERR(host);
1438 
1439     host->mmc_host_ops.start_signal_voltage_switch =
1440         esdhc_signal_voltage_switch;
1441     host->mmc_host_ops.execute_tuning = esdhc_execute_tuning;
1442     host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr;
1443     host->tuning_delay = 1;
1444 
1445     esdhc_init(pdev, host);
1446 
1447     sdhci_get_of_property(pdev);
1448 
1449     pltfm_host = sdhci_priv(host);
1450     esdhc = sdhci_pltfm_priv(pltfm_host);
1451     if (soc_device_match(soc_tuning_erratum_type1))
1452         esdhc->quirk_tuning_erratum_type1 = true;
1453     else
1454         esdhc->quirk_tuning_erratum_type1 = false;
1455 
1456     if (soc_device_match(soc_tuning_erratum_type2))
1457         esdhc->quirk_tuning_erratum_type2 = true;
1458     else
1459         esdhc->quirk_tuning_erratum_type2 = false;
1460 
1461     if (esdhc->vendor_ver == VENDOR_V_22)
1462         host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
1463 
1464     if (esdhc->vendor_ver > VENDOR_V_22)
1465         host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1466 
1467     tp = of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc");
1468     if (tp) {
1469         of_node_put(tp);
1470         host->quirks |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
1471         host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1472     }
1473 
1474     if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
1475         of_device_is_compatible(np, "fsl,p5020-esdhc") ||
1476         of_device_is_compatible(np, "fsl,p4080-esdhc") ||
1477         of_device_is_compatible(np, "fsl,p1020-esdhc") ||
1478         of_device_is_compatible(np, "fsl,t1040-esdhc"))
1479         host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1480 
1481     if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
1482         host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1483 
1484     esdhc->quirk_ignore_data_inhibit = false;
1485     if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
1486         /*
1487          * Freescale messed up with P2020 as it has a non-standard
1488          * host control register
1489          */
1490         host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
1491         esdhc->quirk_ignore_data_inhibit = true;
1492     }
1493 
1494     /* call to generic mmc_of_parse to support additional capabilities */
1495     ret = mmc_of_parse(host->mmc);
1496     if (ret)
1497         goto err;
1498 
1499     mmc_of_parse_voltage(host->mmc, &host->ocr_mask);
1500 
1501     ret = sdhci_add_host(host);
1502     if (ret)
1503         goto err;
1504 
1505     return 0;
1506  err:
1507     sdhci_pltfm_free(pdev);
1508     return ret;
1509 }
1510 
1511 static struct platform_driver sdhci_esdhc_driver = {
1512     .driver = {
1513         .name = "sdhci-esdhc",
1514         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1515         .of_match_table = sdhci_esdhc_of_match,
1516         .pm = &esdhc_of_dev_pm_ops,
1517     },
1518     .probe = sdhci_esdhc_probe,
1519     .remove = sdhci_pltfm_unregister,
1520 };
1521 
1522 module_platform_driver(sdhci_esdhc_driver);
1523 
1524 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
1525 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
1526           "Anton Vorontsov <avorontsov@ru.mvista.com>");
1527 MODULE_LICENSE("GPL v2");
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