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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller
0004  *
0005  * Copyright (C) 2018 Synaptics Incorporated
0006  *
0007  * Author: Jisheng Zhang <jszhang@kernel.org>
0008  */
0009 
0010 #include <linux/acpi.h>
0011 #include <linux/clk.h>
0012 #include <linux/dma-mapping.h>
0013 #include <linux/iopoll.h>
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/of.h>
0017 #include <linux/of_device.h>
0018 #include <linux/reset.h>
0019 #include <linux/sizes.h>
0020 
0021 #include "sdhci-pltfm.h"
0022 
0023 #define SDHCI_DWCMSHC_ARG2_STUFF    GENMASK(31, 16)
0024 
0025 /* DWCMSHC specific Mode Select value */
0026 #define DWCMSHC_CTRL_HS400      0x7
0027 
0028 /* DWC IP vendor area 1 pointer */
0029 #define DWCMSHC_P_VENDOR_AREA1      0xe8
0030 #define DWCMSHC_AREA1_MASK      GENMASK(11, 0)
0031 /* Offset inside the  vendor area 1 */
0032 #define DWCMSHC_HOST_CTRL3      0x8
0033 #define DWCMSHC_EMMC_CONTROL        0x2c
0034 #define DWCMSHC_CARD_IS_EMMC        BIT(0)
0035 #define DWCMSHC_ENHANCED_STROBE     BIT(8)
0036 #define DWCMSHC_EMMC_ATCTRL     0x40
0037 
0038 /* Rockchip specific Registers */
0039 #define DWCMSHC_EMMC_DLL_CTRL       0x800
0040 #define DWCMSHC_EMMC_DLL_RXCLK      0x804
0041 #define DWCMSHC_EMMC_DLL_TXCLK      0x808
0042 #define DWCMSHC_EMMC_DLL_STRBIN     0x80c
0043 #define DECMSHC_EMMC_DLL_CMDOUT     0x810
0044 #define DWCMSHC_EMMC_DLL_STATUS0    0x840
0045 #define DWCMSHC_EMMC_DLL_START      BIT(0)
0046 #define DWCMSHC_EMMC_DLL_LOCKED     BIT(8)
0047 #define DWCMSHC_EMMC_DLL_TIMEOUT    BIT(9)
0048 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL   29
0049 #define DWCMSHC_EMMC_DLL_START_POINT    16
0050 #define DWCMSHC_EMMC_DLL_INC        8
0051 #define DWCMSHC_EMMC_DLL_DLYENA     BIT(27)
0052 #define DLL_TXCLK_TAPNUM_DEFAULT    0x10
0053 #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA
0054 #define DLL_TXCLK_TAPNUM_FROM_SW    BIT(24)
0055 #define DLL_STRBIN_TAPNUM_DEFAULT   0x8
0056 #define DLL_STRBIN_TAPNUM_FROM_SW   BIT(24)
0057 #define DLL_STRBIN_DELAY_NUM_SEL    BIT(26)
0058 #define DLL_STRBIN_DELAY_NUM_OFFSET 16
0059 #define DLL_STRBIN_DELAY_NUM_DEFAULT    0x16
0060 #define DLL_RXCLK_NO_INVERTER       1
0061 #define DLL_RXCLK_INVERTER      0
0062 #define DLL_CMDOUT_TAPNUM_90_DEGREES    0x8
0063 #define DLL_CMDOUT_TAPNUM_FROM_SW   BIT(24)
0064 #define DLL_CMDOUT_SRC_CLK_NEG      BIT(28)
0065 #define DLL_CMDOUT_EN_SRC_CLK_NEG   BIT(29)
0066 
0067 #define DLL_LOCK_WO_TMOUT(x) \
0068     ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
0069     (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
0070 #define RK35xx_MAX_CLKS 3
0071 
0072 #define BOUNDARY_OK(addr, len) \
0073     ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
0074 
0075 enum dwcmshc_rk_type {
0076     DWCMSHC_RK3568,
0077     DWCMSHC_RK3588,
0078 };
0079 
0080 struct rk35xx_priv {
0081     /* Rockchip specified optional clocks */
0082     struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS];
0083     struct reset_control *reset;
0084     enum dwcmshc_rk_type devtype;
0085     u8 txclk_tapnum;
0086 };
0087 
0088 struct dwcmshc_priv {
0089     struct clk  *bus_clk;
0090     int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */
0091     void *priv; /* pointer to SoC private stuff */
0092 };
0093 
0094 /*
0095  * If DMA addr spans 128MB boundary, we split the DMA transfer into two
0096  * so that each DMA transfer doesn't exceed the boundary.
0097  */
0098 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
0099                     dma_addr_t addr, int len, unsigned int cmd)
0100 {
0101     int tmplen, offset;
0102 
0103     if (likely(!len || BOUNDARY_OK(addr, len))) {
0104         sdhci_adma_write_desc(host, desc, addr, len, cmd);
0105         return;
0106     }
0107 
0108     offset = addr & (SZ_128M - 1);
0109     tmplen = SZ_128M - offset;
0110     sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
0111 
0112     addr += tmplen;
0113     len -= tmplen;
0114     sdhci_adma_write_desc(host, desc, addr, len, cmd);
0115 }
0116 
0117 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
0118 {
0119     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0120 
0121     if (pltfm_host->clk)
0122         return sdhci_pltfm_clk_get_max_clock(host);
0123     else
0124         return pltfm_host->clock;
0125 }
0126 
0127 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
0128                      struct mmc_request *mrq)
0129 {
0130     struct sdhci_host *host = mmc_priv(mmc);
0131 
0132     /*
0133      * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit
0134      * block count register which doesn't support stuff bits of
0135      * CMD23 argument on dwcmsch host controller.
0136      */
0137     if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF))
0138         host->flags &= ~SDHCI_AUTO_CMD23;
0139     else
0140         host->flags |= SDHCI_AUTO_CMD23;
0141 }
0142 
0143 static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq)
0144 {
0145     dwcmshc_check_auto_cmd23(mmc, mrq);
0146 
0147     sdhci_request(mmc, mrq);
0148 }
0149 
0150 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
0151                       unsigned int timing)
0152 {
0153     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0154     struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
0155     u16 ctrl, ctrl_2;
0156 
0157     ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
0158     /* Select Bus Speed Mode for host */
0159     ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
0160     if ((timing == MMC_TIMING_MMC_HS200) ||
0161         (timing == MMC_TIMING_UHS_SDR104))
0162         ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
0163     else if (timing == MMC_TIMING_UHS_SDR12)
0164         ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
0165     else if ((timing == MMC_TIMING_UHS_SDR25) ||
0166          (timing == MMC_TIMING_MMC_HS))
0167         ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
0168     else if (timing == MMC_TIMING_UHS_SDR50)
0169         ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
0170     else if ((timing == MMC_TIMING_UHS_DDR50) ||
0171          (timing == MMC_TIMING_MMC_DDR52))
0172         ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
0173     else if (timing == MMC_TIMING_MMC_HS400) {
0174         /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
0175         ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
0176         ctrl |= DWCMSHC_CARD_IS_EMMC;
0177         sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
0178 
0179         ctrl_2 |= DWCMSHC_CTRL_HS400;
0180     }
0181 
0182     sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
0183 }
0184 
0185 static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc,
0186                       struct mmc_ios *ios)
0187 {
0188     u32 vendor;
0189     struct sdhci_host *host = mmc_priv(mmc);
0190     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0191     struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
0192     int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL;
0193 
0194     vendor = sdhci_readl(host, reg);
0195     if (ios->enhanced_strobe)
0196         vendor |= DWCMSHC_ENHANCED_STROBE;
0197     else
0198         vendor &= ~DWCMSHC_ENHANCED_STROBE;
0199 
0200     sdhci_writel(host, vendor, reg);
0201 }
0202 
0203 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
0204 {
0205     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0206     struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
0207     struct rk35xx_priv *priv = dwc_priv->priv;
0208     u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
0209     u32 extra, reg;
0210     int err;
0211 
0212     host->mmc->actual_clock = 0;
0213 
0214     if (clock == 0) {
0215         /* Disable interface clock at initial state. */
0216         sdhci_set_clock(host, clock);
0217         return;
0218     }
0219 
0220     /* Rockchip platform only support 375KHz for identify mode */
0221     if (clock <= 400000)
0222         clock = 375000;
0223 
0224     err = clk_set_rate(pltfm_host->clk, clock);
0225     if (err)
0226         dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
0227 
0228     sdhci_set_clock(host, clock);
0229 
0230     /* Disable cmd conflict check */
0231     reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
0232     extra = sdhci_readl(host, reg);
0233     extra &= ~BIT(0);
0234     sdhci_writel(host, extra, reg);
0235 
0236     if (clock <= 52000000) {
0237         /* Disable DLL and reset both of sample and drive clock */
0238         sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
0239         sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK);
0240         sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
0241         sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
0242         /*
0243          * Before switching to hs400es mode, the driver will enable
0244          * enhanced strobe first. PHY needs to configure the parameters
0245          * of enhanced strobe first.
0246          */
0247         extra = DWCMSHC_EMMC_DLL_DLYENA |
0248             DLL_STRBIN_DELAY_NUM_SEL |
0249             DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
0250         sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
0251         return;
0252     }
0253 
0254     /* Reset DLL */
0255     sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
0256     udelay(1);
0257     sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
0258 
0259     /*
0260      * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but
0261      * we must set it in higher speed mode.
0262      */
0263     extra = DWCMSHC_EMMC_DLL_DLYENA;
0264     if (priv->devtype == DWCMSHC_RK3568)
0265         extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
0266     sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
0267 
0268     /* Init DLL settings */
0269     extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT |
0270         0x2 << DWCMSHC_EMMC_DLL_INC |
0271         DWCMSHC_EMMC_DLL_START;
0272     sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
0273     err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
0274                  extra, DLL_LOCK_WO_TMOUT(extra), 1,
0275                  500 * USEC_PER_MSEC);
0276     if (err) {
0277         dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
0278         return;
0279     }
0280 
0281     extra = 0x1 << 16 | /* tune clock stop en */
0282         0x2 << 17 | /* pre-change delay */
0283         0x3 << 19;  /* post-change delay */
0284     sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
0285 
0286     if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
0287         host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
0288         txclk_tapnum = priv->txclk_tapnum;
0289 
0290     if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
0291         txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES;
0292 
0293         extra = DLL_CMDOUT_SRC_CLK_NEG |
0294             DLL_CMDOUT_EN_SRC_CLK_NEG |
0295             DWCMSHC_EMMC_DLL_DLYENA |
0296             DLL_CMDOUT_TAPNUM_90_DEGREES |
0297             DLL_CMDOUT_TAPNUM_FROM_SW;
0298         sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
0299     }
0300 
0301     extra = DWCMSHC_EMMC_DLL_DLYENA |
0302         DLL_TXCLK_TAPNUM_FROM_SW |
0303         DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL |
0304         txclk_tapnum;
0305     sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
0306 
0307     extra = DWCMSHC_EMMC_DLL_DLYENA |
0308         DLL_STRBIN_TAPNUM_DEFAULT |
0309         DLL_STRBIN_TAPNUM_FROM_SW;
0310     sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
0311 }
0312 
0313 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
0314 {
0315     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0316     struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
0317     struct rk35xx_priv *priv = dwc_priv->priv;
0318 
0319     if (mask & SDHCI_RESET_ALL && priv->reset) {
0320         reset_control_assert(priv->reset);
0321         udelay(1);
0322         reset_control_deassert(priv->reset);
0323     }
0324 
0325     sdhci_reset(host, mask);
0326 }
0327 
0328 static const struct sdhci_ops sdhci_dwcmshc_ops = {
0329     .set_clock      = sdhci_set_clock,
0330     .set_bus_width      = sdhci_set_bus_width,
0331     .set_uhs_signaling  = dwcmshc_set_uhs_signaling,
0332     .get_max_clock      = dwcmshc_get_max_clock,
0333     .reset          = sdhci_reset,
0334     .adma_write_desc    = dwcmshc_adma_write_desc,
0335 };
0336 
0337 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {
0338     .set_clock      = dwcmshc_rk3568_set_clock,
0339     .set_bus_width      = sdhci_set_bus_width,
0340     .set_uhs_signaling  = dwcmshc_set_uhs_signaling,
0341     .get_max_clock      = sdhci_pltfm_clk_get_max_clock,
0342     .reset          = rk35xx_sdhci_reset,
0343     .adma_write_desc    = dwcmshc_adma_write_desc,
0344 };
0345 
0346 static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
0347     .ops = &sdhci_dwcmshc_ops,
0348     .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
0349     .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
0350 };
0351 
0352 #ifdef CONFIG_ACPI
0353 static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = {
0354     .ops = &sdhci_dwcmshc_ops,
0355     .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
0356     .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
0357            SDHCI_QUIRK2_ACMD23_BROKEN,
0358 };
0359 #endif
0360 
0361 static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {
0362     .ops = &sdhci_dwcmshc_rk35xx_ops,
0363     .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
0364           SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
0365     .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
0366            SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
0367 };
0368 
0369 static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
0370 {
0371     int err;
0372     struct rk35xx_priv *priv = dwc_priv->priv;
0373 
0374     priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
0375     if (IS_ERR(priv->reset)) {
0376         err = PTR_ERR(priv->reset);
0377         dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
0378         return err;
0379     }
0380 
0381     priv->rockchip_clks[0].id = "axi";
0382     priv->rockchip_clks[1].id = "block";
0383     priv->rockchip_clks[2].id = "timer";
0384     err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS,
0385                      priv->rockchip_clks);
0386     if (err) {
0387         dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
0388         return err;
0389     }
0390 
0391     err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks);
0392     if (err) {
0393         dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
0394         return err;
0395     }
0396 
0397     if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
0398                 &priv->txclk_tapnum))
0399         priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
0400 
0401     /* Disable cmd conflict check */
0402     sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
0403     /* Reset previous settings */
0404     sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
0405     sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
0406 
0407     return 0;
0408 }
0409 
0410 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
0411 {
0412     /*
0413      * Don't support highspeed bus mode with low clk speed as we
0414      * cannot use DLL for this condition.
0415      */
0416     if (host->mmc->f_max <= 52000000) {
0417         dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",
0418              host->mmc->f_max);
0419         host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);
0420         host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);
0421     }
0422 }
0423 
0424 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
0425     {
0426         .compatible = "rockchip,rk3588-dwcmshc",
0427         .data = &sdhci_dwcmshc_rk35xx_pdata,
0428     },
0429     {
0430         .compatible = "rockchip,rk3568-dwcmshc",
0431         .data = &sdhci_dwcmshc_rk35xx_pdata,
0432     },
0433     {
0434         .compatible = "snps,dwcmshc-sdhci",
0435         .data = &sdhci_dwcmshc_pdata,
0436     },
0437     {},
0438 };
0439 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
0440 
0441 #ifdef CONFIG_ACPI
0442 static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {
0443     {
0444         .id = "MLNXBF30",
0445         .driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata,
0446     },
0447     {}
0448 };
0449 #endif
0450 
0451 static int dwcmshc_probe(struct platform_device *pdev)
0452 {
0453     struct device *dev = &pdev->dev;
0454     struct sdhci_pltfm_host *pltfm_host;
0455     struct sdhci_host *host;
0456     struct dwcmshc_priv *priv;
0457     struct rk35xx_priv *rk_priv = NULL;
0458     const struct sdhci_pltfm_data *pltfm_data;
0459     int err;
0460     u32 extra;
0461 
0462     pltfm_data = device_get_match_data(&pdev->dev);
0463     if (!pltfm_data) {
0464         dev_err(&pdev->dev, "Error: No device match data found\n");
0465         return -ENODEV;
0466     }
0467 
0468     host = sdhci_pltfm_init(pdev, pltfm_data,
0469                 sizeof(struct dwcmshc_priv));
0470     if (IS_ERR(host))
0471         return PTR_ERR(host);
0472 
0473     /*
0474      * extra adma table cnt for cross 128M boundary handling.
0475      */
0476     extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
0477     if (extra > SDHCI_MAX_SEGS)
0478         extra = SDHCI_MAX_SEGS;
0479     host->adma_table_cnt += extra;
0480 
0481     pltfm_host = sdhci_priv(host);
0482     priv = sdhci_pltfm_priv(pltfm_host);
0483 
0484     if (dev->of_node) {
0485         pltfm_host->clk = devm_clk_get(dev, "core");
0486         if (IS_ERR(pltfm_host->clk)) {
0487             err = PTR_ERR(pltfm_host->clk);
0488             dev_err(dev, "failed to get core clk: %d\n", err);
0489             goto free_pltfm;
0490         }
0491         err = clk_prepare_enable(pltfm_host->clk);
0492         if (err)
0493             goto free_pltfm;
0494 
0495         priv->bus_clk = devm_clk_get(dev, "bus");
0496         if (!IS_ERR(priv->bus_clk))
0497             clk_prepare_enable(priv->bus_clk);
0498     }
0499 
0500     err = mmc_of_parse(host->mmc);
0501     if (err)
0502         goto err_clk;
0503 
0504     sdhci_get_of_property(pdev);
0505 
0506     priv->vendor_specific_area1 =
0507         sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;
0508 
0509     host->mmc_host_ops.request = dwcmshc_request;
0510     host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
0511 
0512     if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) {
0513         rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL);
0514         if (!rk_priv) {
0515             err = -ENOMEM;
0516             goto err_clk;
0517         }
0518 
0519         if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc"))
0520             rk_priv->devtype = DWCMSHC_RK3588;
0521         else
0522             rk_priv->devtype = DWCMSHC_RK3568;
0523 
0524         priv->priv = rk_priv;
0525 
0526         err = dwcmshc_rk35xx_init(host, priv);
0527         if (err)
0528             goto err_clk;
0529     }
0530 
0531     host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
0532 
0533     err = sdhci_setup_host(host);
0534     if (err)
0535         goto err_clk;
0536 
0537     if (rk_priv)
0538         dwcmshc_rk35xx_postinit(host, priv);
0539 
0540     err = __sdhci_add_host(host);
0541     if (err)
0542         goto err_setup_host;
0543 
0544     return 0;
0545 
0546 err_setup_host:
0547     sdhci_cleanup_host(host);
0548 err_clk:
0549     clk_disable_unprepare(pltfm_host->clk);
0550     clk_disable_unprepare(priv->bus_clk);
0551     if (rk_priv)
0552         clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
0553                        rk_priv->rockchip_clks);
0554 free_pltfm:
0555     sdhci_pltfm_free(pdev);
0556     return err;
0557 }
0558 
0559 static int dwcmshc_remove(struct platform_device *pdev)
0560 {
0561     struct sdhci_host *host = platform_get_drvdata(pdev);
0562     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0563     struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
0564     struct rk35xx_priv *rk_priv = priv->priv;
0565 
0566     sdhci_remove_host(host, 0);
0567 
0568     clk_disable_unprepare(pltfm_host->clk);
0569     clk_disable_unprepare(priv->bus_clk);
0570     if (rk_priv)
0571         clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
0572                        rk_priv->rockchip_clks);
0573     sdhci_pltfm_free(pdev);
0574 
0575     return 0;
0576 }
0577 
0578 #ifdef CONFIG_PM_SLEEP
0579 static int dwcmshc_suspend(struct device *dev)
0580 {
0581     struct sdhci_host *host = dev_get_drvdata(dev);
0582     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0583     struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
0584     struct rk35xx_priv *rk_priv = priv->priv;
0585     int ret;
0586 
0587     ret = sdhci_suspend_host(host);
0588     if (ret)
0589         return ret;
0590 
0591     clk_disable_unprepare(pltfm_host->clk);
0592     if (!IS_ERR(priv->bus_clk))
0593         clk_disable_unprepare(priv->bus_clk);
0594 
0595     if (rk_priv)
0596         clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
0597                        rk_priv->rockchip_clks);
0598 
0599     return ret;
0600 }
0601 
0602 static int dwcmshc_resume(struct device *dev)
0603 {
0604     struct sdhci_host *host = dev_get_drvdata(dev);
0605     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0606     struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
0607     struct rk35xx_priv *rk_priv = priv->priv;
0608     int ret;
0609 
0610     ret = clk_prepare_enable(pltfm_host->clk);
0611     if (ret)
0612         return ret;
0613 
0614     if (!IS_ERR(priv->bus_clk)) {
0615         ret = clk_prepare_enable(priv->bus_clk);
0616         if (ret)
0617             return ret;
0618     }
0619 
0620     if (rk_priv) {
0621         ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS,
0622                           rk_priv->rockchip_clks);
0623         if (ret)
0624             return ret;
0625     }
0626 
0627     return sdhci_resume_host(host);
0628 }
0629 #endif
0630 
0631 static SIMPLE_DEV_PM_OPS(dwcmshc_pmops, dwcmshc_suspend, dwcmshc_resume);
0632 
0633 static struct platform_driver sdhci_dwcmshc_driver = {
0634     .driver = {
0635         .name   = "sdhci-dwcmshc",
0636         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0637         .of_match_table = sdhci_dwcmshc_dt_ids,
0638         .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
0639         .pm = &dwcmshc_pmops,
0640     },
0641     .probe  = dwcmshc_probe,
0642     .remove = dwcmshc_remove,
0643 };
0644 module_platform_driver(sdhci_dwcmshc_driver);
0645 
0646 MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC");
0647 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
0648 MODULE_LICENSE("GPL v2");
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