mmc/host/sdhci-of-at91.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Atmel SDMMC controller driver.
0004  *
0005  * Copyright (C) 2015 Atmel,
0006  *       2015 Ludovic Desroches <ludovic.desroches@atmel.com>
0007  */
0008
0009 #include <linux/bitfield.h>
0010 #include <linux/clk.h>
0011 #include <linux/delay.h>
0012 #include <linux/err.h>
0013 #include <linux/io.h>
0014 #include <linux/iopoll.h>
0015 #include <linux/kernel.h>
0016 #include <linux/mmc/host.h>
0017 #include <linux/mmc/slot-gpio.h>
0018 #include <linux/module.h>
0019 #include <linux/of.h>
0020 #include <linux/of_device.h>
0021 #include <linux/pm.h>
0022 #include <linux/pm_runtime.h>
0023
0024 #include "sdhci-pltfm.h"
0025
0026 #define SDMMC_MC1R  0x204
0027 #define     SDMMC_MC1R_DDR      BIT(3)
0028 #define     SDMMC_MC1R_FCD      BIT(7)
0029 #define SDMMC_CACR  0x230
0030 #define     SDMMC_CACR_CAPWREN  BIT(0)
0031 #define     SDMMC_CACR_KEY      (0x46 << 8)
0032 #define SDMMC_CALCR 0x240
0033 #define     SDMMC_CALCR_EN      BIT(0)
0034 #define     SDMMC_CALCR_ALWYSON BIT(4)
0035
0036 #define SDHCI_AT91_PRESET_COMMON_CONF   0x400 /* drv type B, programmable clock mode */
0037
0038 struct sdhci_at91_soc_data {
0039     const struct sdhci_pltfm_data *pdata;
0040     bool baseclk_is_generated_internally;
0041     unsigned int divider_for_baseclk;
0042 };
0043
0044 struct sdhci_at91_priv {
0045     const struct sdhci_at91_soc_data *soc_data;
0046     struct clk *hclock;
0047     struct clk *gck;
0048     struct clk *mainck;
0049     bool restore_needed;
0050     bool cal_always_on;
0051 };
0052
0053 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
0054 {
0055     u8 mc1r;
0056
0057     mc1r = readb(host->ioaddr + SDMMC_MC1R);
0058     mc1r |= SDMMC_MC1R_FCD;
0059     writeb(mc1r, host->ioaddr + SDMMC_MC1R);
0060 }
0061
0062 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
0063 {
0064     u16 clk;
0065
0066     host->mmc->actual_clock = 0;
0067
0068     /*
0069      * There is no requirement to disable the internal clock before
0070      * changing the SD clock configuration. Moreover, disabling the
0071      * internal clock, changing the configuration and re-enabling the
0072      * internal clock causes some bugs. It can prevent to get the internal
0073      * clock stable flag ready and an unexpected switch to the base clock
0074      * when using presets.
0075      */
0076     clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
0077     clk &= SDHCI_CLOCK_INT_EN;
0078     sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
0079
0080     if (clock == 0)
0081         return;
0082
0083     clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
0084
0085     clk |= SDHCI_CLOCK_INT_EN;
0086     sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
0087
0088     /* Wait max 20 ms */
0089     if (read_poll_timeout(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE),
0090                   1000, 20000, false, host, SDHCI_CLOCK_CONTROL)) {
0091         pr_err("%s: Internal clock never stabilised.\n",
0092                mmc_hostname(host->mmc));
0093         return;
0094     }
0095
0096     clk |= SDHCI_CLOCK_CARD_EN;
0097     sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
0098 }
0099
0100 static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,
0101                      unsigned int timing)
0102 {
0103     u8 mc1r;
0104
0105     if (timing == MMC_TIMING_MMC_DDR52) {
0106         mc1r = sdhci_readb(host, SDMMC_MC1R);
0107         mc1r |= SDMMC_MC1R_DDR;
0108         sdhci_writeb(host, mc1r, SDMMC_MC1R);
0109     }
0110     sdhci_set_uhs_signaling(host, timing);
0111 }
0112
0113 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
0114 {
0115     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0116     struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
0117     unsigned int tmp;
0118
0119     sdhci_reset(host, mask);
0120
0121     if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
0122         || mmc_gpio_get_cd(host->mmc) >= 0)
0123         sdhci_at91_set_force_card_detect(host);
0124
0125     if (priv->cal_always_on && (mask & SDHCI_RESET_ALL)) {
0126         u32 calcr = sdhci_readl(host, SDMMC_CALCR);
0127
0128         sdhci_writel(host, calcr | SDMMC_CALCR_ALWYSON | SDMMC_CALCR_EN,
0129                  SDMMC_CALCR);
0130
0131         if (read_poll_timeout(sdhci_readl, tmp, !(tmp & SDMMC_CALCR_EN),
0132                       10, 20000, false, host, SDMMC_CALCR))
0133             dev_err(mmc_dev(host->mmc), "Failed to calibrate\n");
0134     }
0135 }
0136
0137 static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
0138     .set_clock      = sdhci_at91_set_clock,
0139     .set_bus_width      = sdhci_set_bus_width,
0140     .reset          = sdhci_at91_reset,
0141     .set_uhs_signaling  = sdhci_at91_set_uhs_signaling,
0142     .set_power      = sdhci_set_power_and_bus_voltage,
0143 };
0144
0145 static const struct sdhci_pltfm_data sdhci_sama5d2_pdata = {
0146     .ops = &sdhci_at91_sama5d2_ops,
0147 };
0148
0149 static const struct sdhci_at91_soc_data soc_data_sama5d2 = {
0150     .pdata = &sdhci_sama5d2_pdata,
0151     .baseclk_is_generated_internally = false,
0152 };
0153
0154 static const struct sdhci_at91_soc_data soc_data_sam9x60 = {
0155     .pdata = &sdhci_sama5d2_pdata,
0156     .baseclk_is_generated_internally = true,
0157     .divider_for_baseclk = 2,
0158 };
0159
0160 static const struct of_device_id sdhci_at91_dt_match[] = {
0161     { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
0162     { .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 },
0163     {}
0164 };
0165 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);
0166
0167 static int sdhci_at91_set_clks_presets(struct device *dev)
0168 {
0169     struct sdhci_host *host = dev_get_drvdata(dev);
0170     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0171     struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
0172     unsigned int            caps0, caps1;
0173     unsigned int            clk_base, clk_mul;
0174     unsigned int            gck_rate, clk_base_rate;
0175     unsigned int            preset_div;
0176
0177     clk_prepare_enable(priv->hclock);
0178     caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
0179     caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
0180
0181     gck_rate = clk_get_rate(priv->gck);
0182     if (priv->soc_data->baseclk_is_generated_internally)
0183         clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk;
0184     else
0185         clk_base_rate = clk_get_rate(priv->mainck);
0186
0187     clk_base = clk_base_rate / 1000000;
0188     clk_mul = gck_rate / clk_base_rate - 1;
0189
0190     caps0 &= ~SDHCI_CLOCK_V3_BASE_MASK;
0191     caps0 |= FIELD_PREP(SDHCI_CLOCK_V3_BASE_MASK, clk_base);
0192     caps1 &= ~SDHCI_CLOCK_MUL_MASK;
0193     caps1 |= FIELD_PREP(SDHCI_CLOCK_MUL_MASK, clk_mul);
0194     /* Set capabilities in r/w mode. */
0195     writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
0196     writel(caps0, host->ioaddr + SDHCI_CAPABILITIES);
0197     writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
0198     /* Set capabilities in ro mode. */
0199     writel(0, host->ioaddr + SDMMC_CACR);
0200
0201     dev_dbg(dev, "update clk mul to %u as gck rate is %u Hz and clk base is %u Hz\n",
0202         clk_mul, gck_rate, clk_base_rate);
0203
0204     /*
0205      * We have to set preset values because it depends on the clk_mul
0206      * value. Moreover, SDR104 is supported in a degraded mode since the
0207      * maximum sd clock value is 120 MHz instead of 208 MHz. For that
0208      * reason, we need to use presets to support SDR104.
0209      */
0210     preset_div = DIV_ROUND_UP(gck_rate, 24000000) - 1;
0211     writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
0212            host->ioaddr + SDHCI_PRESET_FOR_SDR12);
0213     preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1;
0214     writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
0215            host->ioaddr + SDHCI_PRESET_FOR_SDR25);
0216     preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1;
0217     writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
0218            host->ioaddr + SDHCI_PRESET_FOR_SDR50);
0219     preset_div = DIV_ROUND_UP(gck_rate, 120000000) - 1;
0220     writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
0221            host->ioaddr + SDHCI_PRESET_FOR_SDR104);
0222     preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1;
0223     writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
0224            host->ioaddr + SDHCI_PRESET_FOR_DDR50);
0225
0226     clk_prepare_enable(priv->mainck);
0227     clk_prepare_enable(priv->gck);
0228
0229     return 0;
0230 }
0231
0232 #ifdef CONFIG_PM_SLEEP
0233 static int sdhci_at91_suspend(struct device *dev)
0234 {
0235     struct sdhci_host *host = dev_get_drvdata(dev);
0236     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0237     struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
0238     int ret;
0239
0240     ret = pm_runtime_force_suspend(dev);
0241
0242     priv->restore_needed = true;
0243
0244     return ret;
0245 }
0246 #endif /* CONFIG_PM_SLEEP */
0247
0248 #ifdef CONFIG_PM
0249 static int sdhci_at91_runtime_suspend(struct device *dev)
0250 {
0251     struct sdhci_host *host = dev_get_drvdata(dev);
0252     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0253     struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
0254     int ret;
0255
0256     ret = sdhci_runtime_suspend_host(host);
0257
0258     if (host->tuning_mode != SDHCI_TUNING_MODE_3)
0259         mmc_retune_needed(host->mmc);
0260
0261     clk_disable_unprepare(priv->gck);
0262     clk_disable_unprepare(priv->hclock);
0263     clk_disable_unprepare(priv->mainck);
0264
0265     return ret;
0266 }
0267
0268 static int sdhci_at91_runtime_resume(struct device *dev)
0269 {
0270     struct sdhci_host *host = dev_get_drvdata(dev);
0271     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0272     struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
0273     int ret;
0274
0275     if (priv->restore_needed) {
0276         ret = sdhci_at91_set_clks_presets(dev);
0277         if (ret)
0278             return ret;
0279
0280         priv->restore_needed = false;
0281         goto out;
0282     }
0283
0284     ret = clk_prepare_enable(priv->mainck);
0285     if (ret) {
0286         dev_err(dev, "can't enable mainck\n");
0287         return ret;
0288     }
0289
0290     ret = clk_prepare_enable(priv->hclock);
0291     if (ret) {
0292         dev_err(dev, "can't enable hclock\n");
0293         return ret;
0294     }
0295
0296     ret = clk_prepare_enable(priv->gck);
0297     if (ret) {
0298         dev_err(dev, "can't enable gck\n");
0299         return ret;
0300     }
0301
0302 out:
0303     return sdhci_runtime_resume_host(host, 0);
0304 }
0305 #endif /* CONFIG_PM */
0306
0307 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
0308     SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume)
0309     SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
0310                sdhci_at91_runtime_resume,
0311                NULL)
0312 };
0313
0314 static int sdhci_at91_probe(struct platform_device *pdev)
0315 {
0316     const struct sdhci_at91_soc_data    *soc_data;
0317     struct sdhci_host       *host;
0318     struct sdhci_pltfm_host     *pltfm_host;
0319     struct sdhci_at91_priv      *priv;
0320     int             ret;
0321
0322     soc_data = of_device_get_match_data(&pdev->dev);
0323     if (!soc_data)
0324         return -EINVAL;
0325
0326     host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*priv));
0327     if (IS_ERR(host))
0328         return PTR_ERR(host);
0329
0330     pltfm_host = sdhci_priv(host);
0331     priv = sdhci_pltfm_priv(pltfm_host);
0332     priv->soc_data = soc_data;
0333
0334     priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
0335     if (IS_ERR(priv->mainck)) {
0336         if (soc_data->baseclk_is_generated_internally) {
0337             priv->mainck = NULL;
0338         } else {
0339             dev_err(&pdev->dev, "failed to get baseclk\n");
0340             ret = PTR_ERR(priv->mainck);
0341             goto sdhci_pltfm_free;
0342         }
0343     }
0344
0345     priv->hclock = devm_clk_get(&pdev->dev, "hclock");
0346     if (IS_ERR(priv->hclock)) {
0347         dev_err(&pdev->dev, "failed to get hclock\n");
0348         ret = PTR_ERR(priv->hclock);
0349         goto sdhci_pltfm_free;
0350     }
0351
0352     priv->gck = devm_clk_get(&pdev->dev, "multclk");
0353     if (IS_ERR(priv->gck)) {
0354         dev_err(&pdev->dev, "failed to get multclk\n");
0355         ret = PTR_ERR(priv->gck);
0356         goto sdhci_pltfm_free;
0357     }
0358
0359     ret = sdhci_at91_set_clks_presets(&pdev->dev);
0360     if (ret)
0361         goto sdhci_pltfm_free;
0362
0363     priv->restore_needed = false;
0364
0365     /*
0366      * if SDCAL pin is wrongly connected, we must enable
0367      * the analog calibration cell permanently.
0368      */
0369     priv->cal_always_on =
0370         device_property_read_bool(&pdev->dev,
0371                       "microchip,sdcal-inverted");
0372
0373     ret = mmc_of_parse(host->mmc);
0374     if (ret)
0375         goto clocks_disable_unprepare;
0376
0377     sdhci_get_of_property(pdev);
0378
0379     pm_runtime_get_noresume(&pdev->dev);
0380     pm_runtime_set_active(&pdev->dev);
0381     pm_runtime_enable(&pdev->dev);
0382     pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
0383     pm_runtime_use_autosuspend(&pdev->dev);
0384
0385     /* HS200 is broken at this moment */
0386     host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
0387
0388     ret = sdhci_add_host(host);
0389     if (ret)
0390         goto pm_runtime_disable;
0391
0392     /*
0393      * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
0394      * the assumption that all the clocks of the controller are disabled.
0395      * It means we can't get irq from it when it is runtime suspended.
0396      * For that reason, it is not planned to wake-up on a card detect irq
0397      * from the controller.
0398      * If we want to use runtime PM and to be able to wake-up on card
0399      * insertion, we have to use a GPIO for the card detection or we can
0400      * use polling. Be aware that using polling will resume/suspend the
0401      * controller between each attempt.
0402      * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
0403      * to enable polling via device tree with broken-cd property.
0404      */
0405     if (mmc_card_is_removable(host->mmc) &&
0406         mmc_gpio_get_cd(host->mmc) < 0) {
0407         host->mmc->caps |= MMC_CAP_NEEDS_POLL;
0408         host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
0409     }
0410
0411     /*
0412      * If the device attached to the MMC bus is not removable, it is safer
0413      * to set the Force Card Detect bit. People often don't connect the
0414      * card detect signal and use this pin for another purpose. If the card
0415      * detect pin is not muxed to SDHCI controller, a default value is
0416      * used. This value can be different from a SoC revision to another
0417      * one. Problems come when this default value is not card present. To
0418      * avoid this case, if the device is non removable then the card
0419      * detection procedure using the SDMCC_CD signal is bypassed.
0420      * This bit is reset when a software reset for all command is performed
0421      * so we need to implement our own reset function to set back this bit.
0422      *
0423      * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line.
0424      */
0425     if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
0426         || mmc_gpio_get_cd(host->mmc) >= 0)
0427         sdhci_at91_set_force_card_detect(host);
0428
0429     pm_runtime_put_autosuspend(&pdev->dev);
0430
0431     return 0;
0432
0433 pm_runtime_disable:
0434     pm_runtime_disable(&pdev->dev);
0435     pm_runtime_set_suspended(&pdev->dev);
0436     pm_runtime_put_noidle(&pdev->dev);
0437 clocks_disable_unprepare:
0438     clk_disable_unprepare(priv->gck);
0439     clk_disable_unprepare(priv->mainck);
0440     clk_disable_unprepare(priv->hclock);
0441 sdhci_pltfm_free:
0442     sdhci_pltfm_free(pdev);
0443     return ret;
0444 }
0445
0446 static int sdhci_at91_remove(struct platform_device *pdev)
0447 {
0448     struct sdhci_host   *host = platform_get_drvdata(pdev);
0449     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0450     struct sdhci_at91_priv  *priv = sdhci_pltfm_priv(pltfm_host);
0451     struct clk *gck = priv->gck;
0452     struct clk *hclock = priv->hclock;
0453     struct clk *mainck = priv->mainck;
0454
0455     pm_runtime_get_sync(&pdev->dev);
0456     pm_runtime_disable(&pdev->dev);
0457     pm_runtime_put_noidle(&pdev->dev);
0458
0459     sdhci_pltfm_unregister(pdev);
0460
0461     clk_disable_unprepare(gck);
0462     clk_disable_unprepare(hclock);
0463     clk_disable_unprepare(mainck);
0464
0465     return 0;
0466 }
0467
0468 static struct platform_driver sdhci_at91_driver = {
0469     .driver     = {
0470         .name   = "sdhci-at91",
0471         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0472         .of_match_table = sdhci_at91_dt_match,
0473         .pm = &sdhci_at91_dev_pm_ops,
0474     },
0475     .probe      = sdhci_at91_probe,
0476     .remove     = sdhci_at91_remove,
0477 };
0478
0479 module_platform_driver(sdhci_at91_driver);
0480
0481 MODULE_DESCRIPTION("SDHCI driver for at91");
0482 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
0483 MODULE_LICENSE("GPL v2");