0001
0002
0003
0004
0005 #include <linux/clk.h>
0006 #include <linux/delay.h>
0007 #include <linux/device.h>
0008 #include <linux/io.h>
0009 #include <linux/math64.h>
0010 #include <linux/mmc/host.h>
0011 #include <linux/module.h>
0012 #include <linux/of_address.h>
0013 #include <linux/of.h>
0014 #include <linux/of_platform.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/spinlock.h>
0017
0018 #include "sdhci-pltfm.h"
0019
0020 #define ASPEED_SDC_INFO 0x00
0021 #define ASPEED_SDC_S1_MMC8 BIT(25)
0022 #define ASPEED_SDC_S0_MMC8 BIT(24)
0023 #define ASPEED_SDC_PHASE 0xf4
0024 #define ASPEED_SDC_S1_PHASE_IN GENMASK(25, 21)
0025 #define ASPEED_SDC_S0_PHASE_IN GENMASK(20, 16)
0026 #define ASPEED_SDC_S1_PHASE_OUT GENMASK(15, 11)
0027 #define ASPEED_SDC_S1_PHASE_IN_EN BIT(10)
0028 #define ASPEED_SDC_S1_PHASE_OUT_EN GENMASK(9, 8)
0029 #define ASPEED_SDC_S0_PHASE_OUT GENMASK(7, 3)
0030 #define ASPEED_SDC_S0_PHASE_IN_EN BIT(2)
0031 #define ASPEED_SDC_S0_PHASE_OUT_EN GENMASK(1, 0)
0032 #define ASPEED_SDC_PHASE_MAX 31
0033
0034
0035 #define ASPEED_SDC_CAP1_1_8V (0 * 32 + 26)
0036
0037 #define ASPEED_SDC_CAP2_SDR104 (1 * 32 + 1)
0038
0039 struct aspeed_sdc {
0040 struct clk *clk;
0041 struct resource *res;
0042
0043 spinlock_t lock;
0044 void __iomem *regs;
0045 };
0046
0047 struct aspeed_sdhci_tap_param {
0048 bool valid;
0049
0050 #define ASPEED_SDHCI_TAP_PARAM_INVERT_CLK BIT(4)
0051 u8 in;
0052 u8 out;
0053 };
0054
0055 struct aspeed_sdhci_tap_desc {
0056 u32 tap_mask;
0057 u32 enable_mask;
0058 u8 enable_value;
0059 };
0060
0061 struct aspeed_sdhci_phase_desc {
0062 struct aspeed_sdhci_tap_desc in;
0063 struct aspeed_sdhci_tap_desc out;
0064 };
0065
0066 struct aspeed_sdhci_pdata {
0067 unsigned int clk_div_start;
0068 const struct aspeed_sdhci_phase_desc *phase_desc;
0069 size_t nr_phase_descs;
0070 };
0071
0072 struct aspeed_sdhci {
0073 const struct aspeed_sdhci_pdata *pdata;
0074 struct aspeed_sdc *parent;
0075 u32 width_mask;
0076 struct mmc_clk_phase_map phase_map;
0077 const struct aspeed_sdhci_phase_desc *phase_desc;
0078 };
0079
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
0091 static void aspeed_sdc_set_slot_capability(struct sdhci_host *host, struct aspeed_sdc *sdc,
0092 int capability, bool enable, u8 slot)
0093 {
0094 u32 mirror_reg_offset;
0095 u32 cap_val;
0096 u8 cap_reg;
0097
0098 if (slot > 1)
0099 return;
0100
0101 cap_reg = capability / 32;
0102 cap_val = sdhci_readl(host, 0x40 + (cap_reg * 4));
0103 if (enable)
0104 cap_val |= BIT(capability % 32);
0105 else
0106 cap_val &= ~BIT(capability % 32);
0107 mirror_reg_offset = ((slot + 1) * 0x10) + (cap_reg * 4);
0108 writel(cap_val, sdc->regs + mirror_reg_offset);
0109 }
0110
0111 static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc,
0112 struct aspeed_sdhci *sdhci,
0113 bool bus8)
0114 {
0115 u32 info;
0116
0117
0118 spin_lock(&sdc->lock);
0119 info = readl(sdc->regs + ASPEED_SDC_INFO);
0120 if (bus8)
0121 info |= sdhci->width_mask;
0122 else
0123 info &= ~sdhci->width_mask;
0124 writel(info, sdc->regs + ASPEED_SDC_INFO);
0125 spin_unlock(&sdc->lock);
0126 }
0127
0128 static u32
0129 aspeed_sdc_set_phase_tap(const struct aspeed_sdhci_tap_desc *desc,
0130 u8 tap, bool enable, u32 reg)
0131 {
0132 reg &= ~(desc->enable_mask | desc->tap_mask);
0133 if (enable) {
0134 reg |= tap << __ffs(desc->tap_mask);
0135 reg |= desc->enable_value << __ffs(desc->enable_mask);
0136 }
0137
0138 return reg;
0139 }
0140
0141 static void
0142 aspeed_sdc_set_phase_taps(struct aspeed_sdc *sdc,
0143 const struct aspeed_sdhci_phase_desc *desc,
0144 const struct aspeed_sdhci_tap_param *taps)
0145 {
0146 u32 reg;
0147
0148 spin_lock(&sdc->lock);
0149 reg = readl(sdc->regs + ASPEED_SDC_PHASE);
0150
0151 reg = aspeed_sdc_set_phase_tap(&desc->in, taps->in, taps->valid, reg);
0152 reg = aspeed_sdc_set_phase_tap(&desc->out, taps->out, taps->valid, reg);
0153
0154 writel(reg, sdc->regs + ASPEED_SDC_PHASE);
0155 spin_unlock(&sdc->lock);
0156 }
0157
0158 #define PICOSECONDS_PER_SECOND 1000000000000ULL
0159 #define ASPEED_SDHCI_NR_TAPS 15
0160
0161 #define ASPEED_SDHCI_MAX_TAP_DELAY_PS 1253
0162 static int aspeed_sdhci_phase_to_tap(struct device *dev, unsigned long rate_hz,
0163 int phase_deg)
0164 {
0165 u64 phase_period_ps;
0166 u64 prop_delay_ps;
0167 u64 clk_period_ps;
0168 unsigned int tap;
0169 u8 inverted;
0170
0171 phase_deg %= 360;
0172
0173 if (phase_deg >= 180) {
0174 inverted = ASPEED_SDHCI_TAP_PARAM_INVERT_CLK;
0175 phase_deg -= 180;
0176 dev_dbg(dev,
0177 "Inverting clock to reduce phase correction from %d to %d degrees\n",
0178 phase_deg + 180, phase_deg);
0179 } else {
0180 inverted = 0;
0181 }
0182
0183 prop_delay_ps = ASPEED_SDHCI_MAX_TAP_DELAY_PS / ASPEED_SDHCI_NR_TAPS;
0184 clk_period_ps = div_u64(PICOSECONDS_PER_SECOND, (u64)rate_hz);
0185 phase_period_ps = div_u64((u64)phase_deg * clk_period_ps, 360ULL);
0186
0187 tap = div_u64(phase_period_ps, prop_delay_ps);
0188 if (tap > ASPEED_SDHCI_NR_TAPS) {
0189 dev_dbg(dev,
0190 "Requested out of range phase tap %d for %d degrees of phase compensation at %luHz, clamping to tap %d\n",
0191 tap, phase_deg, rate_hz, ASPEED_SDHCI_NR_TAPS);
0192 tap = ASPEED_SDHCI_NR_TAPS;
0193 }
0194
0195 return inverted | tap;
0196 }
0197
0198 static void
0199 aspeed_sdhci_phases_to_taps(struct device *dev, unsigned long rate,
0200 const struct mmc_clk_phase *phases,
0201 struct aspeed_sdhci_tap_param *taps)
0202 {
0203 taps->valid = phases->valid;
0204
0205 if (!phases->valid)
0206 return;
0207
0208 taps->in = aspeed_sdhci_phase_to_tap(dev, rate, phases->in_deg);
0209 taps->out = aspeed_sdhci_phase_to_tap(dev, rate, phases->out_deg);
0210 }
0211
0212 static void
0213 aspeed_sdhci_configure_phase(struct sdhci_host *host, unsigned long rate)
0214 {
0215 struct aspeed_sdhci_tap_param _taps = {0}, *taps = &_taps;
0216 struct mmc_clk_phase *params;
0217 struct aspeed_sdhci *sdhci;
0218 struct device *dev;
0219
0220 dev = mmc_dev(host->mmc);
0221 sdhci = sdhci_pltfm_priv(sdhci_priv(host));
0222
0223 if (!sdhci->phase_desc)
0224 return;
0225
0226 params = &sdhci->phase_map.phase[host->timing];
0227 aspeed_sdhci_phases_to_taps(dev, rate, params, taps);
0228 aspeed_sdc_set_phase_taps(sdhci->parent, sdhci->phase_desc, taps);
0229 dev_dbg(dev,
0230 "Using taps [%d, %d] for [%d, %d] degrees of phase correction at %luHz (%d)\n",
0231 taps->in & ASPEED_SDHCI_NR_TAPS,
0232 taps->out & ASPEED_SDHCI_NR_TAPS,
0233 params->in_deg, params->out_deg, rate, host->timing);
0234 }
0235
0236 static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
0237 {
0238 struct sdhci_pltfm_host *pltfm_host;
0239 unsigned long parent, bus;
0240 struct aspeed_sdhci *sdhci;
0241 int div;
0242 u16 clk;
0243
0244 pltfm_host = sdhci_priv(host);
0245 sdhci = sdhci_pltfm_priv(pltfm_host);
0246
0247 parent = clk_get_rate(pltfm_host->clk);
0248
0249 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
0250
0251 if (clock == 0)
0252 return;
0253
0254 if (WARN_ON(clock > host->max_clk))
0255 clock = host->max_clk;
0256
0257
0258
0259
0260
0261
0262
0263
0264
0265
0266
0267
0268
0269
0270
0271
0272
0273 for (div = sdhci->pdata->clk_div_start; div < 256; div *= 2) {
0274 bus = parent / div;
0275 if (bus <= clock)
0276 break;
0277 }
0278
0279 div >>= 1;
0280
0281 clk = div << SDHCI_DIVIDER_SHIFT;
0282
0283 aspeed_sdhci_configure_phase(host, bus);
0284
0285 sdhci_enable_clk(host, clk);
0286 }
0287
0288 static unsigned int aspeed_sdhci_get_max_clock(struct sdhci_host *host)
0289 {
0290 if (host->mmc->f_max)
0291 return host->mmc->f_max;
0292
0293 return sdhci_pltfm_clk_get_max_clock(host);
0294 }
0295
0296 static void aspeed_sdhci_set_bus_width(struct sdhci_host *host, int width)
0297 {
0298 struct sdhci_pltfm_host *pltfm_priv;
0299 struct aspeed_sdhci *aspeed_sdhci;
0300 struct aspeed_sdc *aspeed_sdc;
0301 u8 ctrl;
0302
0303 pltfm_priv = sdhci_priv(host);
0304 aspeed_sdhci = sdhci_pltfm_priv(pltfm_priv);
0305 aspeed_sdc = aspeed_sdhci->parent;
0306
0307
0308 aspeed_sdc_configure_8bit_mode(aspeed_sdc, aspeed_sdhci,
0309 width == MMC_BUS_WIDTH_8);
0310
0311
0312 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
0313 if (width == MMC_BUS_WIDTH_4)
0314 ctrl |= SDHCI_CTRL_4BITBUS;
0315 else
0316 ctrl &= ~SDHCI_CTRL_4BITBUS;
0317 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
0318 }
0319
0320 static u32 aspeed_sdhci_readl(struct sdhci_host *host, int reg)
0321 {
0322 u32 val = readl(host->ioaddr + reg);
0323
0324 if (unlikely(reg == SDHCI_PRESENT_STATE) &&
0325 (host->mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH))
0326 val ^= SDHCI_CARD_PRESENT;
0327
0328 return val;
0329 }
0330
0331 static const struct sdhci_ops aspeed_sdhci_ops = {
0332 .read_l = aspeed_sdhci_readl,
0333 .set_clock = aspeed_sdhci_set_clock,
0334 .get_max_clock = aspeed_sdhci_get_max_clock,
0335 .set_bus_width = aspeed_sdhci_set_bus_width,
0336 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
0337 .reset = sdhci_reset,
0338 .set_uhs_signaling = sdhci_set_uhs_signaling,
0339 };
0340
0341 static const struct sdhci_pltfm_data aspeed_sdhci_pdata = {
0342 .ops = &aspeed_sdhci_ops,
0343 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
0344 };
0345
0346 static inline int aspeed_sdhci_calculate_slot(struct aspeed_sdhci *dev,
0347 struct resource *res)
0348 {
0349 resource_size_t delta;
0350
0351 if (!res || resource_type(res) != IORESOURCE_MEM)
0352 return -EINVAL;
0353
0354 if (res->start < dev->parent->res->start)
0355 return -EINVAL;
0356
0357 delta = res->start - dev->parent->res->start;
0358 if (delta & (0x100 - 1))
0359 return -EINVAL;
0360
0361 return (delta / 0x100) - 1;
0362 }
0363
0364 static int aspeed_sdhci_probe(struct platform_device *pdev)
0365 {
0366 const struct aspeed_sdhci_pdata *aspeed_pdata;
0367 struct device_node *np = pdev->dev.of_node;
0368 struct sdhci_pltfm_host *pltfm_host;
0369 struct aspeed_sdhci *dev;
0370 struct sdhci_host *host;
0371 struct resource *res;
0372 int slot;
0373 int ret;
0374
0375 aspeed_pdata = of_device_get_match_data(&pdev->dev);
0376 if (!aspeed_pdata) {
0377 dev_err(&pdev->dev, "Missing platform configuration data\n");
0378 return -EINVAL;
0379 }
0380
0381 host = sdhci_pltfm_init(pdev, &aspeed_sdhci_pdata, sizeof(*dev));
0382 if (IS_ERR(host))
0383 return PTR_ERR(host);
0384
0385 pltfm_host = sdhci_priv(host);
0386 dev = sdhci_pltfm_priv(pltfm_host);
0387 dev->pdata = aspeed_pdata;
0388 dev->parent = dev_get_drvdata(pdev->dev.parent);
0389
0390 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0391 slot = aspeed_sdhci_calculate_slot(dev, res);
0392
0393 if (slot < 0)
0394 return slot;
0395 else if (slot >= 2)
0396 return -EINVAL;
0397
0398 if (slot < dev->pdata->nr_phase_descs) {
0399 dev->phase_desc = &dev->pdata->phase_desc[slot];
0400 } else {
0401 dev_info(&pdev->dev,
0402 "Phase control not supported for slot %d\n", slot);
0403 dev->phase_desc = NULL;
0404 }
0405
0406 dev->width_mask = !slot ? ASPEED_SDC_S0_MMC8 : ASPEED_SDC_S1_MMC8;
0407
0408 dev_info(&pdev->dev, "Configured for slot %d\n", slot);
0409
0410 sdhci_get_of_property(pdev);
0411
0412 if (of_property_read_bool(np, "mmc-hs200-1_8v") ||
0413 of_property_read_bool(np, "sd-uhs-sdr104")) {
0414 aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP1_1_8V,
0415 true, slot);
0416 }
0417
0418 if (of_property_read_bool(np, "sd-uhs-sdr104")) {
0419 aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP2_SDR104,
0420 true, slot);
0421 }
0422
0423 pltfm_host->clk = devm_clk_get(&pdev->dev, NULL);
0424 if (IS_ERR(pltfm_host->clk))
0425 return PTR_ERR(pltfm_host->clk);
0426
0427 ret = clk_prepare_enable(pltfm_host->clk);
0428 if (ret) {
0429 dev_err(&pdev->dev, "Unable to enable SDIO clock\n");
0430 goto err_pltfm_free;
0431 }
0432
0433 ret = mmc_of_parse(host->mmc);
0434 if (ret)
0435 goto err_sdhci_add;
0436
0437 if (dev->phase_desc)
0438 mmc_of_parse_clk_phase(host->mmc, &dev->phase_map);
0439
0440 ret = sdhci_add_host(host);
0441 if (ret)
0442 goto err_sdhci_add;
0443
0444 return 0;
0445
0446 err_sdhci_add:
0447 clk_disable_unprepare(pltfm_host->clk);
0448 err_pltfm_free:
0449 sdhci_pltfm_free(pdev);
0450 return ret;
0451 }
0452
0453 static int aspeed_sdhci_remove(struct platform_device *pdev)
0454 {
0455 struct sdhci_pltfm_host *pltfm_host;
0456 struct sdhci_host *host;
0457 int dead = 0;
0458
0459 host = platform_get_drvdata(pdev);
0460 pltfm_host = sdhci_priv(host);
0461
0462 sdhci_remove_host(host, dead);
0463
0464 clk_disable_unprepare(pltfm_host->clk);
0465
0466 sdhci_pltfm_free(pdev);
0467
0468 return 0;
0469 }
0470
0471 static const struct aspeed_sdhci_pdata ast2400_sdhci_pdata = {
0472 .clk_div_start = 2,
0473 };
0474
0475 static const struct aspeed_sdhci_phase_desc ast2600_sdhci_phase[] = {
0476
0477 [0] = {
0478 .in = {
0479 .tap_mask = ASPEED_SDC_S0_PHASE_IN,
0480 .enable_mask = ASPEED_SDC_S0_PHASE_IN_EN,
0481 .enable_value = 1,
0482 },
0483 .out = {
0484 .tap_mask = ASPEED_SDC_S0_PHASE_OUT,
0485 .enable_mask = ASPEED_SDC_S0_PHASE_OUT_EN,
0486 .enable_value = 3,
0487 },
0488 },
0489
0490 [1] = {
0491 .in = {
0492 .tap_mask = ASPEED_SDC_S1_PHASE_IN,
0493 .enable_mask = ASPEED_SDC_S1_PHASE_IN_EN,
0494 .enable_value = 1,
0495 },
0496 .out = {
0497 .tap_mask = ASPEED_SDC_S1_PHASE_OUT,
0498 .enable_mask = ASPEED_SDC_S1_PHASE_OUT_EN,
0499 .enable_value = 3,
0500 },
0501 },
0502 };
0503
0504 static const struct aspeed_sdhci_pdata ast2600_sdhci_pdata = {
0505 .clk_div_start = 1,
0506 .phase_desc = ast2600_sdhci_phase,
0507 .nr_phase_descs = ARRAY_SIZE(ast2600_sdhci_phase),
0508 };
0509
0510 static const struct of_device_id aspeed_sdhci_of_match[] = {
0511 { .compatible = "aspeed,ast2400-sdhci", .data = &ast2400_sdhci_pdata, },
0512 { .compatible = "aspeed,ast2500-sdhci", .data = &ast2400_sdhci_pdata, },
0513 { .compatible = "aspeed,ast2600-sdhci", .data = &ast2600_sdhci_pdata, },
0514 { }
0515 };
0516
0517 static struct platform_driver aspeed_sdhci_driver = {
0518 .driver = {
0519 .name = "sdhci-aspeed",
0520 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0521 .of_match_table = aspeed_sdhci_of_match,
0522 },
0523 .probe = aspeed_sdhci_probe,
0524 .remove = aspeed_sdhci_remove,
0525 };
0526
0527 static int aspeed_sdc_probe(struct platform_device *pdev)
0528
0529 {
0530 struct device_node *parent, *child;
0531 struct aspeed_sdc *sdc;
0532 int ret;
0533
0534 sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL);
0535 if (!sdc)
0536 return -ENOMEM;
0537
0538 spin_lock_init(&sdc->lock);
0539
0540 sdc->clk = devm_clk_get(&pdev->dev, NULL);
0541 if (IS_ERR(sdc->clk))
0542 return PTR_ERR(sdc->clk);
0543
0544 ret = clk_prepare_enable(sdc->clk);
0545 if (ret) {
0546 dev_err(&pdev->dev, "Unable to enable SDCLK\n");
0547 return ret;
0548 }
0549
0550 sdc->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0551 sdc->regs = devm_ioremap_resource(&pdev->dev, sdc->res);
0552 if (IS_ERR(sdc->regs)) {
0553 ret = PTR_ERR(sdc->regs);
0554 goto err_clk;
0555 }
0556
0557 dev_set_drvdata(&pdev->dev, sdc);
0558
0559 parent = pdev->dev.of_node;
0560 for_each_available_child_of_node(parent, child) {
0561 struct platform_device *cpdev;
0562
0563 cpdev = of_platform_device_create(child, NULL, &pdev->dev);
0564 if (!cpdev) {
0565 of_node_put(child);
0566 ret = -ENODEV;
0567 goto err_clk;
0568 }
0569 }
0570
0571 return 0;
0572
0573 err_clk:
0574 clk_disable_unprepare(sdc->clk);
0575 return ret;
0576 }
0577
0578 static int aspeed_sdc_remove(struct platform_device *pdev)
0579 {
0580 struct aspeed_sdc *sdc = dev_get_drvdata(&pdev->dev);
0581
0582 clk_disable_unprepare(sdc->clk);
0583
0584 return 0;
0585 }
0586
0587 static const struct of_device_id aspeed_sdc_of_match[] = {
0588 { .compatible = "aspeed,ast2400-sd-controller", },
0589 { .compatible = "aspeed,ast2500-sd-controller", },
0590 { .compatible = "aspeed,ast2600-sd-controller", },
0591 { }
0592 };
0593
0594 MODULE_DEVICE_TABLE(of, aspeed_sdc_of_match);
0595
0596 static struct platform_driver aspeed_sdc_driver = {
0597 .driver = {
0598 .name = "sd-controller-aspeed",
0599 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0600 .pm = &sdhci_pltfm_pmops,
0601 .of_match_table = aspeed_sdc_of_match,
0602 },
0603 .probe = aspeed_sdc_probe,
0604 .remove = aspeed_sdc_remove,
0605 };
0606
0607 #if defined(CONFIG_MMC_SDHCI_OF_ASPEED_TEST)
0608 #include "sdhci-of-aspeed-test.c"
0609 #endif
0610
0611 static int __init aspeed_sdc_init(void)
0612 {
0613 int rc;
0614
0615 rc = platform_driver_register(&aspeed_sdhci_driver);
0616 if (rc < 0)
0617 return rc;
0618
0619 rc = platform_driver_register(&aspeed_sdc_driver);
0620 if (rc < 0)
0621 platform_driver_unregister(&aspeed_sdhci_driver);
0622
0623 return rc;
0624 }
0625 module_init(aspeed_sdc_init);
0626
0627 static void __exit aspeed_sdc_exit(void)
0628 {
0629 platform_driver_unregister(&aspeed_sdc_driver);
0630 platform_driver_unregister(&aspeed_sdhci_driver);
0631 }
0632 module_exit(aspeed_sdc_exit);
0633
0634 MODULE_DESCRIPTION("Driver for the ASPEED SD/SDIO/SDHCI Controllers");
0635 MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>");
0636 MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>");
0637 MODULE_LICENSE("GPL");
