mmc/host/sdhci-esdhc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Freescale eSDHC controller driver generics for OF and pltfm.
0004  *
0005  * Copyright (c) 2007 Freescale Semiconductor, Inc.
0006  * Copyright (c) 2009 MontaVista Software, Inc.
0007  * Copyright (c) 2010 Pengutronix e.K.
0008  * Copyright 2020 NXP
0009  *   Author: Wolfram Sang <kernel@pengutronix.de>
0010  */
0011
0012 #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
0013 #define _DRIVERS_MMC_SDHCI_ESDHC_H
0014
0015 /*
0016  * Ops and quirks for the Freescale eSDHC controller.
0017  */
0018
0019 #define ESDHC_DEFAULT_QUIRKS    (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
0020                 SDHCI_QUIRK_32BIT_DMA_ADDR | \
0021                 SDHCI_QUIRK_NO_BUSY_IRQ | \
0022                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
0023                 SDHCI_QUIRK_PIO_NEEDS_DELAY | \
0024                 SDHCI_QUIRK_NO_HISPD_BIT)
0025
0026 /* pltfm-specific */
0027 #define ESDHC_HOST_CONTROL_LE   0x20
0028
0029 /*
0030  * eSDHC register definition
0031  */
0032
0033 /* Present State Register */
0034 #define ESDHC_PRSSTAT           0x24
0035 #define ESDHC_CLOCK_GATE_OFF        0x00000080
0036 #define ESDHC_CLOCK_STABLE      0x00000008
0037
0038 /* Protocol Control Register */
0039 #define ESDHC_PROCTL            0x28
0040 #define ESDHC_VOLT_SEL          0x00000400
0041 #define ESDHC_CTRL_4BITBUS      (0x1 << 1)
0042 #define ESDHC_CTRL_8BITBUS      (0x2 << 1)
0043 #define ESDHC_CTRL_BUSWIDTH_MASK    (0x3 << 1)
0044 #define ESDHC_HOST_CONTROL_RES      0x01
0045
0046 /* System Control Register */
0047 #define ESDHC_SYSTEM_CONTROL        0x2c
0048 #define ESDHC_CLOCK_MASK        0x0000fff0
0049 #define ESDHC_PREDIV_SHIFT      8
0050 #define ESDHC_DIVIDER_SHIFT     4
0051 #define ESDHC_CLOCK_SDCLKEN     0x00000008
0052 #define ESDHC_CLOCK_PEREN       0x00000004
0053 #define ESDHC_CLOCK_HCKEN       0x00000002
0054 #define ESDHC_CLOCK_IPGEN       0x00000001
0055
0056 /* System Control 2 Register */
0057 #define ESDHC_SYSTEM_CONTROL_2      0x3c
0058 #define ESDHC_SMPCLKSEL         0x00800000
0059 #define ESDHC_EXTN          0x00400000
0060
0061 /* Host Controller Capabilities Register 2 */
0062 #define ESDHC_CAPABILITIES_1        0x114
0063
0064 /* Tuning Block Control Register */
0065 #define ESDHC_TBCTL         0x120
0066 #define ESDHC_HS400_WNDW_ADJUST     0x00000040
0067 #define ESDHC_HS400_MODE        0x00000010
0068 #define ESDHC_TB_EN         0x00000004
0069 #define ESDHC_TB_MODE_MASK      0x00000003
0070 #define ESDHC_TB_MODE_SW        0x00000003
0071 #define ESDHC_TB_MODE_3         0x00000002
0072
0073 #define ESDHC_TBSTAT            0x124
0074
0075 #define ESDHC_TBPTR         0x128
0076 #define ESDHC_WNDW_STRT_PTR_SHIFT   8
0077 #define ESDHC_WNDW_STRT_PTR_MASK    (0x7f << 8)
0078 #define ESDHC_WNDW_END_PTR_MASK     0x7f
0079
0080 /* SD Clock Control Register */
0081 #define ESDHC_SDCLKCTL          0x144
0082 #define ESDHC_LPBK_CLK_SEL      0x80000000
0083 #define ESDHC_CMD_CLK_CTL       0x00008000
0084
0085 /* SD Timing Control Register */
0086 #define ESDHC_SDTIMNGCTL        0x148
0087 #define ESDHC_FLW_CTL_BG        0x00008000
0088
0089 /* DLL Config 0 Register */
0090 #define ESDHC_DLLCFG0           0x160
0091 #define ESDHC_DLL_ENABLE        0x80000000
0092 #define ESDHC_DLL_RESET         0x40000000
0093 #define ESDHC_DLL_FREQ_SEL      0x08000000
0094
0095 /* DLL Config 1 Register */
0096 #define ESDHC_DLLCFG1           0x164
0097 #define ESDHC_DLL_PD_PULSE_STRETCH_SEL  0x80000000
0098
0099 /* DLL Status 0 Register */
0100 #define ESDHC_DLLSTAT0          0x170
0101 #define ESDHC_DLL_STS_SLV_LOCK      0x08000000
0102
0103 /* Control Register for DMA transfer */
0104 #define ESDHC_DMA_SYSCTL        0x40c
0105 #define ESDHC_PERIPHERAL_CLK_SEL    0x00080000
0106 #define ESDHC_FLUSH_ASYNC_FIFO      0x00040000
0107 #define ESDHC_DMA_SNOOP         0x00000040
0108
0109 #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */