mmc/host/sdhci-esdhc-mcf.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Freescale eSDHC ColdFire family controller driver, platform bus.
0004  *
0005  * Copyright (c) 2020 Timesys Corporation
0006  *   Author: Angelo Dureghello <angelo.dureghello@timesys.it>
0007  */
0008
0009 #include <linux/module.h>
0010 #include <linux/delay.h>
0011 #include <linux/platform_data/mmc-esdhc-mcf.h>
0012 #include <linux/mmc/mmc.h>
0013 #include "sdhci-pltfm.h"
0014 #include "sdhci-esdhc.h"
0015
0016 #define ESDHC_PROCTL_D3CD       0x08
0017 #define ESDHC_SYS_CTRL_DTOCV_MASK   0x0f
0018 #define ESDHC_DEFAULT_HOST_CONTROL  0x28
0019
0020 /*
0021  * Freescale eSDHC has DMA ERR flag at bit 28, not as std spec says, bit 25.
0022  */
0023 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   BIT(28)
0024
0025 struct pltfm_mcf_data {
0026     struct clk *clk_ipg;
0027     struct clk *clk_ahb;
0028     struct clk *clk_per;
0029     int aside;
0030     int current_bus_width;
0031 };
0032
0033 static inline void esdhc_mcf_buffer_swap32(u32 *buf, int len)
0034 {
0035     int i;
0036     u32 temp;
0037
0038     len = (len + 3) >> 2;
0039
0040     for (i = 0; i < len;  i++) {
0041         temp = swab32(*buf);
0042         *buf++ = temp;
0043     }
0044 }
0045
0046 static inline void esdhc_clrset_be(struct sdhci_host *host,
0047                    u32 mask, u32 val, int reg)
0048 {
0049     void __iomem *base = host->ioaddr + (reg & ~3);
0050     u8 shift = (reg & 3) << 3;
0051
0052     mask <<= shift;
0053     val <<= shift;
0054
0055     if (reg == SDHCI_HOST_CONTROL)
0056         val |= ESDHC_PROCTL_D3CD;
0057
0058     writel((readl(base) & ~mask) | val, base);
0059 }
0060
0061 /*
0062  * Note: mcf is big-endian, single bytes need to be accessed at big endian
0063  * offsets.
0064  */
0065 static void esdhc_mcf_writeb_be(struct sdhci_host *host, u8 val, int reg)
0066 {
0067     void __iomem *base = host->ioaddr + (reg & ~3);
0068     u8 shift = (reg & 3) << 3;
0069     u32 mask = ~(0xff << shift);
0070
0071     if (reg == SDHCI_HOST_CONTROL) {
0072         u32 host_ctrl = ESDHC_DEFAULT_HOST_CONTROL;
0073         u8 dma_bits = (val & SDHCI_CTRL_DMA_MASK) >> 3;
0074         u8 tmp = readb(host->ioaddr + SDHCI_HOST_CONTROL + 1);
0075
0076         tmp &= ~0x03;
0077         tmp |= dma_bits;
0078
0079         /*
0080          * Recomposition needed, restore always endianness and
0081          * keep D3CD and AI, just setting bus width.
0082          */
0083         host_ctrl |= val;
0084         host_ctrl |= (dma_bits << 8);
0085         writel(host_ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
0086
0087         return;
0088     }
0089
0090     writel((readl(base) & mask) | (val << shift), base);
0091 }
0092
0093 static void esdhc_mcf_writew_be(struct sdhci_host *host, u16 val, int reg)
0094 {
0095     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0096     struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
0097     void __iomem *base = host->ioaddr + (reg & ~3);
0098     u8 shift = (reg & 3) << 3;
0099     u32 mask = ~(0xffff << shift);
0100
0101     switch (reg) {
0102     case SDHCI_TRANSFER_MODE:
0103         mcf_data->aside = val;
0104         return;
0105     case SDHCI_COMMAND:
0106         if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
0107             val |= SDHCI_CMD_ABORTCMD;
0108
0109         /*
0110          * As for the fsl driver,
0111          * we have to set the mode in a single write here.
0112          */
0113         writel(val << 16 | mcf_data->aside,
0114                host->ioaddr + SDHCI_TRANSFER_MODE);
0115         return;
0116     }
0117
0118     writel((readl(base) & mask) | (val << shift), base);
0119 }
0120
0121 static void esdhc_mcf_writel_be(struct sdhci_host *host, u32 val, int reg)
0122 {
0123     writel(val, host->ioaddr + reg);
0124 }
0125
0126 static u8 esdhc_mcf_readb_be(struct sdhci_host *host, int reg)
0127 {
0128     if (reg == SDHCI_HOST_CONTROL) {
0129         u8 __iomem *base = host->ioaddr + (reg & ~3);
0130         u16 val = readw(base + 2);
0131         u8 dma_bits = (val >> 5) & SDHCI_CTRL_DMA_MASK;
0132         u8 host_ctrl = val & 0xff;
0133
0134         host_ctrl &= ~SDHCI_CTRL_DMA_MASK;
0135         host_ctrl |= dma_bits;
0136
0137         return host_ctrl;
0138     }
0139
0140     return readb(host->ioaddr + (reg ^ 0x3));
0141 }
0142
0143 static u16 esdhc_mcf_readw_be(struct sdhci_host *host, int reg)
0144 {
0145     /*
0146      * For SDHCI_HOST_VERSION, sdhci specs defines 0xFE,
0147      * a wrong offset for us, we are at 0xFC.
0148      */
0149     if (reg == SDHCI_HOST_VERSION)
0150         reg -= 2;
0151
0152     return readw(host->ioaddr + (reg ^ 0x2));
0153 }
0154
0155 static u32 esdhc_mcf_readl_be(struct sdhci_host *host, int reg)
0156 {
0157     u32 val;
0158
0159     val = readl(host->ioaddr + reg);
0160
0161     /*
0162      * RM (25.3.9) sd pin clock must never exceed 25Mhz.
0163      * So forcing legacy mode at 25Mhz.
0164      */
0165     if (unlikely(reg == SDHCI_CAPABILITIES))
0166         val &= ~SDHCI_CAN_DO_HISPD;
0167
0168     if (unlikely(reg == SDHCI_INT_STATUS)) {
0169         if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
0170             val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
0171             val |= SDHCI_INT_ADMA_ERROR;
0172         }
0173     }
0174
0175     return val;
0176 }
0177
0178 static unsigned int esdhc_mcf_get_max_timeout_count(struct sdhci_host *host)
0179 {
0180     return 1 << 27;
0181 }
0182
0183 static void esdhc_mcf_set_timeout(struct sdhci_host *host,
0184                   struct mmc_command *cmd)
0185 {
0186     /* Use maximum timeout counter */
0187     esdhc_clrset_be(host, ESDHC_SYS_CTRL_DTOCV_MASK, 0xE,
0188             SDHCI_TIMEOUT_CONTROL);
0189 }
0190
0191 static void esdhc_mcf_reset(struct sdhci_host *host, u8 mask)
0192 {
0193     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0194     struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
0195
0196     sdhci_reset(host, mask);
0197
0198     esdhc_clrset_be(host, ESDHC_CTRL_BUSWIDTH_MASK,
0199             mcf_data->current_bus_width, SDHCI_HOST_CONTROL);
0200
0201     sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
0202     sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
0203 }
0204
0205 static unsigned int esdhc_mcf_pltfm_get_max_clock(struct sdhci_host *host)
0206 {
0207     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0208
0209     return pltfm_host->clock;
0210 }
0211
0212 static unsigned int esdhc_mcf_pltfm_get_min_clock(struct sdhci_host *host)
0213 {
0214     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0215
0216     return pltfm_host->clock / 256 / 16;
0217 }
0218
0219 static void esdhc_mcf_pltfm_set_clock(struct sdhci_host *host,
0220                       unsigned int clock)
0221 {
0222     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0223     unsigned long *pll_dr = (unsigned long *)MCF_PLL_DR;
0224     u32 fvco, fsys, fesdhc, temp;
0225     const int sdclkfs[] = {2, 4, 8, 16, 32, 64, 128, 256};
0226     int delta, old_delta = clock;
0227     int i, q, ri, rq;
0228
0229     if (clock == 0) {
0230         host->mmc->actual_clock = 0;
0231         return;
0232     }
0233
0234     /*
0235      * ColdFire eSDHC clock.s
0236      *
0237      * pll -+-> / outdiv1 --> fsys
0238      *      +-> / outdiv3 --> eSDHC clock ---> / SDCCLKFS / DVS
0239      *
0240      * mcf5441x datasheet says:
0241      * (8.1.2) eSDHC should be 40 MHz max
0242      * (25.3.9) eSDHC input is, as example, 96 Mhz ...
0243      * (25.3.9) sd pin clock must never exceed 25Mhz
0244      *
0245      * fvco = fsys * outdvi1 + 1
0246      * fshdc = fvco / outdiv3 + 1
0247      */
0248     temp = readl(pll_dr);
0249     fsys = pltfm_host->clock;
0250     fvco = fsys * ((temp & 0x1f) + 1);
0251     fesdhc = fvco / (((temp >> 10) & 0x1f) + 1);
0252
0253     for (i = 0; i < 8; ++i) {
0254         int result = fesdhc / sdclkfs[i];
0255
0256         for (q = 1; q < 17; ++q) {
0257             int finale = result / q;
0258
0259             delta = abs(clock - finale);
0260
0261             if (delta < old_delta) {
0262                 old_delta = delta;
0263                 ri = i;
0264                 rq = q;
0265             }
0266         }
0267     }
0268
0269     /*
0270      * Apply divisors and re-enable all the clocks
0271      */
0272     temp = ((sdclkfs[ri] >> 1) << 8) | ((rq - 1) << 4) |
0273         (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN);
0274     esdhc_clrset_be(host, 0x0000fff7, temp, SDHCI_CLOCK_CONTROL);
0275
0276     host->mmc->actual_clock = clock;
0277
0278     mdelay(1);
0279 }
0280
0281 static void esdhc_mcf_pltfm_set_bus_width(struct sdhci_host *host, int width)
0282 {
0283     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0284     struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
0285
0286     switch (width) {
0287     case MMC_BUS_WIDTH_4:
0288         mcf_data->current_bus_width = ESDHC_CTRL_4BITBUS;
0289         break;
0290     default:
0291         mcf_data->current_bus_width = 0;
0292         break;
0293     }
0294
0295     esdhc_clrset_be(host, ESDHC_CTRL_BUSWIDTH_MASK,
0296             mcf_data->current_bus_width, SDHCI_HOST_CONTROL);
0297 }
0298
0299 static void esdhc_mcf_request_done(struct sdhci_host *host,
0300                    struct mmc_request *mrq)
0301 {
0302     struct scatterlist *sg;
0303     u32 *buffer;
0304     int i;
0305
0306     if (!mrq->data || !mrq->data->bytes_xfered)
0307         goto exit_done;
0308
0309     if (mmc_get_dma_dir(mrq->data) != DMA_FROM_DEVICE)
0310         goto exit_done;
0311
0312     /*
0313      * On mcf5441x there is no hw sdma option/flag to select the dma
0314      * transfer endiannes. A swap after the transfer is needed.
0315      */
0316     for_each_sg(mrq->data->sg, sg, mrq->data->sg_len, i) {
0317         buffer = (u32 *)sg_virt(sg);
0318         esdhc_mcf_buffer_swap32(buffer, sg->length);
0319     }
0320
0321 exit_done:
0322     mmc_request_done(host->mmc, mrq);
0323 }
0324
0325 static void esdhc_mcf_copy_to_bounce_buffer(struct sdhci_host *host,
0326                         struct mmc_data *data,
0327                         unsigned int length)
0328 {
0329     sg_copy_to_buffer(data->sg, data->sg_len,
0330               host->bounce_buffer, length);
0331
0332     esdhc_mcf_buffer_swap32((u32 *)host->bounce_buffer,
0333                 data->blksz * data->blocks);
0334 }
0335
0336 static struct sdhci_ops sdhci_esdhc_ops = {
0337     .reset = esdhc_mcf_reset,
0338     .set_clock = esdhc_mcf_pltfm_set_clock,
0339     .get_max_clock = esdhc_mcf_pltfm_get_max_clock,
0340     .get_min_clock = esdhc_mcf_pltfm_get_min_clock,
0341     .set_bus_width = esdhc_mcf_pltfm_set_bus_width,
0342     .get_max_timeout_count = esdhc_mcf_get_max_timeout_count,
0343     .set_timeout = esdhc_mcf_set_timeout,
0344     .write_b = esdhc_mcf_writeb_be,
0345     .write_w = esdhc_mcf_writew_be,
0346     .write_l = esdhc_mcf_writel_be,
0347     .read_b = esdhc_mcf_readb_be,
0348     .read_w = esdhc_mcf_readw_be,
0349     .read_l = esdhc_mcf_readl_be,
0350     .copy_to_bounce_buffer = esdhc_mcf_copy_to_bounce_buffer,
0351     .request_done = esdhc_mcf_request_done,
0352 };
0353
0354 static const struct sdhci_pltfm_data sdhci_esdhc_mcf_pdata = {
0355     .ops = &sdhci_esdhc_ops,
0356     .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_FORCE_DMA,
0357          /*
0358           * Mandatory quirk,
0359           * controller does not support cmd23,
0360           * without, on > 8G cards cmd23 is used, and
0361           * driver times out.
0362           */
0363           SDHCI_QUIRK2_HOST_NO_CMD23,
0364 };
0365
0366 static int esdhc_mcf_plat_init(struct sdhci_host *host,
0367                    struct pltfm_mcf_data *mcf_data)
0368 {
0369     struct mcf_esdhc_platform_data *plat_data;
0370     struct device *dev = mmc_dev(host->mmc);
0371
0372     if (!dev->platform_data) {
0373         dev_err(dev, "no platform data!\n");
0374         return -EINVAL;
0375     }
0376
0377     plat_data = (struct mcf_esdhc_platform_data *)dev->platform_data;
0378
0379     /* Card_detect */
0380     switch (plat_data->cd_type) {
0381     default:
0382     case ESDHC_CD_CONTROLLER:
0383         /* We have a working card_detect back */
0384         host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
0385         break;
0386     case ESDHC_CD_PERMANENT:
0387         host->mmc->caps |= MMC_CAP_NONREMOVABLE;
0388         break;
0389     case ESDHC_CD_NONE:
0390         break;
0391     }
0392
0393     switch (plat_data->max_bus_width) {
0394     case 4:
0395         host->mmc->caps |= MMC_CAP_4_BIT_DATA;
0396         break;
0397     case 1:
0398     default:
0399         host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
0400         break;
0401     }
0402
0403     return 0;
0404 }
0405
0406 static int sdhci_esdhc_mcf_probe(struct platform_device *pdev)
0407 {
0408     struct sdhci_host *host;
0409     struct sdhci_pltfm_host *pltfm_host;
0410     struct pltfm_mcf_data *mcf_data;
0411     int err;
0412
0413     host = sdhci_pltfm_init(pdev, &sdhci_esdhc_mcf_pdata,
0414                 sizeof(*mcf_data));
0415
0416     if (IS_ERR(host))
0417         return PTR_ERR(host);
0418
0419     pltfm_host = sdhci_priv(host);
0420     mcf_data = sdhci_pltfm_priv(pltfm_host);
0421
0422     host->sdma_boundary = 0;
0423
0424     host->flags |= SDHCI_AUTO_CMD12;
0425
0426     mcf_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
0427     if (IS_ERR(mcf_data->clk_ipg)) {
0428         err = PTR_ERR(mcf_data->clk_ipg);
0429         goto err_exit;
0430     }
0431
0432     mcf_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
0433     if (IS_ERR(mcf_data->clk_ahb)) {
0434         err = PTR_ERR(mcf_data->clk_ahb);
0435         goto err_exit;
0436     }
0437
0438     mcf_data->clk_per = devm_clk_get(&pdev->dev, "per");
0439     if (IS_ERR(mcf_data->clk_per)) {
0440         err = PTR_ERR(mcf_data->clk_per);
0441         goto err_exit;
0442     }
0443
0444     pltfm_host->clk = mcf_data->clk_per;
0445     pltfm_host->clock = clk_get_rate(pltfm_host->clk);
0446     err = clk_prepare_enable(mcf_data->clk_per);
0447     if (err)
0448         goto err_exit;
0449
0450     err = clk_prepare_enable(mcf_data->clk_ipg);
0451     if (err)
0452         goto unprep_per;
0453
0454     err = clk_prepare_enable(mcf_data->clk_ahb);
0455     if (err)
0456         goto unprep_ipg;
0457
0458     err = esdhc_mcf_plat_init(host, mcf_data);
0459     if (err)
0460         goto unprep_ahb;
0461
0462     err = sdhci_setup_host(host);
0463     if (err)
0464         goto unprep_ahb;
0465
0466     if (!host->bounce_buffer) {
0467         dev_err(&pdev->dev, "bounce buffer not allocated");
0468         err = -ENOMEM;
0469         goto cleanup;
0470     }
0471
0472     err = __sdhci_add_host(host);
0473     if (err)
0474         goto cleanup;
0475
0476     return 0;
0477
0478 cleanup:
0479     sdhci_cleanup_host(host);
0480 unprep_ahb:
0481     clk_disable_unprepare(mcf_data->clk_ahb);
0482 unprep_ipg:
0483     clk_disable_unprepare(mcf_data->clk_ipg);
0484 unprep_per:
0485     clk_disable_unprepare(mcf_data->clk_per);
0486 err_exit:
0487     sdhci_pltfm_free(pdev);
0488
0489     return err;
0490 }
0491
0492 static int sdhci_esdhc_mcf_remove(struct platform_device *pdev)
0493 {
0494     struct sdhci_host *host = platform_get_drvdata(pdev);
0495     struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0496     struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
0497
0498     sdhci_remove_host(host, 0);
0499
0500     clk_disable_unprepare(mcf_data->clk_ipg);
0501     clk_disable_unprepare(mcf_data->clk_ahb);
0502     clk_disable_unprepare(mcf_data->clk_per);
0503
0504     sdhci_pltfm_free(pdev);
0505
0506     return 0;
0507 }
0508
0509 static struct platform_driver sdhci_esdhc_mcf_driver = {
0510     .driver = {
0511         .name = "sdhci-esdhc-mcf",
0512         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0513     },
0514     .probe = sdhci_esdhc_mcf_probe,
0515     .remove = sdhci_esdhc_mcf_remove,
0516 };
0517
0518 module_platform_driver(sdhci_esdhc_mcf_driver);
0519
0520 MODULE_DESCRIPTION("SDHCI driver for Freescale ColdFire eSDHC");
0521 MODULE_AUTHOR("Angelo Dureghello <angelo.dureghello@timesys.com>");
0522 MODULE_LICENSE("GPL v2");