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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Secure Digital Host Controller Interface ACPI driver.
0004  *
0005  * Copyright (c) 2012, Intel Corporation.
0006  */
0007 
0008 #include <linux/bitfield.h>
0009 #include <linux/init.h>
0010 #include <linux/export.h>
0011 #include <linux/module.h>
0012 #include <linux/device.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/ioport.h>
0015 #include <linux/io.h>
0016 #include <linux/dma-mapping.h>
0017 #include <linux/compiler.h>
0018 #include <linux/stddef.h>
0019 #include <linux/bitops.h>
0020 #include <linux/types.h>
0021 #include <linux/err.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/acpi.h>
0024 #include <linux/pm.h>
0025 #include <linux/pm_runtime.h>
0026 #include <linux/delay.h>
0027 #include <linux/dmi.h>
0028 
0029 #include <linux/mmc/host.h>
0030 #include <linux/mmc/pm.h>
0031 #include <linux/mmc/slot-gpio.h>
0032 
0033 #ifdef CONFIG_X86
0034 #include <linux/platform_data/x86/soc.h>
0035 #include <asm/iosf_mbi.h>
0036 #endif
0037 
0038 #include "sdhci.h"
0039 
0040 enum {
0041     SDHCI_ACPI_SD_CD        = BIT(0),
0042     SDHCI_ACPI_RUNTIME_PM       = BIT(1),
0043     SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = BIT(2),
0044 };
0045 
0046 struct sdhci_acpi_chip {
0047     const struct    sdhci_ops *ops;
0048     unsigned int    quirks;
0049     unsigned int    quirks2;
0050     unsigned long   caps;
0051     unsigned int    caps2;
0052     mmc_pm_flag_t   pm_caps;
0053 };
0054 
0055 struct sdhci_acpi_slot {
0056     const struct    sdhci_acpi_chip *chip;
0057     unsigned int    quirks;
0058     unsigned int    quirks2;
0059     unsigned long   caps;
0060     unsigned int    caps2;
0061     mmc_pm_flag_t   pm_caps;
0062     unsigned int    flags;
0063     size_t      priv_size;
0064     int (*probe_slot)(struct platform_device *, struct acpi_device *);
0065     int (*remove_slot)(struct platform_device *);
0066     int (*free_slot)(struct platform_device *pdev);
0067     int (*setup_host)(struct platform_device *pdev);
0068 };
0069 
0070 struct sdhci_acpi_host {
0071     struct sdhci_host       *host;
0072     const struct sdhci_acpi_slot    *slot;
0073     struct platform_device      *pdev;
0074     bool                use_runtime_pm;
0075     bool                is_intel;
0076     bool                reset_signal_volt_on_suspend;
0077     unsigned long           private[] ____cacheline_aligned;
0078 };
0079 
0080 enum {
0081     DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP          = BIT(0),
0082     DMI_QUIRK_SD_NO_WRITE_PROTECT               = BIT(1),
0083 };
0084 
0085 static inline void *sdhci_acpi_priv(struct sdhci_acpi_host *c)
0086 {
0087     return (void *)c->private;
0088 }
0089 
0090 static inline bool sdhci_acpi_flag(struct sdhci_acpi_host *c, unsigned int flag)
0091 {
0092     return c->slot && (c->slot->flags & flag);
0093 }
0094 
0095 #define INTEL_DSM_HS_CAPS_SDR25     BIT(0)
0096 #define INTEL_DSM_HS_CAPS_DDR50     BIT(1)
0097 #define INTEL_DSM_HS_CAPS_SDR50     BIT(2)
0098 #define INTEL_DSM_HS_CAPS_SDR104    BIT(3)
0099 
0100 enum {
0101     INTEL_DSM_FNS       =  0,
0102     INTEL_DSM_V18_SWITCH    =  3,
0103     INTEL_DSM_V33_SWITCH    =  4,
0104     INTEL_DSM_HS_CAPS   =  8,
0105 };
0106 
0107 struct intel_host {
0108     u32 dsm_fns;
0109     u32 hs_caps;
0110 };
0111 
0112 static const guid_t intel_dsm_guid =
0113     GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
0114           0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
0115 
0116 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
0117                unsigned int fn, u32 *result)
0118 {
0119     union acpi_object *obj;
0120     int err = 0;
0121 
0122     obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
0123     if (!obj)
0124         return -EOPNOTSUPP;
0125 
0126     if (obj->type == ACPI_TYPE_INTEGER) {
0127         *result = obj->integer.value;
0128     } else if (obj->type == ACPI_TYPE_BUFFER && obj->buffer.length > 0) {
0129         size_t len = min_t(size_t, obj->buffer.length, 4);
0130 
0131         *result = 0;
0132         memcpy(result, obj->buffer.pointer, len);
0133     } else {
0134         dev_err(dev, "%s DSM fn %u obj->type %d obj->buffer.length %d\n",
0135             __func__, fn, obj->type, obj->buffer.length);
0136         err = -EINVAL;
0137     }
0138 
0139     ACPI_FREE(obj);
0140 
0141     return err;
0142 }
0143 
0144 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
0145              unsigned int fn, u32 *result)
0146 {
0147     if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
0148         return -EOPNOTSUPP;
0149 
0150     return __intel_dsm(intel_host, dev, fn, result);
0151 }
0152 
0153 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
0154                struct mmc_host *mmc)
0155 {
0156     int err;
0157 
0158     intel_host->hs_caps = ~0;
0159 
0160     err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
0161     if (err) {
0162         pr_debug("%s: DSM not supported, error %d\n",
0163              mmc_hostname(mmc), err);
0164         return;
0165     }
0166 
0167     pr_debug("%s: DSM function mask %#x\n",
0168          mmc_hostname(mmc), intel_host->dsm_fns);
0169 
0170     intel_dsm(intel_host, dev, INTEL_DSM_HS_CAPS, &intel_host->hs_caps);
0171 }
0172 
0173 static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
0174                          struct mmc_ios *ios)
0175 {
0176     struct device *dev = mmc_dev(mmc);
0177     struct sdhci_acpi_host *c = dev_get_drvdata(dev);
0178     struct intel_host *intel_host = sdhci_acpi_priv(c);
0179     unsigned int fn;
0180     u32 result = 0;
0181     int err;
0182 
0183     err = sdhci_start_signal_voltage_switch(mmc, ios);
0184     if (err)
0185         return err;
0186 
0187     switch (ios->signal_voltage) {
0188     case MMC_SIGNAL_VOLTAGE_330:
0189         fn = INTEL_DSM_V33_SWITCH;
0190         break;
0191     case MMC_SIGNAL_VOLTAGE_180:
0192         fn = INTEL_DSM_V18_SWITCH;
0193         break;
0194     default:
0195         return 0;
0196     }
0197 
0198     err = intel_dsm(intel_host, dev, fn, &result);
0199     pr_debug("%s: %s DSM fn %u error %d result %u\n",
0200          mmc_hostname(mmc), __func__, fn, err, result);
0201 
0202     return 0;
0203 }
0204 
0205 static void sdhci_acpi_int_hw_reset(struct sdhci_host *host)
0206 {
0207     u8 reg;
0208 
0209     reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
0210     reg |= 0x10;
0211     sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
0212     /* For eMMC, minimum is 1us but give it 9us for good measure */
0213     udelay(9);
0214     reg &= ~0x10;
0215     sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
0216     /* For eMMC, minimum is 200us but give it 300us for good measure */
0217     usleep_range(300, 1000);
0218 }
0219 
0220 static const struct sdhci_ops sdhci_acpi_ops_dflt = {
0221     .set_clock = sdhci_set_clock,
0222     .set_bus_width = sdhci_set_bus_width,
0223     .reset = sdhci_reset,
0224     .set_uhs_signaling = sdhci_set_uhs_signaling,
0225 };
0226 
0227 static const struct sdhci_ops sdhci_acpi_ops_int = {
0228     .set_clock = sdhci_set_clock,
0229     .set_bus_width = sdhci_set_bus_width,
0230     .reset = sdhci_reset,
0231     .set_uhs_signaling = sdhci_set_uhs_signaling,
0232     .hw_reset   = sdhci_acpi_int_hw_reset,
0233 };
0234 
0235 static const struct sdhci_acpi_chip sdhci_acpi_chip_int = {
0236     .ops = &sdhci_acpi_ops_int,
0237 };
0238 
0239 #ifdef CONFIG_X86
0240 
0241 #define BYT_IOSF_SCCEP          0x63
0242 #define BYT_IOSF_OCP_NETCTRL0       0x1078
0243 #define BYT_IOSF_OCP_TIMEOUT_BASE   GENMASK(10, 8)
0244 
0245 static void sdhci_acpi_byt_setting(struct device *dev)
0246 {
0247     u32 val = 0;
0248 
0249     if (!soc_intel_is_byt())
0250         return;
0251 
0252     if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
0253               &val)) {
0254         dev_err(dev, "%s read error\n", __func__);
0255         return;
0256     }
0257 
0258     if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
0259         return;
0260 
0261     val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
0262 
0263     if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
0264                val)) {
0265         dev_err(dev, "%s write error\n", __func__);
0266         return;
0267     }
0268 
0269     dev_dbg(dev, "%s completed\n", __func__);
0270 }
0271 
0272 static bool sdhci_acpi_byt_defer(struct device *dev)
0273 {
0274     if (!soc_intel_is_byt())
0275         return false;
0276 
0277     if (!iosf_mbi_available())
0278         return true;
0279 
0280     sdhci_acpi_byt_setting(dev);
0281 
0282     return false;
0283 }
0284 
0285 #else
0286 
0287 static inline void sdhci_acpi_byt_setting(struct device *dev)
0288 {
0289 }
0290 
0291 static inline bool sdhci_acpi_byt_defer(struct device *dev)
0292 {
0293     return false;
0294 }
0295 
0296 #endif
0297 
0298 static int bxt_get_cd(struct mmc_host *mmc)
0299 {
0300     int gpio_cd = mmc_gpio_get_cd(mmc);
0301 
0302     if (!gpio_cd)
0303         return 0;
0304 
0305     return sdhci_get_cd_nogpio(mmc);
0306 }
0307 
0308 static int intel_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
0309 {
0310     struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
0311     struct intel_host *intel_host = sdhci_acpi_priv(c);
0312     struct sdhci_host *host = c->host;
0313 
0314     if (acpi_dev_hid_uid_match(adev, "80860F14", "1") &&
0315         sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
0316         sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807)
0317         host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
0318 
0319     if (acpi_dev_hid_uid_match(adev, "80865ACA", NULL))
0320         host->mmc_host_ops.get_cd = bxt_get_cd;
0321 
0322     intel_dsm_init(intel_host, &pdev->dev, host->mmc);
0323 
0324     host->mmc_host_ops.start_signal_voltage_switch =
0325                     intel_start_signal_voltage_switch;
0326 
0327     c->is_intel = true;
0328 
0329     return 0;
0330 }
0331 
0332 static int intel_setup_host(struct platform_device *pdev)
0333 {
0334     struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
0335     struct intel_host *intel_host = sdhci_acpi_priv(c);
0336 
0337     if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR25))
0338         c->host->mmc->caps &= ~MMC_CAP_UHS_SDR25;
0339 
0340     if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR50))
0341         c->host->mmc->caps &= ~MMC_CAP_UHS_SDR50;
0342 
0343     if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_DDR50))
0344         c->host->mmc->caps &= ~MMC_CAP_UHS_DDR50;
0345 
0346     if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR104))
0347         c->host->mmc->caps &= ~MMC_CAP_UHS_SDR104;
0348 
0349     return 0;
0350 }
0351 
0352 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = {
0353     .chip    = &sdhci_acpi_chip_int,
0354     .caps    = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
0355            MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
0356            MMC_CAP_CMD_DURING_TFR | MMC_CAP_WAIT_WHILE_BUSY,
0357     .flags   = SDHCI_ACPI_RUNTIME_PM,
0358     .quirks  = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
0359            SDHCI_QUIRK_NO_LED,
0360     .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
0361            SDHCI_QUIRK2_STOP_WITH_TC |
0362            SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
0363     .probe_slot = intel_probe_slot,
0364     .setup_host = intel_setup_host,
0365     .priv_size  = sizeof(struct intel_host),
0366 };
0367 
0368 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
0369     .quirks  = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
0370            SDHCI_QUIRK_NO_LED |
0371            SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
0372     .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
0373     .caps    = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD |
0374            MMC_CAP_WAIT_WHILE_BUSY,
0375     .flags   = SDHCI_ACPI_RUNTIME_PM,
0376     .pm_caps = MMC_PM_KEEP_POWER,
0377     .probe_slot = intel_probe_slot,
0378     .setup_host = intel_setup_host,
0379     .priv_size  = sizeof(struct intel_host),
0380 };
0381 
0382 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = {
0383     .flags   = SDHCI_ACPI_SD_CD | SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL |
0384            SDHCI_ACPI_RUNTIME_PM,
0385     .quirks  = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
0386            SDHCI_QUIRK_NO_LED,
0387     .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
0388            SDHCI_QUIRK2_STOP_WITH_TC,
0389     .caps    = MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_AGGRESSIVE_PM,
0390     .probe_slot = intel_probe_slot,
0391     .setup_host = intel_setup_host,
0392     .priv_size  = sizeof(struct intel_host),
0393 };
0394 
0395 #define VENDOR_SPECIFIC_PWRCTL_CLEAR_REG    0x1a8
0396 #define VENDOR_SPECIFIC_PWRCTL_CTL_REG      0x1ac
0397 static irqreturn_t sdhci_acpi_qcom_handler(int irq, void *ptr)
0398 {
0399     struct sdhci_host *host = ptr;
0400 
0401     sdhci_writel(host, 0x3, VENDOR_SPECIFIC_PWRCTL_CLEAR_REG);
0402     sdhci_writel(host, 0x1, VENDOR_SPECIFIC_PWRCTL_CTL_REG);
0403 
0404     return IRQ_HANDLED;
0405 }
0406 
0407 static int qcom_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
0408 {
0409     struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
0410     struct sdhci_host *host = c->host;
0411     int *irq = sdhci_acpi_priv(c);
0412 
0413     *irq = -EINVAL;
0414 
0415     if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
0416         return 0;
0417 
0418     *irq = platform_get_irq(pdev, 1);
0419     if (*irq < 0)
0420         return 0;
0421 
0422     return request_threaded_irq(*irq, NULL, sdhci_acpi_qcom_handler,
0423                     IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
0424                     "sdhci_qcom", host);
0425 }
0426 
0427 static int qcom_free_slot(struct platform_device *pdev)
0428 {
0429     struct device *dev = &pdev->dev;
0430     struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
0431     struct sdhci_host *host = c->host;
0432     struct acpi_device *adev;
0433     int *irq = sdhci_acpi_priv(c);
0434 
0435     adev = ACPI_COMPANION(dev);
0436     if (!adev)
0437         return -ENODEV;
0438 
0439     if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
0440         return 0;
0441 
0442     if (*irq < 0)
0443         return 0;
0444 
0445     free_irq(*irq, host);
0446     return 0;
0447 }
0448 
0449 static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd_3v = {
0450     .quirks  = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
0451     .quirks2 = SDHCI_QUIRK2_NO_1_8_V,
0452     .caps    = MMC_CAP_NONREMOVABLE,
0453     .priv_size  = sizeof(int),
0454     .probe_slot = qcom_probe_slot,
0455     .free_slot  = qcom_free_slot,
0456 };
0457 
0458 static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd = {
0459     .quirks  = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
0460     .caps    = MMC_CAP_NONREMOVABLE,
0461 };
0462 
0463 struct amd_sdhci_host {
0464     bool    tuned_clock;
0465     bool    dll_enabled;
0466 };
0467 
0468 /* AMD sdhci reset dll register. */
0469 #define SDHCI_AMD_RESET_DLL_REGISTER    0x908
0470 
0471 static int amd_select_drive_strength(struct mmc_card *card,
0472                      unsigned int max_dtr, int host_drv,
0473                      int card_drv, int *host_driver_strength)
0474 {
0475     struct sdhci_host *host = mmc_priv(card->host);
0476     u16 preset, preset_driver_strength;
0477 
0478     /*
0479      * This method is only called by mmc_select_hs200 so we only need to
0480      * read from the HS200 (SDR104) preset register.
0481      *
0482      * Firmware that has "invalid/default" presets return a driver strength
0483      * of A. This matches the previously hard coded value.
0484      */
0485     preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
0486     preset_driver_strength = FIELD_GET(SDHCI_PRESET_DRV_MASK, preset);
0487 
0488     /*
0489      * We want the controller driver strength to match the card's driver
0490      * strength so they have similar rise/fall times.
0491      *
0492      * The controller driver strength set by this method is sticky for all
0493      * timings after this method is called. This unfortunately means that
0494      * while HS400 tuning is in progress we end up with mismatched driver
0495      * strengths between the controller and the card. HS400 tuning requires
0496      * switching from HS400->DDR52->HS->HS200->HS400. So the driver mismatch
0497      * happens while in DDR52 and HS modes. This has not been observed to
0498      * cause problems. Enabling presets would fix this issue.
0499      */
0500     *host_driver_strength = preset_driver_strength;
0501 
0502     /*
0503      * The resulting card driver strength is only set when switching the
0504      * card's timing to HS200 or HS400. The card will use the default driver
0505      * strength (B) for any other mode.
0506      */
0507     return preset_driver_strength;
0508 }
0509 
0510 static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host, bool enable)
0511 {
0512     struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
0513     struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
0514 
0515     /* AMD Platform requires dll setting */
0516     sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER);
0517     usleep_range(10, 20);
0518     if (enable)
0519         sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER);
0520 
0521     amd_host->dll_enabled = enable;
0522 }
0523 
0524 /*
0525  * The initialization sequence for HS400 is:
0526  *     HS->HS200->Perform Tuning->HS->HS400
0527  *
0528  * The re-tuning sequence is:
0529  *     HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
0530  *
0531  * The AMD eMMC Controller can only use the tuned clock while in HS200 and HS400
0532  * mode. If we switch to a different mode, we need to disable the tuned clock.
0533  * If we have previously performed tuning and switch back to HS200 or
0534  * HS400, we can re-enable the tuned clock.
0535  *
0536  */
0537 static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
0538 {
0539     struct sdhci_host *host = mmc_priv(mmc);
0540     struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
0541     struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
0542     unsigned int old_timing = host->timing;
0543     u16 val;
0544 
0545     sdhci_set_ios(mmc, ios);
0546 
0547     if (old_timing != host->timing && amd_host->tuned_clock) {
0548         if (host->timing == MMC_TIMING_MMC_HS400 ||
0549             host->timing == MMC_TIMING_MMC_HS200) {
0550             val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
0551             val |= SDHCI_CTRL_TUNED_CLK;
0552             sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
0553         } else {
0554             val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
0555             val &= ~SDHCI_CTRL_TUNED_CLK;
0556             sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
0557         }
0558 
0559         /* DLL is only required for HS400 */
0560         if (host->timing == MMC_TIMING_MMC_HS400 &&
0561             !amd_host->dll_enabled)
0562             sdhci_acpi_amd_hs400_dll(host, true);
0563     }
0564 }
0565 
0566 static int amd_sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
0567 {
0568     int err;
0569     struct sdhci_host *host = mmc_priv(mmc);
0570     struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
0571     struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
0572 
0573     amd_host->tuned_clock = false;
0574 
0575     err = sdhci_execute_tuning(mmc, opcode);
0576 
0577     if (!err && !host->tuning_err)
0578         amd_host->tuned_clock = true;
0579 
0580     return err;
0581 }
0582 
0583 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
0584 {
0585     struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
0586     struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
0587 
0588     if (mask & SDHCI_RESET_ALL) {
0589         amd_host->tuned_clock = false;
0590         sdhci_acpi_amd_hs400_dll(host, false);
0591     }
0592 
0593     sdhci_reset(host, mask);
0594 }
0595 
0596 static const struct sdhci_ops sdhci_acpi_ops_amd = {
0597     .set_clock  = sdhci_set_clock,
0598     .set_bus_width  = sdhci_set_bus_width,
0599     .reset      = amd_sdhci_reset,
0600     .set_uhs_signaling = sdhci_set_uhs_signaling,
0601 };
0602 
0603 static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = {
0604     .ops = &sdhci_acpi_ops_amd,
0605 };
0606 
0607 static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev,
0608                       struct acpi_device *adev)
0609 {
0610     struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
0611     struct sdhci_host *host   = c->host;
0612 
0613     sdhci_read_caps(host);
0614     if (host->caps1 & SDHCI_SUPPORT_DDR50)
0615         host->mmc->caps = MMC_CAP_1_8V_DDR;
0616 
0617     if ((host->caps1 & SDHCI_SUPPORT_SDR104) &&
0618         (host->mmc->caps & MMC_CAP_1_8V_DDR))
0619         host->mmc->caps2 = MMC_CAP2_HS400_1_8V;
0620 
0621     /*
0622      * There are two types of presets out in the wild:
0623      * 1) Default/broken presets.
0624      *    These presets have two sets of problems:
0625      *    a) The clock divisor for SDR12, SDR25, and SDR50 is too small.
0626      *       This results in clock frequencies that are 2x higher than
0627      *       acceptable. i.e., SDR12 = 25 MHz, SDR25 = 50 MHz, SDR50 =
0628      *       100 MHz.x
0629      *    b) The HS200 and HS400 driver strengths don't match.
0630      *       By default, the SDR104 preset register has a driver strength of
0631      *       A, but the (internal) HS400 preset register has a driver
0632      *       strength of B. As part of initializing HS400, HS200 tuning
0633      *       needs to be performed. Having different driver strengths
0634      *       between tuning and operation is wrong. It results in different
0635      *       rise/fall times that lead to incorrect sampling.
0636      * 2) Firmware with properly initialized presets.
0637      *    These presets have proper clock divisors. i.e., SDR12 => 12MHz,
0638      *    SDR25 => 25 MHz, SDR50 => 50 MHz. Additionally the HS200 and
0639      *    HS400 preset driver strengths match.
0640      *
0641      *    Enabling presets for HS400 doesn't work for the following reasons:
0642      *    1) sdhci_set_ios has a hard coded list of timings that are used
0643      *       to determine if presets should be enabled.
0644      *    2) sdhci_get_preset_value is using a non-standard register to
0645      *       read out HS400 presets. The AMD controller doesn't support this
0646      *       non-standard register. In fact, it doesn't expose the HS400
0647      *       preset register anywhere in the SDHCI memory map. This results
0648      *       in reading a garbage value and using the wrong presets.
0649      *
0650      *       Since HS400 and HS200 presets must be identical, we could
0651      *       instead use the the SDR104 preset register.
0652      *
0653      *    If the above issues are resolved we could remove this quirk for
0654      *    firmware that that has valid presets (i.e., SDR12 <= 12 MHz).
0655      */
0656     host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
0657 
0658     host->mmc_host_ops.select_drive_strength = amd_select_drive_strength;
0659     host->mmc_host_ops.set_ios = amd_set_ios;
0660     host->mmc_host_ops.execute_tuning = amd_sdhci_execute_tuning;
0661     return 0;
0662 }
0663 
0664 static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = {
0665     .chip       = &sdhci_acpi_chip_amd,
0666     .caps       = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
0667     .quirks     = SDHCI_QUIRK_32BIT_DMA_ADDR |
0668               SDHCI_QUIRK_32BIT_DMA_SIZE |
0669               SDHCI_QUIRK_32BIT_ADMA_SIZE,
0670     .quirks2    = SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
0671     .probe_slot     = sdhci_acpi_emmc_amd_probe_slot,
0672     .priv_size  = sizeof(struct amd_sdhci_host),
0673 };
0674 
0675 struct sdhci_acpi_uid_slot {
0676     const char *hid;
0677     const char *uid;
0678     const struct sdhci_acpi_slot *slot;
0679 };
0680 
0681 static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = {
0682     { "80865ACA", NULL, &sdhci_acpi_slot_int_sd },
0683     { "80865ACC", NULL, &sdhci_acpi_slot_int_emmc },
0684     { "80865AD0", NULL, &sdhci_acpi_slot_int_sdio },
0685     { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc },
0686     { "80860F14" , "2" , &sdhci_acpi_slot_int_sdio },
0687     { "80860F14" , "3" , &sdhci_acpi_slot_int_sd   },
0688     { "80860F16" , NULL, &sdhci_acpi_slot_int_sd   },
0689     { "INT33BB"  , "2" , &sdhci_acpi_slot_int_sdio },
0690     { "INT33BB"  , "3" , &sdhci_acpi_slot_int_sd },
0691     { "INT33C6"  , NULL, &sdhci_acpi_slot_int_sdio },
0692     { "INT3436"  , NULL, &sdhci_acpi_slot_int_sdio },
0693     { "INT344D"  , NULL, &sdhci_acpi_slot_int_sdio },
0694     { "PNP0FFF"  , "3" , &sdhci_acpi_slot_int_sd   },
0695     { "PNP0D40"  },
0696     { "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v },
0697     { "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
0698     { "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
0699     { "AMDI0041", NULL, &sdhci_acpi_slot_amd_emmc },
0700     { },
0701 };
0702 
0703 static const struct acpi_device_id sdhci_acpi_ids[] = {
0704     { "80865ACA" },
0705     { "80865ACC" },
0706     { "80865AD0" },
0707     { "80860F14" },
0708     { "80860F16" },
0709     { "INT33BB"  },
0710     { "INT33C6"  },
0711     { "INT3436"  },
0712     { "INT344D"  },
0713     { "PNP0D40"  },
0714     { "QCOM8051" },
0715     { "QCOM8052" },
0716     { "AMDI0040" },
0717     { "AMDI0041" },
0718     { },
0719 };
0720 MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
0721 
0722 static const struct dmi_system_id sdhci_acpi_quirks[] = {
0723     {
0724         /*
0725          * The Lenovo Miix 320-10ICR has a bug in the _PS0 method of
0726          * the SHC1 ACPI device, this bug causes it to reprogram the
0727          * wrong LDO (DLDO3) to 1.8V if 1.8V modes are used and the
0728          * card is (runtime) suspended + resumed. DLDO3 is used for
0729          * the LCD and setting it to 1.8V causes the LCD to go black.
0730          */
0731         .matches = {
0732             DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
0733             DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
0734         },
0735         .driver_data = (void *)DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP,
0736     },
0737     {
0738         /*
0739          * The Acer Aspire Switch 10 (SW5-012) microSD slot always
0740          * reports the card being write-protected even though microSD
0741          * cards do not have a write-protect switch at all.
0742          */
0743         .matches = {
0744             DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
0745             DMI_MATCH(DMI_PRODUCT_NAME, "Aspire SW5-012"),
0746         },
0747         .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
0748     },
0749     {
0750         /*
0751          * The Toshiba WT8-B's microSD slot always reports the card being
0752          * write-protected.
0753          */
0754         .matches = {
0755             DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
0756             DMI_MATCH(DMI_PRODUCT_NAME, "TOSHIBA ENCORE 2 WT8-B"),
0757         },
0758         .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
0759     },
0760     {} /* Terminating entry */
0761 };
0762 
0763 static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(struct acpi_device *adev)
0764 {
0765     const struct sdhci_acpi_uid_slot *u;
0766 
0767     for (u = sdhci_acpi_uids; u->hid; u++) {
0768         if (acpi_dev_hid_uid_match(adev, u->hid, u->uid))
0769             return u->slot;
0770     }
0771     return NULL;
0772 }
0773 
0774 static int sdhci_acpi_probe(struct platform_device *pdev)
0775 {
0776     struct device *dev = &pdev->dev;
0777     const struct sdhci_acpi_slot *slot;
0778     const struct dmi_system_id *id;
0779     struct acpi_device *device;
0780     struct sdhci_acpi_host *c;
0781     struct sdhci_host *host;
0782     struct resource *iomem;
0783     resource_size_t len;
0784     size_t priv_size;
0785     int quirks = 0;
0786     int err;
0787 
0788     device = ACPI_COMPANION(dev);
0789     if (!device)
0790         return -ENODEV;
0791 
0792     id = dmi_first_match(sdhci_acpi_quirks);
0793     if (id)
0794         quirks = (long)id->driver_data;
0795 
0796     slot = sdhci_acpi_get_slot(device);
0797 
0798     /* Power on the SDHCI controller and its children */
0799     acpi_device_fix_up_power_extended(device);
0800 
0801     if (sdhci_acpi_byt_defer(dev))
0802         return -EPROBE_DEFER;
0803 
0804     iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0805     if (!iomem)
0806         return -ENOMEM;
0807 
0808     len = resource_size(iomem);
0809     if (len < 0x100)
0810         dev_err(dev, "Invalid iomem size!\n");
0811 
0812     if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev)))
0813         return -ENOMEM;
0814 
0815     priv_size = slot ? slot->priv_size : 0;
0816     host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size);
0817     if (IS_ERR(host))
0818         return PTR_ERR(host);
0819 
0820     c = sdhci_priv(host);
0821     c->host = host;
0822     c->slot = slot;
0823     c->pdev = pdev;
0824     c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM);
0825 
0826     platform_set_drvdata(pdev, c);
0827 
0828     host->hw_name   = "ACPI";
0829     host->ops   = &sdhci_acpi_ops_dflt;
0830     host->irq   = platform_get_irq(pdev, 0);
0831     if (host->irq < 0) {
0832         err = -EINVAL;
0833         goto err_free;
0834     }
0835 
0836     host->ioaddr = devm_ioremap(dev, iomem->start,
0837                         resource_size(iomem));
0838     if (host->ioaddr == NULL) {
0839         err = -ENOMEM;
0840         goto err_free;
0841     }
0842 
0843     if (c->slot) {
0844         if (c->slot->probe_slot) {
0845             err = c->slot->probe_slot(pdev, device);
0846             if (err)
0847                 goto err_free;
0848         }
0849         if (c->slot->chip) {
0850             host->ops            = c->slot->chip->ops;
0851             host->quirks        |= c->slot->chip->quirks;
0852             host->quirks2       |= c->slot->chip->quirks2;
0853             host->mmc->caps     |= c->slot->chip->caps;
0854             host->mmc->caps2    |= c->slot->chip->caps2;
0855             host->mmc->pm_caps  |= c->slot->chip->pm_caps;
0856         }
0857         host->quirks        |= c->slot->quirks;
0858         host->quirks2       |= c->slot->quirks2;
0859         host->mmc->caps     |= c->slot->caps;
0860         host->mmc->caps2    |= c->slot->caps2;
0861         host->mmc->pm_caps  |= c->slot->pm_caps;
0862     }
0863 
0864     host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
0865 
0866     if (sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD)) {
0867         bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL);
0868 
0869         err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0);
0870         if (err) {
0871             if (err == -EPROBE_DEFER)
0872                 goto err_free;
0873             dev_warn(dev, "failed to setup card detect gpio\n");
0874             c->use_runtime_pm = false;
0875         }
0876 
0877         if (quirks & DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP)
0878             c->reset_signal_volt_on_suspend = true;
0879 
0880         if (quirks & DMI_QUIRK_SD_NO_WRITE_PROTECT)
0881             host->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
0882     }
0883 
0884     err = sdhci_setup_host(host);
0885     if (err)
0886         goto err_free;
0887 
0888     if (c->slot && c->slot->setup_host) {
0889         err = c->slot->setup_host(pdev);
0890         if (err)
0891             goto err_cleanup;
0892     }
0893 
0894     err = __sdhci_add_host(host);
0895     if (err)
0896         goto err_cleanup;
0897 
0898     if (c->use_runtime_pm) {
0899         pm_runtime_set_active(dev);
0900         pm_suspend_ignore_children(dev, 1);
0901         pm_runtime_set_autosuspend_delay(dev, 50);
0902         pm_runtime_use_autosuspend(dev);
0903         pm_runtime_enable(dev);
0904     }
0905 
0906     device_enable_async_suspend(dev);
0907 
0908     return 0;
0909 
0910 err_cleanup:
0911     sdhci_cleanup_host(c->host);
0912 err_free:
0913     if (c->slot && c->slot->free_slot)
0914         c->slot->free_slot(pdev);
0915 
0916     sdhci_free_host(c->host);
0917     return err;
0918 }
0919 
0920 static int sdhci_acpi_remove(struct platform_device *pdev)
0921 {
0922     struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
0923     struct device *dev = &pdev->dev;
0924     int dead;
0925 
0926     if (c->use_runtime_pm) {
0927         pm_runtime_get_sync(dev);
0928         pm_runtime_disable(dev);
0929         pm_runtime_put_noidle(dev);
0930     }
0931 
0932     if (c->slot && c->slot->remove_slot)
0933         c->slot->remove_slot(pdev);
0934 
0935     dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0);
0936     sdhci_remove_host(c->host, dead);
0937 
0938     if (c->slot && c->slot->free_slot)
0939         c->slot->free_slot(pdev);
0940 
0941     sdhci_free_host(c->host);
0942 
0943     return 0;
0944 }
0945 
0946 static void __maybe_unused sdhci_acpi_reset_signal_voltage_if_needed(
0947     struct device *dev)
0948 {
0949     struct sdhci_acpi_host *c = dev_get_drvdata(dev);
0950     struct sdhci_host *host = c->host;
0951 
0952     if (c->is_intel && c->reset_signal_volt_on_suspend &&
0953         host->mmc->ios.signal_voltage != MMC_SIGNAL_VOLTAGE_330) {
0954         struct intel_host *intel_host = sdhci_acpi_priv(c);
0955         unsigned int fn = INTEL_DSM_V33_SWITCH;
0956         u32 result = 0;
0957 
0958         intel_dsm(intel_host, dev, fn, &result);
0959     }
0960 }
0961 
0962 #ifdef CONFIG_PM_SLEEP
0963 
0964 static int sdhci_acpi_suspend(struct device *dev)
0965 {
0966     struct sdhci_acpi_host *c = dev_get_drvdata(dev);
0967     struct sdhci_host *host = c->host;
0968     int ret;
0969 
0970     if (host->tuning_mode != SDHCI_TUNING_MODE_3)
0971         mmc_retune_needed(host->mmc);
0972 
0973     ret = sdhci_suspend_host(host);
0974     if (ret)
0975         return ret;
0976 
0977     sdhci_acpi_reset_signal_voltage_if_needed(dev);
0978     return 0;
0979 }
0980 
0981 static int sdhci_acpi_resume(struct device *dev)
0982 {
0983     struct sdhci_acpi_host *c = dev_get_drvdata(dev);
0984 
0985     sdhci_acpi_byt_setting(&c->pdev->dev);
0986 
0987     return sdhci_resume_host(c->host);
0988 }
0989 
0990 #endif
0991 
0992 #ifdef CONFIG_PM
0993 
0994 static int sdhci_acpi_runtime_suspend(struct device *dev)
0995 {
0996     struct sdhci_acpi_host *c = dev_get_drvdata(dev);
0997     struct sdhci_host *host = c->host;
0998     int ret;
0999 
1000     if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1001         mmc_retune_needed(host->mmc);
1002 
1003     ret = sdhci_runtime_suspend_host(host);
1004     if (ret)
1005         return ret;
1006 
1007     sdhci_acpi_reset_signal_voltage_if_needed(dev);
1008     return 0;
1009 }
1010 
1011 static int sdhci_acpi_runtime_resume(struct device *dev)
1012 {
1013     struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1014 
1015     sdhci_acpi_byt_setting(&c->pdev->dev);
1016 
1017     return sdhci_runtime_resume_host(c->host, 0);
1018 }
1019 
1020 #endif
1021 
1022 static const struct dev_pm_ops sdhci_acpi_pm_ops = {
1023     SET_SYSTEM_SLEEP_PM_OPS(sdhci_acpi_suspend, sdhci_acpi_resume)
1024     SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend,
1025             sdhci_acpi_runtime_resume, NULL)
1026 };
1027 
1028 static struct platform_driver sdhci_acpi_driver = {
1029     .driver = {
1030         .name           = "sdhci-acpi",
1031         .probe_type     = PROBE_PREFER_ASYNCHRONOUS,
1032         .acpi_match_table   = sdhci_acpi_ids,
1033         .pm         = &sdhci_acpi_pm_ops,
1034     },
1035     .probe  = sdhci_acpi_probe,
1036     .remove = sdhci_acpi_remove,
1037 };
1038 
1039 module_platform_driver(sdhci_acpi_driver);
1040 
1041 MODULE_DESCRIPTION("Secure Digital Host Controller Interface ACPI driver");
1042 MODULE_AUTHOR("Adrian Hunter");
1043 MODULE_LICENSE("GPL v2");
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