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0008 enum s3cmci_waitfor {
0009 COMPLETION_NONE,
0010 COMPLETION_FINALIZE,
0011 COMPLETION_CMDSENT,
0012 COMPLETION_RSPFIN,
0013 COMPLETION_XFERFINISH,
0014 COMPLETION_XFERFINISH_RSPFIN,
0015 };
0016
0017 struct s3cmci_host {
0018 struct platform_device *pdev;
0019 struct s3c24xx_mci_pdata *pdata;
0020 struct mmc_host *mmc;
0021 struct resource *mem;
0022 struct clk *clk;
0023 void __iomem *base;
0024 int irq;
0025 int irq_cd;
0026 struct dma_chan *dma;
0027
0028 unsigned long clk_rate;
0029 unsigned long clk_div;
0030 unsigned long real_rate;
0031 u8 prescaler;
0032
0033 int is2440;
0034 unsigned sdiimsk;
0035 unsigned sdidata;
0036
0037 bool irq_disabled;
0038 bool irq_enabled;
0039 bool irq_state;
0040 int sdio_irqen;
0041
0042 struct mmc_request *mrq;
0043 int cmd_is_stop;
0044
0045 spinlock_t complete_lock;
0046 enum s3cmci_waitfor complete_what;
0047
0048 int dma_complete;
0049
0050 u32 pio_sgptr;
0051 u32 pio_bytes;
0052 u32 pio_count;
0053 u32 *pio_ptr;
0054 #define XFER_NONE 0
0055 #define XFER_READ 1
0056 #define XFER_WRITE 2
0057 u32 pio_active;
0058
0059 int bus_width;
0060
0061 char dbgmsg_cmd[301];
0062 char dbgmsg_dat[301];
0063 char *status;
0064
0065 unsigned int ccnt, dcnt;
0066 struct tasklet_struct pio_tasklet;
0067
0068 #ifdef CONFIG_DEBUG_FS
0069 struct dentry *debug_root;
0070 #endif
0071
0072 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
0073 struct notifier_block freq_transition;
0074 #endif
0075 };