Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* Realtek PCI-Express SD/MMC Card Interface driver
0003  *
0004  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
0005  *
0006  * Author:
0007  *   Wei WANG <wei_wang@realsil.com.cn>
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/slab.h>
0012 #include <linux/highmem.h>
0013 #include <linux/delay.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/workqueue.h>
0016 #include <linux/mmc/host.h>
0017 #include <linux/mmc/mmc.h>
0018 #include <linux/mmc/sd.h>
0019 #include <linux/mmc/sdio.h>
0020 #include <linux/mmc/card.h>
0021 #include <linux/rtsx_pci.h>
0022 #include <asm/unaligned.h>
0023 #include <linux/pm_runtime.h>
0024 
0025 struct realtek_pci_sdmmc {
0026     struct platform_device  *pdev;
0027     struct rtsx_pcr     *pcr;
0028     struct mmc_host     *mmc;
0029     struct mmc_request  *mrq;
0030 #define SDMMC_WORKQ_NAME    "rtsx_pci_sdmmc_workq"
0031 
0032     struct work_struct  work;
0033     struct mutex        host_mutex;
0034 
0035     u8          ssc_depth;
0036     unsigned int        clock;
0037     bool            vpclk;
0038     bool            double_clk;
0039     bool            eject;
0040     bool            initial_mode;
0041     int         prev_power_state;
0042     int         sg_count;
0043     s32         cookie;
0044     int         cookie_sg_count;
0045     bool            using_cookie;
0046 };
0047 
0048 static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios);
0049 
0050 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
0051 {
0052     return &(host->pdev->dev);
0053 }
0054 
0055 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
0056 {
0057     rtsx_pci_write_register(host->pcr, CARD_STOP,
0058             SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
0059 }
0060 
0061 #ifdef DEBUG
0062 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
0063 {
0064     u16 len = end - start + 1;
0065     int i;
0066     u8 data[8];
0067 
0068     for (i = 0; i < len; i += 8) {
0069         int j;
0070         int n = min(8, len - i);
0071 
0072         memset(&data, 0, sizeof(data));
0073         for (j = 0; j < n; j++)
0074             rtsx_pci_read_register(host->pcr, start + i + j,
0075                 data + j);
0076         dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
0077             start + i, n, data);
0078     }
0079 }
0080 
0081 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
0082 {
0083     dump_reg_range(host, 0xFDA0, 0xFDB3);
0084     dump_reg_range(host, 0xFD52, 0xFD69);
0085 }
0086 #else
0087 #define sd_print_debug_regs(host)
0088 #endif /* DEBUG */
0089 
0090 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
0091 {
0092     return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
0093 }
0094 
0095 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
0096 {
0097     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
0098         SD_CMD_START | cmd->opcode);
0099     rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
0100 }
0101 
0102 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
0103 {
0104     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
0105     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
0106     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
0107     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
0108 }
0109 
0110 static int sd_response_type(struct mmc_command *cmd)
0111 {
0112     switch (mmc_resp_type(cmd)) {
0113     case MMC_RSP_NONE:
0114         return SD_RSP_TYPE_R0;
0115     case MMC_RSP_R1:
0116         return SD_RSP_TYPE_R1;
0117     case MMC_RSP_R1_NO_CRC:
0118         return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
0119     case MMC_RSP_R1B:
0120         return SD_RSP_TYPE_R1b;
0121     case MMC_RSP_R2:
0122         return SD_RSP_TYPE_R2;
0123     case MMC_RSP_R3:
0124         return SD_RSP_TYPE_R3;
0125     default:
0126         return -EINVAL;
0127     }
0128 }
0129 
0130 static int sd_status_index(int resp_type)
0131 {
0132     if (resp_type == SD_RSP_TYPE_R0)
0133         return 0;
0134     else if (resp_type == SD_RSP_TYPE_R2)
0135         return 16;
0136 
0137     return 5;
0138 }
0139 /*
0140  * sd_pre_dma_transfer - do dma_map_sg() or using cookie
0141  *
0142  * @pre: if called in pre_req()
0143  * return:
0144  *  0 - do dma_map_sg()
0145  *  1 - using cookie
0146  */
0147 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
0148         struct mmc_data *data, bool pre)
0149 {
0150     struct rtsx_pcr *pcr = host->pcr;
0151     int read = data->flags & MMC_DATA_READ;
0152     int count = 0;
0153     int using_cookie = 0;
0154 
0155     if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
0156         dev_err(sdmmc_dev(host),
0157             "error: data->host_cookie = %d, host->cookie = %d\n",
0158             data->host_cookie, host->cookie);
0159         data->host_cookie = 0;
0160     }
0161 
0162     if (pre || data->host_cookie != host->cookie) {
0163         count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
0164     } else {
0165         count = host->cookie_sg_count;
0166         using_cookie = 1;
0167     }
0168 
0169     if (pre) {
0170         host->cookie_sg_count = count;
0171         if (++host->cookie < 0)
0172             host->cookie = 1;
0173         data->host_cookie = host->cookie;
0174     } else {
0175         host->sg_count = count;
0176     }
0177 
0178     return using_cookie;
0179 }
0180 
0181 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
0182 {
0183     struct realtek_pci_sdmmc *host = mmc_priv(mmc);
0184     struct mmc_data *data = mrq->data;
0185 
0186     if (data->host_cookie) {
0187         dev_err(sdmmc_dev(host),
0188             "error: reset data->host_cookie = %d\n",
0189             data->host_cookie);
0190         data->host_cookie = 0;
0191     }
0192 
0193     sd_pre_dma_transfer(host, data, true);
0194     dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
0195 }
0196 
0197 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
0198         int err)
0199 {
0200     struct realtek_pci_sdmmc *host = mmc_priv(mmc);
0201     struct rtsx_pcr *pcr = host->pcr;
0202     struct mmc_data *data = mrq->data;
0203     int read = data->flags & MMC_DATA_READ;
0204 
0205     rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
0206     data->host_cookie = 0;
0207 }
0208 
0209 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
0210         struct mmc_command *cmd)
0211 {
0212     struct rtsx_pcr *pcr = host->pcr;
0213     u8 cmd_idx = (u8)cmd->opcode;
0214     u32 arg = cmd->arg;
0215     int err = 0;
0216     int timeout = 100;
0217     int i;
0218     u8 *ptr;
0219     int rsp_type;
0220     int stat_idx;
0221     bool clock_toggled = false;
0222 
0223     dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
0224             __func__, cmd_idx, arg);
0225 
0226     rsp_type = sd_response_type(cmd);
0227     if (rsp_type < 0)
0228         goto out;
0229 
0230     stat_idx = sd_status_index(rsp_type);
0231 
0232     if (rsp_type == SD_RSP_TYPE_R1b)
0233         timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
0234 
0235     if (cmd->opcode == SD_SWITCH_VOLTAGE) {
0236         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
0237                 0xFF, SD_CLK_TOGGLE_EN);
0238         if (err < 0)
0239             goto out;
0240 
0241         clock_toggled = true;
0242     }
0243 
0244     rtsx_pci_init_cmd(pcr);
0245     sd_cmd_set_sd_cmd(pcr, cmd);
0246     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
0247     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
0248             0x01, PINGPONG_BUFFER);
0249     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
0250             0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
0251     rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
0252              SD_TRANSFER_END | SD_STAT_IDLE,
0253              SD_TRANSFER_END | SD_STAT_IDLE);
0254 
0255     if (rsp_type == SD_RSP_TYPE_R2) {
0256         /* Read data from ping-pong buffer */
0257         for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
0258             rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
0259     } else if (rsp_type != SD_RSP_TYPE_R0) {
0260         /* Read data from SD_CMDx registers */
0261         for (i = SD_CMD0; i <= SD_CMD4; i++)
0262             rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
0263     }
0264 
0265     rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
0266 
0267     err = rtsx_pci_send_cmd(pcr, timeout);
0268     if (err < 0) {
0269         sd_print_debug_regs(host);
0270         sd_clear_error(host);
0271         dev_dbg(sdmmc_dev(host),
0272             "rtsx_pci_send_cmd error (err = %d)\n", err);
0273         goto out;
0274     }
0275 
0276     if (rsp_type == SD_RSP_TYPE_R0) {
0277         err = 0;
0278         goto out;
0279     }
0280 
0281     /* Eliminate returned value of CHECK_REG_CMD */
0282     ptr = rtsx_pci_get_cmd_data(pcr) + 1;
0283 
0284     /* Check (Start,Transmission) bit of Response */
0285     if ((ptr[0] & 0xC0) != 0) {
0286         err = -EILSEQ;
0287         dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
0288         goto out;
0289     }
0290 
0291     /* Check CRC7 */
0292     if (!(rsp_type & SD_NO_CHECK_CRC7)) {
0293         if (ptr[stat_idx] & SD_CRC7_ERR) {
0294             err = -EILSEQ;
0295             dev_dbg(sdmmc_dev(host), "CRC7 error\n");
0296             goto out;
0297         }
0298     }
0299 
0300     if (rsp_type == SD_RSP_TYPE_R2) {
0301         /*
0302          * The controller offloads the last byte {CRC-7, end bit 1'b1}
0303          * of response type R2. Assign dummy CRC, 0, and end bit to the
0304          * byte(ptr[16], goes into the LSB of resp[3] later).
0305          */
0306         ptr[16] = 1;
0307 
0308         for (i = 0; i < 4; i++) {
0309             cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
0310             dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
0311                     i, cmd->resp[i]);
0312         }
0313     } else {
0314         cmd->resp[0] = get_unaligned_be32(ptr + 1);
0315         dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
0316                 cmd->resp[0]);
0317     }
0318 
0319 out:
0320     cmd->error = err;
0321 
0322     if (err && clock_toggled)
0323         rtsx_pci_write_register(pcr, SD_BUS_STAT,
0324                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
0325 }
0326 
0327 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
0328     u16 byte_cnt, u8 *buf, int buf_len, int timeout)
0329 {
0330     struct rtsx_pcr *pcr = host->pcr;
0331     int err;
0332     u8 trans_mode;
0333 
0334     dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
0335         __func__, cmd->opcode, cmd->arg);
0336 
0337     if (!buf)
0338         buf_len = 0;
0339 
0340     if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
0341         trans_mode = SD_TM_AUTO_TUNING;
0342     else
0343         trans_mode = SD_TM_NORMAL_READ;
0344 
0345     rtsx_pci_init_cmd(pcr);
0346     sd_cmd_set_sd_cmd(pcr, cmd);
0347     sd_cmd_set_data_len(pcr, 1, byte_cnt);
0348     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
0349             SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
0350             SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
0351     if (trans_mode != SD_TM_AUTO_TUNING)
0352         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
0353                 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
0354 
0355     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
0356             0xFF, trans_mode | SD_TRANSFER_START);
0357     rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
0358             SD_TRANSFER_END, SD_TRANSFER_END);
0359 
0360     err = rtsx_pci_send_cmd(pcr, timeout);
0361     if (err < 0) {
0362         sd_print_debug_regs(host);
0363         dev_dbg(sdmmc_dev(host),
0364             "rtsx_pci_send_cmd fail (err = %d)\n", err);
0365         return err;
0366     }
0367 
0368     if (buf && buf_len) {
0369         err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
0370         if (err < 0) {
0371             dev_dbg(sdmmc_dev(host),
0372                 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
0373             return err;
0374         }
0375     }
0376 
0377     return 0;
0378 }
0379 
0380 static int sd_write_data(struct realtek_pci_sdmmc *host,
0381     struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
0382     int timeout)
0383 {
0384     struct rtsx_pcr *pcr = host->pcr;
0385     int err;
0386 
0387     dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
0388         __func__, cmd->opcode, cmd->arg);
0389 
0390     if (!buf)
0391         buf_len = 0;
0392 
0393     sd_send_cmd_get_rsp(host, cmd);
0394     if (cmd->error)
0395         return cmd->error;
0396 
0397     if (buf && buf_len) {
0398         err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
0399         if (err < 0) {
0400             dev_dbg(sdmmc_dev(host),
0401                 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
0402             return err;
0403         }
0404     }
0405 
0406     rtsx_pci_init_cmd(pcr);
0407     sd_cmd_set_data_len(pcr, 1, byte_cnt);
0408     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
0409         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
0410         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
0411     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
0412             SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
0413     rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
0414             SD_TRANSFER_END, SD_TRANSFER_END);
0415 
0416     err = rtsx_pci_send_cmd(pcr, timeout);
0417     if (err < 0) {
0418         sd_print_debug_regs(host);
0419         dev_dbg(sdmmc_dev(host),
0420             "rtsx_pci_send_cmd fail (err = %d)\n", err);
0421         return err;
0422     }
0423 
0424     return 0;
0425 }
0426 
0427 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
0428     struct mmc_request *mrq)
0429 {
0430     struct rtsx_pcr *pcr = host->pcr;
0431     struct mmc_host *mmc = host->mmc;
0432     struct mmc_card *card = mmc->card;
0433     struct mmc_command *cmd = mrq->cmd;
0434     struct mmc_data *data = mrq->data;
0435     int uhs = mmc_card_uhs(card);
0436     u8 cfg2 = 0;
0437     int err;
0438     int resp_type;
0439     size_t data_len = data->blksz * data->blocks;
0440 
0441     dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
0442         __func__, cmd->opcode, cmd->arg);
0443 
0444     resp_type = sd_response_type(cmd);
0445     if (resp_type < 0)
0446         return resp_type;
0447 
0448     if (!uhs)
0449         cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
0450 
0451     rtsx_pci_init_cmd(pcr);
0452     sd_cmd_set_sd_cmd(pcr, cmd);
0453     sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
0454     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
0455             DMA_DONE_INT, DMA_DONE_INT);
0456     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
0457         0xFF, (u8)(data_len >> 24));
0458     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
0459         0xFF, (u8)(data_len >> 16));
0460     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
0461         0xFF, (u8)(data_len >> 8));
0462     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
0463     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
0464         0x03 | DMA_PACK_SIZE_MASK,
0465         DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
0466     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
0467             0x01, RING_BUFFER);
0468     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
0469     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
0470             SD_TRANSFER_START | SD_TM_AUTO_READ_2);
0471     rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
0472             SD_TRANSFER_END, SD_TRANSFER_END);
0473     rtsx_pci_send_cmd_no_wait(pcr);
0474 
0475     err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
0476     if (err < 0) {
0477         sd_print_debug_regs(host);
0478         sd_clear_error(host);
0479         return err;
0480     }
0481 
0482     return 0;
0483 }
0484 
0485 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
0486     struct mmc_request *mrq)
0487 {
0488     struct rtsx_pcr *pcr = host->pcr;
0489     struct mmc_host *mmc = host->mmc;
0490     struct mmc_card *card = mmc->card;
0491     struct mmc_command *cmd = mrq->cmd;
0492     struct mmc_data *data = mrq->data;
0493     int uhs = mmc_card_uhs(card);
0494     u8 cfg2;
0495     int err;
0496     size_t data_len = data->blksz * data->blocks;
0497 
0498     sd_send_cmd_get_rsp(host, cmd);
0499     if (cmd->error)
0500         return cmd->error;
0501 
0502     dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
0503         __func__, cmd->opcode, cmd->arg);
0504 
0505     cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
0506         SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
0507 
0508     if (!uhs)
0509         cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
0510 
0511     rtsx_pci_init_cmd(pcr);
0512     sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
0513     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
0514             DMA_DONE_INT, DMA_DONE_INT);
0515     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
0516         0xFF, (u8)(data_len >> 24));
0517     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
0518         0xFF, (u8)(data_len >> 16));
0519     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
0520         0xFF, (u8)(data_len >> 8));
0521     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
0522     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
0523         0x03 | DMA_PACK_SIZE_MASK,
0524         DMA_DIR_TO_CARD | DMA_EN | DMA_512);
0525     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
0526             0x01, RING_BUFFER);
0527     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
0528     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
0529             SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
0530     rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
0531             SD_TRANSFER_END, SD_TRANSFER_END);
0532     rtsx_pci_send_cmd_no_wait(pcr);
0533     err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
0534     if (err < 0) {
0535         sd_clear_error(host);
0536         return err;
0537     }
0538 
0539     return 0;
0540 }
0541 
0542 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
0543 {
0544     rtsx_pci_write_register(host->pcr, SD_CFG1,
0545             SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
0546 }
0547 
0548 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
0549 {
0550     rtsx_pci_write_register(host->pcr, SD_CFG1,
0551             SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
0552 }
0553 
0554 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
0555 {
0556     struct mmc_data *data = mrq->data;
0557     int err;
0558 
0559     if (host->sg_count < 0) {
0560         data->error = host->sg_count;
0561         dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
0562             __func__, host->sg_count);
0563         return data->error;
0564     }
0565 
0566     if (data->flags & MMC_DATA_READ) {
0567         if (host->initial_mode)
0568             sd_disable_initial_mode(host);
0569 
0570         err = sd_read_long_data(host, mrq);
0571 
0572         if (host->initial_mode)
0573             sd_enable_initial_mode(host);
0574 
0575         return err;
0576     }
0577 
0578     return sd_write_long_data(host, mrq);
0579 }
0580 
0581 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
0582         struct mmc_request *mrq)
0583 {
0584     struct mmc_command *cmd = mrq->cmd;
0585     struct mmc_data *data = mrq->data;
0586     u8 *buf;
0587 
0588     buf = kzalloc(data->blksz, GFP_NOIO);
0589     if (!buf) {
0590         cmd->error = -ENOMEM;
0591         return;
0592     }
0593 
0594     if (data->flags & MMC_DATA_READ) {
0595         if (host->initial_mode)
0596             sd_disable_initial_mode(host);
0597 
0598         cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
0599                 data->blksz, 200);
0600 
0601         if (host->initial_mode)
0602             sd_enable_initial_mode(host);
0603 
0604         sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
0605     } else {
0606         sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
0607 
0608         cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
0609                 data->blksz, 200);
0610     }
0611 
0612     kfree(buf);
0613 }
0614 
0615 static int sd_change_phase(struct realtek_pci_sdmmc *host,
0616         u8 sample_point, bool rx)
0617 {
0618     struct rtsx_pcr *pcr = host->pcr;
0619     u16 SD_VP_CTL = 0;
0620     dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
0621             __func__, rx ? "RX" : "TX", sample_point);
0622 
0623     rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
0624     if (rx) {
0625         SD_VP_CTL = SD_VPRX_CTL;
0626         rtsx_pci_write_register(pcr, SD_VPRX_CTL,
0627             PHASE_SELECT_MASK, sample_point);
0628     } else {
0629         SD_VP_CTL = SD_VPTX_CTL;
0630         rtsx_pci_write_register(pcr, SD_VPTX_CTL,
0631             PHASE_SELECT_MASK, sample_point);
0632     }
0633     rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0);
0634     rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET,
0635                 PHASE_NOT_RESET);
0636     rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
0637     rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
0638 
0639     return 0;
0640 }
0641 
0642 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
0643 {
0644     bit %= RTSX_PHASE_MAX;
0645     return phase_map & (1 << bit);
0646 }
0647 
0648 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
0649 {
0650     int i;
0651 
0652     for (i = 0; i < RTSX_PHASE_MAX; i++) {
0653         if (test_phase_bit(phase_map, start_bit + i) == 0)
0654             return i;
0655     }
0656     return RTSX_PHASE_MAX;
0657 }
0658 
0659 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
0660 {
0661     int start = 0, len = 0;
0662     int start_final = 0, len_final = 0;
0663     u8 final_phase = 0xFF;
0664 
0665     if (phase_map == 0) {
0666         dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
0667         return final_phase;
0668     }
0669 
0670     while (start < RTSX_PHASE_MAX) {
0671         len = sd_get_phase_len(phase_map, start);
0672         if (len_final < len) {
0673             start_final = start;
0674             len_final = len;
0675         }
0676         start += len ? len : 1;
0677     }
0678 
0679     final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
0680     dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
0681         phase_map, len_final, final_phase);
0682 
0683     return final_phase;
0684 }
0685 
0686 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
0687 {
0688     int i;
0689     u8 val = 0;
0690 
0691     for (i = 0; i < 100; i++) {
0692         rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
0693         if (val & SD_DATA_IDLE)
0694             return;
0695 
0696         udelay(100);
0697     }
0698 }
0699 
0700 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
0701         u8 opcode, u8 sample_point)
0702 {
0703     int err;
0704     struct mmc_command cmd = {};
0705     struct rtsx_pcr *pcr = host->pcr;
0706 
0707     sd_change_phase(host, sample_point, true);
0708 
0709     rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
0710         SD_RSP_80CLK_TIMEOUT_EN);
0711 
0712     cmd.opcode = opcode;
0713     err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
0714     if (err < 0) {
0715         /* Wait till SD DATA IDLE */
0716         sd_wait_data_idle(host);
0717         sd_clear_error(host);
0718         rtsx_pci_write_register(pcr, SD_CFG3,
0719             SD_RSP_80CLK_TIMEOUT_EN, 0);
0720         return err;
0721     }
0722 
0723     rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
0724     return 0;
0725 }
0726 
0727 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
0728         u8 opcode, u32 *phase_map)
0729 {
0730     int err, i;
0731     u32 raw_phase_map = 0;
0732 
0733     for (i = 0; i < RTSX_PHASE_MAX; i++) {
0734         err = sd_tuning_rx_cmd(host, opcode, (u8)i);
0735         if (err == 0)
0736             raw_phase_map |= 1 << i;
0737     }
0738 
0739     if (phase_map)
0740         *phase_map = raw_phase_map;
0741 
0742     return 0;
0743 }
0744 
0745 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
0746 {
0747     int err, i;
0748     u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
0749     u8 final_phase;
0750 
0751     for (i = 0; i < RX_TUNING_CNT; i++) {
0752         err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
0753         if (err < 0)
0754             return err;
0755 
0756         if (raw_phase_map[i] == 0)
0757             break;
0758     }
0759 
0760     phase_map = 0xFFFFFFFF;
0761     for (i = 0; i < RX_TUNING_CNT; i++) {
0762         dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
0763                 i, raw_phase_map[i]);
0764         phase_map &= raw_phase_map[i];
0765     }
0766     dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
0767 
0768     if (phase_map) {
0769         final_phase = sd_search_final_phase(host, phase_map);
0770         if (final_phase == 0xFF)
0771             return -EINVAL;
0772 
0773         err = sd_change_phase(host, final_phase, true);
0774         if (err < 0)
0775             return err;
0776     } else {
0777         return -EINVAL;
0778     }
0779 
0780     return 0;
0781 }
0782 
0783 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
0784     struct mmc_data *data)
0785 {
0786     return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
0787 }
0788 
0789 static inline int sd_rw_cmd(struct mmc_command *cmd)
0790 {
0791     return mmc_op_multi(cmd->opcode) ||
0792         (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
0793         (cmd->opcode == MMC_WRITE_BLOCK);
0794 }
0795 
0796 static void sd_request(struct work_struct *work)
0797 {
0798     struct realtek_pci_sdmmc *host = container_of(work,
0799             struct realtek_pci_sdmmc, work);
0800     struct rtsx_pcr *pcr = host->pcr;
0801 
0802     struct mmc_host *mmc = host->mmc;
0803     struct mmc_request *mrq = host->mrq;
0804     struct mmc_command *cmd = mrq->cmd;
0805     struct mmc_data *data = mrq->data;
0806 
0807     unsigned int data_size = 0;
0808     int err;
0809 
0810     if (host->eject || !sd_get_cd_int(host)) {
0811         cmd->error = -ENOMEDIUM;
0812         goto finish;
0813     }
0814 
0815     err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
0816     if (err) {
0817         cmd->error = err;
0818         goto finish;
0819     }
0820 
0821     mutex_lock(&pcr->pcr_mutex);
0822 
0823     rtsx_pci_start_run(pcr);
0824 
0825     rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
0826             host->initial_mode, host->double_clk, host->vpclk);
0827     rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
0828     rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
0829             CARD_SHARE_MASK, CARD_SHARE_48_SD);
0830 
0831     mutex_lock(&host->host_mutex);
0832     host->mrq = mrq;
0833     mutex_unlock(&host->host_mutex);
0834 
0835     if (mrq->data)
0836         data_size = data->blocks * data->blksz;
0837 
0838     if (!data_size) {
0839         sd_send_cmd_get_rsp(host, cmd);
0840     } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
0841         cmd->error = sd_rw_multi(host, mrq);
0842         if (!host->using_cookie)
0843             sdmmc_post_req(host->mmc, host->mrq, 0);
0844 
0845         if (mmc_op_multi(cmd->opcode) && mrq->stop)
0846             sd_send_cmd_get_rsp(host, mrq->stop);
0847     } else {
0848         sd_normal_rw(host, mrq);
0849     }
0850 
0851     if (mrq->data) {
0852         if (cmd->error || data->error)
0853             data->bytes_xfered = 0;
0854         else
0855             data->bytes_xfered = data->blocks * data->blksz;
0856     }
0857 
0858     mutex_unlock(&pcr->pcr_mutex);
0859 
0860 finish:
0861     if (cmd->error) {
0862         dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
0863             cmd->opcode, cmd->arg, cmd->error);
0864     }
0865 
0866     mutex_lock(&host->host_mutex);
0867     host->mrq = NULL;
0868     mutex_unlock(&host->host_mutex);
0869 
0870     mmc_request_done(mmc, mrq);
0871 }
0872 
0873 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
0874 {
0875     struct realtek_pci_sdmmc *host = mmc_priv(mmc);
0876     struct mmc_data *data = mrq->data;
0877 
0878     mutex_lock(&host->host_mutex);
0879     host->mrq = mrq;
0880     mutex_unlock(&host->host_mutex);
0881 
0882     if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
0883         host->using_cookie = sd_pre_dma_transfer(host, data, false);
0884 
0885     schedule_work(&host->work);
0886 }
0887 
0888 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
0889         unsigned char bus_width)
0890 {
0891     int err = 0;
0892     u8 width[] = {
0893         [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
0894         [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
0895         [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
0896     };
0897 
0898     if (bus_width <= MMC_BUS_WIDTH_8)
0899         err = rtsx_pci_write_register(host->pcr, SD_CFG1,
0900                 0x03, width[bus_width]);
0901 
0902     return err;
0903 }
0904 
0905 static int sd_power_on(struct realtek_pci_sdmmc *host, unsigned char power_mode)
0906 {
0907     struct rtsx_pcr *pcr = host->pcr;
0908     struct mmc_host *mmc = host->mmc;
0909     int err;
0910     u32 val;
0911     u8 test_mode;
0912 
0913     if (host->prev_power_state == MMC_POWER_ON)
0914         return 0;
0915 
0916     if (host->prev_power_state == MMC_POWER_UP) {
0917         rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0);
0918         goto finish;
0919     }
0920 
0921     msleep(100);
0922 
0923     rtsx_pci_init_cmd(pcr);
0924     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
0925     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
0926             CARD_SHARE_MASK, CARD_SHARE_48_SD);
0927     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
0928             SD_CLK_EN, SD_CLK_EN);
0929     err = rtsx_pci_send_cmd(pcr, 100);
0930     if (err < 0)
0931         return err;
0932 
0933     err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
0934     if (err < 0)
0935         return err;
0936 
0937     err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
0938     if (err < 0)
0939         return err;
0940 
0941     mdelay(1);
0942 
0943     err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
0944     if (err < 0)
0945         return err;
0946 
0947     /* send at least 74 clocks */
0948     rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
0949 
0950     if (PCI_PID(pcr) == PID_5261) {
0951         /*
0952          * If test mode is set switch to SD Express mandatorily,
0953          * this is only for factory testing.
0954          */
0955         rtsx_pci_read_register(pcr, RTS5261_FW_CFG_INFO0, &test_mode);
0956         if (test_mode & RTS5261_FW_EXPRESS_TEST_MASK) {
0957             sdmmc_init_sd_express(mmc, NULL);
0958             return 0;
0959         }
0960         if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS)
0961             mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V;
0962         /*
0963          * HW read wp status when resuming from S3/S4,
0964          * and then picks SD legacy interface if it's set
0965          * in read-only mode.
0966          */
0967         val = rtsx_pci_readl(pcr, RTSX_BIPR);
0968         if (val & SD_WRITE_PROTECT) {
0969             pcr->extra_caps &= ~EXTRA_CAPS_SD_EXPRESS;
0970             mmc->caps2 &= ~(MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V);
0971         }
0972     }
0973 
0974 finish:
0975     host->prev_power_state = power_mode;
0976     return 0;
0977 }
0978 
0979 static int sd_power_off(struct realtek_pci_sdmmc *host)
0980 {
0981     struct rtsx_pcr *pcr = host->pcr;
0982     int err;
0983 
0984     host->prev_power_state = MMC_POWER_OFF;
0985 
0986     rtsx_pci_init_cmd(pcr);
0987 
0988     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
0989     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
0990 
0991     err = rtsx_pci_send_cmd(pcr, 100);
0992     if (err < 0)
0993         return err;
0994 
0995     err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
0996     if (err < 0)
0997         return err;
0998 
0999     return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
1000 }
1001 
1002 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
1003         unsigned char power_mode)
1004 {
1005     int err;
1006 
1007     if (power_mode == MMC_POWER_OFF)
1008         err = sd_power_off(host);
1009     else
1010         err = sd_power_on(host, power_mode);
1011 
1012     return err;
1013 }
1014 
1015 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
1016 {
1017     struct rtsx_pcr *pcr = host->pcr;
1018     int err = 0;
1019 
1020     rtsx_pci_init_cmd(pcr);
1021 
1022     switch (timing) {
1023     case MMC_TIMING_UHS_SDR104:
1024     case MMC_TIMING_UHS_SDR50:
1025         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1026                 0x0C | SD_ASYNC_FIFO_NOT_RST,
1027                 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
1028         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1029                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1030         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1031                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1032         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1033         break;
1034 
1035     case MMC_TIMING_MMC_DDR52:
1036     case MMC_TIMING_UHS_DDR50:
1037         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1038                 0x0C | SD_ASYNC_FIFO_NOT_RST,
1039                 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
1040         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1041                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1042         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1043                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1044         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1045         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1046                 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1047         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1048                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1049                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1050         break;
1051 
1052     case MMC_TIMING_MMC_HS:
1053     case MMC_TIMING_SD_HS:
1054         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1055                 0x0C, SD_20_MODE);
1056         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1057                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1058         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1059                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1060         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1061         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1062                 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1063         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1064                 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1065         break;
1066 
1067     default:
1068         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1069                 SD_CFG1, 0x0C, SD_20_MODE);
1070         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1071                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1072         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1073                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1074         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1075         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1076                 SD_PUSH_POINT_CTL, 0xFF, 0);
1077         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1078                 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1079         break;
1080     }
1081 
1082     err = rtsx_pci_send_cmd(pcr, 100);
1083 
1084     return err;
1085 }
1086 
1087 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1088 {
1089     struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1090     struct rtsx_pcr *pcr = host->pcr;
1091 
1092     if (host->eject)
1093         return;
1094 
1095     if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1096         return;
1097 
1098     mutex_lock(&pcr->pcr_mutex);
1099 
1100     rtsx_pci_start_run(pcr);
1101 
1102     sd_set_bus_width(host, ios->bus_width);
1103     sd_set_power_mode(host, ios->power_mode);
1104     sd_set_timing(host, ios->timing);
1105 
1106     host->vpclk = false;
1107     host->double_clk = true;
1108 
1109     switch (ios->timing) {
1110     case MMC_TIMING_UHS_SDR104:
1111     case MMC_TIMING_UHS_SDR50:
1112         host->ssc_depth = RTSX_SSC_DEPTH_2M;
1113         host->vpclk = true;
1114         host->double_clk = false;
1115         break;
1116     case MMC_TIMING_MMC_DDR52:
1117     case MMC_TIMING_UHS_DDR50:
1118     case MMC_TIMING_UHS_SDR25:
1119         host->ssc_depth = RTSX_SSC_DEPTH_1M;
1120         break;
1121     default:
1122         host->ssc_depth = RTSX_SSC_DEPTH_500K;
1123         break;
1124     }
1125 
1126     host->initial_mode = (ios->clock <= 1000000) ? true : false;
1127 
1128     host->clock = ios->clock;
1129     rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1130             host->initial_mode, host->double_clk, host->vpclk);
1131 
1132     mutex_unlock(&pcr->pcr_mutex);
1133 }
1134 
1135 static int sdmmc_get_ro(struct mmc_host *mmc)
1136 {
1137     struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1138     struct rtsx_pcr *pcr = host->pcr;
1139     int ro = 0;
1140     u32 val;
1141 
1142     if (host->eject)
1143         return -ENOMEDIUM;
1144 
1145     mutex_lock(&pcr->pcr_mutex);
1146 
1147     rtsx_pci_start_run(pcr);
1148 
1149     /* Check SD mechanical write-protect switch */
1150     val = rtsx_pci_readl(pcr, RTSX_BIPR);
1151     dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1152     if (val & SD_WRITE_PROTECT)
1153         ro = 1;
1154 
1155     mutex_unlock(&pcr->pcr_mutex);
1156 
1157     return ro;
1158 }
1159 
1160 static int sdmmc_get_cd(struct mmc_host *mmc)
1161 {
1162     struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1163     struct rtsx_pcr *pcr = host->pcr;
1164     int cd = 0;
1165     u32 val;
1166 
1167     if (host->eject)
1168         return cd;
1169 
1170     mutex_lock(&pcr->pcr_mutex);
1171 
1172     rtsx_pci_start_run(pcr);
1173 
1174     /* Check SD card detect */
1175     val = rtsx_pci_card_exist(pcr);
1176     dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1177     if (val & SD_EXIST)
1178         cd = 1;
1179 
1180     mutex_unlock(&pcr->pcr_mutex);
1181 
1182     return cd;
1183 }
1184 
1185 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1186 {
1187     struct rtsx_pcr *pcr = host->pcr;
1188     int err;
1189     u8 stat;
1190 
1191     /* Reference to Signal Voltage Switch Sequence in SD spec.
1192      * Wait for a period of time so that the card can drive SD_CMD and
1193      * SD_DAT[3:0] to low after sending back CMD11 response.
1194      */
1195     mdelay(1);
1196 
1197     /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1198      * If either one of SD_CMD,SD_DAT[3:0] is not low,
1199      * abort the voltage switch sequence;
1200      */
1201     err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1202     if (err < 0)
1203         return err;
1204 
1205     if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1206                 SD_DAT1_STATUS | SD_DAT0_STATUS))
1207         return -EINVAL;
1208 
1209     /* Stop toggle SD clock */
1210     err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1211             0xFF, SD_CLK_FORCE_STOP);
1212     if (err < 0)
1213         return err;
1214 
1215     return 0;
1216 }
1217 
1218 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1219 {
1220     struct rtsx_pcr *pcr = host->pcr;
1221     int err;
1222     u8 stat, mask, val;
1223 
1224     /* Wait 1.8V output of voltage regulator in card stable */
1225     msleep(50);
1226 
1227     /* Toggle SD clock again */
1228     err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1229     if (err < 0)
1230         return err;
1231 
1232     /* Wait for a period of time so that the card can drive
1233      * SD_DAT[3:0] to high at 1.8V
1234      */
1235     msleep(20);
1236 
1237     /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1238     err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1239     if (err < 0)
1240         return err;
1241 
1242     mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1243         SD_DAT1_STATUS | SD_DAT0_STATUS;
1244     val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1245         SD_DAT1_STATUS | SD_DAT0_STATUS;
1246     if ((stat & mask) != val) {
1247         dev_dbg(sdmmc_dev(host),
1248             "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1249         rtsx_pci_write_register(pcr, SD_BUS_STAT,
1250                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1251         rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1252         return -EINVAL;
1253     }
1254 
1255     return 0;
1256 }
1257 
1258 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1259 {
1260     struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1261     struct rtsx_pcr *pcr = host->pcr;
1262     int err = 0;
1263     u8 voltage;
1264 
1265     dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1266             __func__, ios->signal_voltage);
1267 
1268     if (host->eject)
1269         return -ENOMEDIUM;
1270 
1271     err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1272     if (err)
1273         return err;
1274 
1275     mutex_lock(&pcr->pcr_mutex);
1276 
1277     rtsx_pci_start_run(pcr);
1278 
1279     if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1280         voltage = OUTPUT_3V3;
1281     else
1282         voltage = OUTPUT_1V8;
1283 
1284     if (voltage == OUTPUT_1V8) {
1285         err = sd_wait_voltage_stable_1(host);
1286         if (err < 0)
1287             goto out;
1288     }
1289 
1290     err = rtsx_pci_switch_output_voltage(pcr, voltage);
1291     if (err < 0)
1292         goto out;
1293 
1294     if (voltage == OUTPUT_1V8) {
1295         err = sd_wait_voltage_stable_2(host);
1296         if (err < 0)
1297             goto out;
1298     }
1299 
1300 out:
1301     /* Stop toggle SD clock in idle */
1302     err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1303             SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1304 
1305     mutex_unlock(&pcr->pcr_mutex);
1306 
1307     return err;
1308 }
1309 
1310 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1311 {
1312     struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1313     struct rtsx_pcr *pcr = host->pcr;
1314     int err = 0;
1315 
1316     if (host->eject)
1317         return -ENOMEDIUM;
1318 
1319     err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1320     if (err)
1321         return err;
1322 
1323     mutex_lock(&pcr->pcr_mutex);
1324 
1325     rtsx_pci_start_run(pcr);
1326 
1327     /* Set initial TX phase */
1328     switch (mmc->ios.timing) {
1329     case MMC_TIMING_UHS_SDR104:
1330         err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1331         break;
1332 
1333     case MMC_TIMING_UHS_SDR50:
1334         err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1335         break;
1336 
1337     case MMC_TIMING_UHS_DDR50:
1338         err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1339         break;
1340 
1341     default:
1342         err = 0;
1343     }
1344 
1345     if (err)
1346         goto out;
1347 
1348     /* Tuning RX phase */
1349     if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1350             (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1351         err = sd_tuning_rx(host, opcode);
1352     else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1353         err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1354 
1355 out:
1356     mutex_unlock(&pcr->pcr_mutex);
1357 
1358     return err;
1359 }
1360 
1361 static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios)
1362 {
1363     u32 relink_time;
1364     struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1365     struct rtsx_pcr *pcr = host->pcr;
1366 
1367     /* Set relink_time for changing to PCIe card */
1368     relink_time = 0x8FFF;
1369 
1370     rtsx_pci_write_register(pcr, 0xFF01, 0xFF, relink_time);
1371     rtsx_pci_write_register(pcr, 0xFF02, 0xFF, relink_time >> 8);
1372     rtsx_pci_write_register(pcr, 0xFF03, 0x01, relink_time >> 16);
1373 
1374     rtsx_pci_write_register(pcr, PETXCFG, 0x80, 0x80);
1375     rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
1376         RTS5261_LDO1_OCP_THD_MASK,
1377         pcr->option.sd_800mA_ocp_thd);
1378 
1379     if (pcr->ops->disable_auto_blink)
1380         pcr->ops->disable_auto_blink(pcr);
1381 
1382     /* For PCIe/NVMe mode can't enter delink issue */
1383     pcr->hw_param.interrupt_en &= ~(SD_INT_EN);
1384     rtsx_pci_writel(pcr, RTSX_BIER, pcr->hw_param.interrupt_en);
1385 
1386     rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4,
1387         RTS5261_AUX_CLK_16M_EN, RTS5261_AUX_CLK_16M_EN);
1388     rtsx_pci_write_register(pcr, RTS5261_FW_CFG0,
1389         RTS5261_FW_ENTER_EXPRESS, RTS5261_FW_ENTER_EXPRESS);
1390     rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1391         RTS5261_MCU_CLOCK_GATING, RTS5261_MCU_CLOCK_GATING);
1392     rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1393         RTS5261_MCU_BUS_SEL_MASK | RTS5261_MCU_CLOCK_SEL_MASK
1394         | RTS5261_DRIVER_ENABLE_FW,
1395         RTS5261_MCU_CLOCK_SEL_16M | RTS5261_DRIVER_ENABLE_FW);
1396     host->eject = true;
1397     return 0;
1398 }
1399 
1400 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1401     .pre_req = sdmmc_pre_req,
1402     .post_req = sdmmc_post_req,
1403     .request = sdmmc_request,
1404     .set_ios = sdmmc_set_ios,
1405     .get_ro = sdmmc_get_ro,
1406     .get_cd = sdmmc_get_cd,
1407     .start_signal_voltage_switch = sdmmc_switch_voltage,
1408     .execute_tuning = sdmmc_execute_tuning,
1409     .init_sd_express = sdmmc_init_sd_express,
1410 };
1411 
1412 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1413 {
1414     struct mmc_host *mmc = host->mmc;
1415     struct rtsx_pcr *pcr = host->pcr;
1416 
1417     dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1418 
1419     if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1420         mmc->caps |= MMC_CAP_UHS_SDR50;
1421     if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1422         mmc->caps |= MMC_CAP_UHS_SDR104;
1423     if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1424         mmc->caps |= MMC_CAP_UHS_DDR50;
1425     if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1426         mmc->caps |= MMC_CAP_1_8V_DDR;
1427     if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1428         mmc->caps |= MMC_CAP_8_BIT_DATA;
1429     if (pcr->extra_caps & EXTRA_CAPS_NO_MMC)
1430         mmc->caps2 |= MMC_CAP2_NO_MMC;
1431     if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS)
1432         mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V;
1433 }
1434 
1435 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1436 {
1437     struct mmc_host *mmc = host->mmc;
1438     struct rtsx_pcr *pcr = host->pcr;
1439 
1440     mmc->f_min = 250000;
1441     mmc->f_max = 208000000;
1442     mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1443     mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1444         MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1445         MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1446     if (pcr->rtd3_en)
1447         mmc->caps = mmc->caps | MMC_CAP_AGGRESSIVE_PM;
1448     mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE |
1449         MMC_CAP2_NO_SDIO;
1450     mmc->max_current_330 = 400;
1451     mmc->max_current_180 = 800;
1452     mmc->ops = &realtek_pci_sdmmc_ops;
1453 
1454     init_extra_caps(host);
1455 
1456     mmc->max_segs = 256;
1457     mmc->max_seg_size = 65536;
1458     mmc->max_blk_size = 512;
1459     mmc->max_blk_count = 65535;
1460     mmc->max_req_size = 524288;
1461 }
1462 
1463 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1464 {
1465     struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1466 
1467     host->cookie = -1;
1468     mmc_detect_change(host->mmc, 0);
1469 }
1470 
1471 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1472 {
1473     struct mmc_host *mmc;
1474     struct realtek_pci_sdmmc *host;
1475     struct rtsx_pcr *pcr;
1476     struct pcr_handle *handle = pdev->dev.platform_data;
1477 
1478     if (!handle)
1479         return -ENXIO;
1480 
1481     pcr = handle->pcr;
1482     if (!pcr)
1483         return -ENXIO;
1484 
1485     dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1486 
1487     mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1488     if (!mmc)
1489         return -ENOMEM;
1490 
1491     host = mmc_priv(mmc);
1492     host->pcr = pcr;
1493     mmc->ios.power_delay_ms = 5;
1494     host->mmc = mmc;
1495     host->pdev = pdev;
1496     host->cookie = -1;
1497     host->prev_power_state = MMC_POWER_OFF;
1498     INIT_WORK(&host->work, sd_request);
1499     platform_set_drvdata(pdev, host);
1500     pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1501     pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1502 
1503     mutex_init(&host->host_mutex);
1504 
1505     realtek_init_host(host);
1506 
1507     pm_runtime_no_callbacks(&pdev->dev);
1508     pm_runtime_set_active(&pdev->dev);
1509     pm_runtime_enable(&pdev->dev);
1510     pm_runtime_set_autosuspend_delay(&pdev->dev, 200);
1511     pm_runtime_mark_last_busy(&pdev->dev);
1512     pm_runtime_use_autosuspend(&pdev->dev);
1513 
1514     mmc_add_host(mmc);
1515 
1516     return 0;
1517 }
1518 
1519 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1520 {
1521     struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1522     struct rtsx_pcr *pcr;
1523     struct mmc_host *mmc;
1524 
1525     if (!host)
1526         return 0;
1527 
1528     pcr = host->pcr;
1529     pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1530     pcr->slots[RTSX_SD_CARD].card_event = NULL;
1531     mmc = host->mmc;
1532 
1533     cancel_work_sync(&host->work);
1534 
1535     mutex_lock(&host->host_mutex);
1536     if (host->mrq) {
1537         dev_dbg(&(pdev->dev),
1538             "%s: Controller removed during transfer\n",
1539             mmc_hostname(mmc));
1540 
1541         rtsx_pci_complete_unfinished_transfer(pcr);
1542 
1543         host->mrq->cmd->error = -ENOMEDIUM;
1544         if (host->mrq->stop)
1545             host->mrq->stop->error = -ENOMEDIUM;
1546         mmc_request_done(mmc, host->mrq);
1547     }
1548     mutex_unlock(&host->host_mutex);
1549 
1550     mmc_remove_host(mmc);
1551     host->eject = true;
1552 
1553     flush_work(&host->work);
1554 
1555     pm_runtime_dont_use_autosuspend(&pdev->dev);
1556     pm_runtime_disable(&pdev->dev);
1557 
1558     mmc_free_host(mmc);
1559 
1560     dev_dbg(&(pdev->dev),
1561         ": Realtek PCI-E SDMMC controller has been removed\n");
1562 
1563     return 0;
1564 }
1565 
1566 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1567     {
1568         .name = DRV_NAME_RTSX_PCI_SDMMC,
1569     }, {
1570         /* sentinel */
1571     }
1572 };
1573 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1574 
1575 static struct platform_driver rtsx_pci_sdmmc_driver = {
1576     .probe      = rtsx_pci_sdmmc_drv_probe,
1577     .remove     = rtsx_pci_sdmmc_drv_remove,
1578     .id_table       = rtsx_pci_sdmmc_ids,
1579     .driver     = {
1580         .name   = DRV_NAME_RTSX_PCI_SDMMC,
1581         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1582     },
1583 };
1584 module_platform_driver(rtsx_pci_sdmmc_driver);
1585 
1586 MODULE_LICENSE("GPL");
1587 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1588 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!