mmc/host/renesas_sdhi_internal_dmac.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * DMA support for Internal DMAC with SDHI SD/SDIO controller
0004  *
0005  * Copyright (C) 2016-19 Renesas Electronics Corporation
0006  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
0007  * Copyright (C) 2018-19 Sang Engineering, Wolfram Sang
0008  */
0009
0010 #include <linux/bitops.h>
0011 #include <linux/device.h>
0012 #include <linux/dma-mapping.h>
0013 #include <linux/io-64-nonatomic-hi-lo.h>
0014 #include <linux/mfd/tmio.h>
0015 #include <linux/mmc/host.h>
0016 #include <linux/mod_devicetable.h>
0017 #include <linux/module.h>
0018 #include <linux/of_device.h>
0019 #include <linux/pagemap.h>
0020 #include <linux/scatterlist.h>
0021 #include <linux/sys_soc.h>
0022
0023 #include "renesas_sdhi.h"
0024 #include "tmio_mmc.h"
0025
0026 #define DM_CM_DTRAN_MODE    0x820
0027 #define DM_CM_DTRAN_CTRL    0x828
0028 #define DM_CM_RST       0x830
0029 #define DM_CM_INFO1     0x840
0030 #define DM_CM_INFO1_MASK    0x848
0031 #define DM_CM_INFO2     0x850
0032 #define DM_CM_INFO2_MASK    0x858
0033 #define DM_DTRAN_ADDR       0x880
0034
0035 /* DM_CM_DTRAN_MODE */
0036 #define DTRAN_MODE_CH_NUM_CH0   0   /* "downstream" = for write commands */
0037 #define DTRAN_MODE_CH_NUM_CH1   BIT(16) /* "upstream" = for read commands */
0038 #define DTRAN_MODE_BUS_WIDTH    (BIT(5) | BIT(4))
0039 #define DTRAN_MODE_ADDR_MODE    BIT(0)  /* 1 = Increment address, 0 = Fixed */
0040
0041 /* DM_CM_DTRAN_CTRL */
0042 #define DTRAN_CTRL_DM_START BIT(0)
0043
0044 /* DM_CM_RST */
0045 #define RST_DTRANRST1       BIT(9)
0046 #define RST_DTRANRST0       BIT(8)
0047 #define RST_RESERVED_BITS   GENMASK_ULL(31, 0)
0048
0049 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */
0050 #define INFO1_CLEAR     0
0051 #define INFO1_MASK_CLEAR    GENMASK_ULL(31, 0)
0052 #define INFO1_DTRANEND1     BIT(17)
0053 #define INFO1_DTRANEND0     BIT(16)
0054
0055 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */
0056 #define INFO2_MASK_CLEAR    GENMASK_ULL(31, 0)
0057 #define INFO2_DTRANERR1     BIT(17)
0058 #define INFO2_DTRANERR0     BIT(16)
0059
0060 enum renesas_sdhi_dma_cookie {
0061     COOKIE_UNMAPPED,
0062     COOKIE_PRE_MAPPED,
0063     COOKIE_MAPPED,
0064 };
0065
0066 /*
0067  * Specification of this driver:
0068  * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
0069  * - Since this SDHI DMAC register set has 16 but 32-bit width, we
0070  *   need a custom accessor.
0071  */
0072
0073 static unsigned long global_flags;
0074 /*
0075  * Workaround for avoiding to use RX DMAC by multiple channels.
0076  * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use
0077  * RX DMAC simultaneously, sometimes hundreds of bytes data are not
0078  * stored into the system memory even if the DMAC interrupt happened.
0079  * So, this driver then uses one RX DMAC channel only.
0080  */
0081 #define SDHI_INTERNAL_DMAC_RX_IN_USE    0
0082
0083 /* Definitions for sampling clocks */
0084 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
0085     {
0086         .clk_rate = 0,
0087         .tap = 0x00000300,
0088         .tap_hs400_4tap = 0x00000100,
0089     },
0090 };
0091
0092 static const struct renesas_sdhi_of_data of_data_rza2 = {
0093     .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
0094               TMIO_MMC_HAVE_CBSY,
0095     .tmio_ocr_mask  = MMC_VDD_32_33,
0096     .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
0097               MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
0098     .bus_shift  = 2,
0099     .scc_offset = 0 - 0x1000,
0100     .taps       = rcar_gen3_scc_taps,
0101     .taps_num   = ARRAY_SIZE(rcar_gen3_scc_taps),
0102     /* DMAC can handle 32bit blk count but only 1 segment */
0103     .max_blk_count  = UINT_MAX / TMIO_MAX_BLK_SIZE,
0104     .max_segs   = 1,
0105 };
0106
0107 static const struct renesas_sdhi_of_data of_data_rcar_gen3 = {
0108     .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
0109               TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
0110     .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
0111               MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
0112     .capabilities2  = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
0113     .bus_shift  = 2,
0114     .scc_offset = 0x1000,
0115     .taps       = rcar_gen3_scc_taps,
0116     .taps_num   = ARRAY_SIZE(rcar_gen3_scc_taps),
0117     /* DMAC can handle 32bit blk count but only 1 segment */
0118     .max_blk_count  = UINT_MAX / TMIO_MAX_BLK_SIZE,
0119     .max_segs   = 1,
0120     .sdhi_flags = SDHI_FLAG_NEED_CLKH_FALLBACK,
0121 };
0122
0123 static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback = {
0124     .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
0125               TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
0126     .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
0127               MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
0128     .capabilities2  = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
0129     .bus_shift  = 2,
0130     .scc_offset = 0x1000,
0131     .taps       = rcar_gen3_scc_taps,
0132     .taps_num   = ARRAY_SIZE(rcar_gen3_scc_taps),
0133     /* DMAC can handle 32bit blk count but only 1 segment */
0134     .max_blk_count  = UINT_MAX / TMIO_MAX_BLK_SIZE,
0135     .max_segs   = 1,
0136 };
0137
0138 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
0139     { 3,  3,  3,  3,  3,  3,  3,  4,  4,  5,  6,  7,  8,  9, 10, 15,
0140      16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
0141     { 5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  6,  7,  8, 11,
0142      12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
0143 };
0144
0145 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
0146     { 1,  2,  6,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
0147      17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
0148     { 2,  3,  4,  4,  5,  6,  7,  9, 10, 11, 12, 13, 14, 15, 16, 17,
0149      17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
0150 };
0151
0152 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
0153     { 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
0154       0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },
0155     { 0,  0,  0,  1,  2,  3,  3,  4,  4,  4,  5,  5,  6,  8,  9, 10,
0156      11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
0157 };
0158
0159 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
0160     .hs400_disabled = true,
0161     .hs400_4taps = true,
0162 };
0163
0164 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_one_rx = {
0165     .hs400_disabled = true,
0166     .hs400_4taps = true,
0167     .dma_one_rx_only = true,
0168 };
0169
0170 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
0171     .hs400_4taps = true,
0172     .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
0173     .manual_tap_correction = true,
0174 };
0175
0176 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
0177     .hs400_disabled = true,
0178 };
0179
0180 static const struct renesas_sdhi_quirks sdhi_quirks_fixed_addr = {
0181     .fixed_addr_mode = true,
0182 };
0183
0184 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = {
0185     .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
0186     .manual_tap_correction = true,
0187 };
0188
0189 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = {
0190     .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
0191     .manual_tap_correction = true,
0192 };
0193
0194 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
0195     .hs400_4taps = true,
0196     .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
0197     .hs400_calib_table = r8a7796_es13_calib_table,
0198     .manual_tap_correction = true,
0199 };
0200
0201 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
0202     .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
0203     .hs400_calib_table = r8a77965_calib_table,
0204     .manual_tap_correction = true,
0205 };
0206
0207 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = {
0208     .hs400_calib_table = r8a77990_calib_table,
0209     .manual_tap_correction = true,
0210 };
0211
0212 /*
0213  * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
0214  * So, we want to treat them equally and only have a match for ES1.2 to enforce
0215  * this if there ever will be a way to distinguish ES1.2.
0216  */
0217 static const struct soc_device_attribute sdhi_quirks_match[]  = {
0218     { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
0219     { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400_one_rx },
0220     { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
0221     { .soc_id = "r8a7796", .revision = "ES1.0", .data = &sdhi_quirks_4tap_nohs400_one_rx },
0222     { .soc_id = "r8a7796", .revision = "ES1.[12]", .data = &sdhi_quirks_4tap_nohs400 },
0223     { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 },
0224     { .soc_id = "r8a77980", .revision = "ES1.*", .data = &sdhi_quirks_nohs400 },
0225     { /* Sentinel. */ }
0226 };
0227
0228 static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible = {
0229     .of_data = &of_data_rcar_gen3,
0230     .quirks = &sdhi_quirks_bad_taps2367,
0231 };
0232
0233 static const struct renesas_sdhi_of_data_with_quirks of_r8a77961_compatible = {
0234     .of_data = &of_data_rcar_gen3,
0235     .quirks = &sdhi_quirks_bad_taps1357,
0236 };
0237
0238 static const struct renesas_sdhi_of_data_with_quirks of_r8a77965_compatible = {
0239     .of_data = &of_data_rcar_gen3,
0240     .quirks = &sdhi_quirks_r8a77965,
0241 };
0242
0243 static const struct renesas_sdhi_of_data_with_quirks of_r8a77970_compatible = {
0244     .of_data = &of_data_rcar_gen3_no_sdh_fallback,
0245     .quirks = &sdhi_quirks_nohs400,
0246 };
0247
0248 static const struct renesas_sdhi_of_data_with_quirks of_r8a77990_compatible = {
0249     .of_data = &of_data_rcar_gen3,
0250     .quirks = &sdhi_quirks_r8a77990,
0251 };
0252
0253 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatible = {
0254     .of_data = &of_data_rcar_gen3,
0255 };
0256
0257 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_nohs400_compatible = {
0258     .of_data = &of_data_rcar_gen3,
0259     .quirks = &sdhi_quirks_nohs400,
0260 };
0261
0262 static const struct renesas_sdhi_of_data_with_quirks of_rza2_compatible = {
0263     .of_data    = &of_data_rza2,
0264     .quirks     = &sdhi_quirks_fixed_addr,
0265 };
0266
0267 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
0268     { .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, },
0269     { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, },
0270     { .compatible = "renesas,sdhi-r8a7795", .data = &of_r8a7795_compatible, },
0271     { .compatible = "renesas,sdhi-r8a77961", .data = &of_r8a77961_compatible, },
0272     { .compatible = "renesas,sdhi-r8a77965", .data = &of_r8a77965_compatible, },
0273     { .compatible = "renesas,sdhi-r8a77970", .data = &of_r8a77970_compatible, },
0274     { .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, },
0275     { .compatible = "renesas,sdhi-r8a77995", .data = &of_rcar_gen3_nohs400_compatible, },
0276     { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
0277     { .compatible = "renesas,rcar-gen4-sdhi", .data = &of_rcar_gen3_compatible, },
0278     {},
0279 };
0280 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
0281
0282 static void
0283 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
0284                     int addr, u64 val)
0285 {
0286     writeq(val, host->ctl + addr);
0287 }
0288
0289 static void
0290 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
0291 {
0292     struct renesas_sdhi *priv = host_to_priv(host);
0293
0294     if (!host->chan_tx || !host->chan_rx)
0295         return;
0296
0297     if (!enable)
0298         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
0299                             INFO1_CLEAR);
0300
0301     if (priv->dma_priv.enable)
0302         priv->dma_priv.enable(host, enable);
0303 }
0304
0305 static void
0306 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host)
0307 {
0308     u64 val = RST_DTRANRST1 | RST_DTRANRST0;
0309
0310     renesas_sdhi_internal_dmac_enable_dma(host, false);
0311
0312     renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
0313                         RST_RESERVED_BITS & ~val);
0314     renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
0315                         RST_RESERVED_BITS | val);
0316
0317     clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
0318
0319     renesas_sdhi_internal_dmac_enable_dma(host, true);
0320 }
0321
0322 static void
0323 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host)
0324 {
0325     struct renesas_sdhi *priv = host_to_priv(host);
0326
0327     tasklet_schedule(&priv->dma_priv.dma_complete);
0328 }
0329
0330 /*
0331  * renesas_sdhi_internal_dmac_map() will be called with two different
0332  * sg pointers in two mmc_data by .pre_req(), but tmio host can have a single
0333  * sg_ptr only. So, renesas_sdhi_internal_dmac_{un}map() should use a sg
0334  * pointer in a mmc_data instead of host->sg_ptr.
0335  */
0336 static void
0337 renesas_sdhi_internal_dmac_unmap(struct tmio_mmc_host *host,
0338                  struct mmc_data *data,
0339                  enum renesas_sdhi_dma_cookie cookie)
0340 {
0341     bool unmap = cookie == COOKIE_UNMAPPED ? (data->host_cookie != cookie) :
0342                          (data->host_cookie == cookie);
0343
0344     if (unmap) {
0345         dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
0346                  mmc_get_dma_dir(data));
0347         data->host_cookie = COOKIE_UNMAPPED;
0348     }
0349 }
0350
0351 static bool
0352 renesas_sdhi_internal_dmac_map(struct tmio_mmc_host *host,
0353                    struct mmc_data *data,
0354                    enum renesas_sdhi_dma_cookie cookie)
0355 {
0356     if (data->host_cookie == COOKIE_PRE_MAPPED)
0357         return true;
0358
0359     if (!dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
0360                 mmc_get_dma_dir(data)))
0361         return false;
0362
0363     data->host_cookie = cookie;
0364
0365     /* This DMAC needs buffers to be 128-byte aligned */
0366     if (!IS_ALIGNED(sg_dma_address(data->sg), 128)) {
0367         renesas_sdhi_internal_dmac_unmap(host, data, cookie);
0368         return false;
0369     }
0370
0371     return true;
0372 }
0373
0374 static void
0375 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
0376                      struct mmc_data *data)
0377 {
0378     struct renesas_sdhi *priv = host_to_priv(host);
0379     struct scatterlist *sg = host->sg_ptr;
0380     u32 dtran_mode = DTRAN_MODE_BUS_WIDTH;
0381
0382     if (!(priv->quirks && priv->quirks->fixed_addr_mode))
0383         dtran_mode |= DTRAN_MODE_ADDR_MODE;
0384
0385     if (!renesas_sdhi_internal_dmac_map(host, data, COOKIE_MAPPED))
0386         goto force_pio;
0387
0388     if (data->flags & MMC_DATA_READ) {
0389         dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
0390         if (priv->quirks && priv->quirks->dma_one_rx_only &&
0391             test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags))
0392             goto force_pio_with_unmap;
0393     } else {
0394         dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
0395     }
0396
0397     renesas_sdhi_internal_dmac_enable_dma(host, true);
0398
0399     /* set dma parameters */
0400     renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
0401                         dtran_mode);
0402     renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
0403                         sg_dma_address(sg));
0404
0405     host->dma_on = true;
0406
0407     return;
0408
0409 force_pio_with_unmap:
0410     renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED);
0411
0412 force_pio:
0413     renesas_sdhi_internal_dmac_enable_dma(host, false);
0414 }
0415
0416 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
0417 {
0418     struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
0419
0420     tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
0421
0422     /* start the DMAC */
0423     renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
0424                         DTRAN_CTRL_DM_START);
0425 }
0426
0427 static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host)
0428 {
0429     enum dma_data_direction dir;
0430
0431     if (!host->dma_on)
0432         return false;
0433
0434     if (!host->data)
0435         return false;
0436
0437     if (host->data->flags & MMC_DATA_READ)
0438         dir = DMA_FROM_DEVICE;
0439     else
0440         dir = DMA_TO_DEVICE;
0441
0442     renesas_sdhi_internal_dmac_enable_dma(host, false);
0443     renesas_sdhi_internal_dmac_unmap(host, host->data, COOKIE_MAPPED);
0444
0445     if (dir == DMA_FROM_DEVICE)
0446         clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
0447
0448     host->dma_on = false;
0449
0450     return true;
0451 }
0452
0453 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
0454 {
0455     struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
0456
0457     spin_lock_irq(&host->lock);
0458     if (!renesas_sdhi_internal_dmac_complete(host))
0459         goto out;
0460
0461     tmio_mmc_do_data_irq(host);
0462 out:
0463     spin_unlock_irq(&host->lock);
0464 }
0465
0466 static void renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host *host)
0467 {
0468     if (host->data)
0469         renesas_sdhi_internal_dmac_complete(host);
0470 }
0471
0472 static void renesas_sdhi_internal_dmac_post_req(struct mmc_host *mmc,
0473                         struct mmc_request *mrq,
0474                         int err)
0475 {
0476     struct tmio_mmc_host *host = mmc_priv(mmc);
0477     struct mmc_data *data = mrq->data;
0478
0479     if (!data)
0480         return;
0481
0482     renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED);
0483 }
0484
0485 static void renesas_sdhi_internal_dmac_pre_req(struct mmc_host *mmc,
0486                            struct mmc_request *mrq)
0487 {
0488     struct tmio_mmc_host *host = mmc_priv(mmc);
0489     struct mmc_data *data = mrq->data;
0490
0491     if (!data)
0492         return;
0493
0494     data->host_cookie = COOKIE_UNMAPPED;
0495     renesas_sdhi_internal_dmac_map(host, data, COOKIE_PRE_MAPPED);
0496 }
0497
0498 static void
0499 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
0500                        struct tmio_mmc_data *pdata)
0501 {
0502     struct renesas_sdhi *priv = host_to_priv(host);
0503
0504     /* Disable DMAC interrupts, we don't use them */
0505     renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK,
0506                         INFO1_MASK_CLEAR);
0507     renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK,
0508                         INFO2_MASK_CLEAR);
0509
0510     /* Each value is set to non-zero to assume "enabling" each DMA */
0511     host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
0512
0513     tasklet_init(&priv->dma_priv.dma_complete,
0514              renesas_sdhi_internal_dmac_complete_tasklet_fn,
0515              (unsigned long)host);
0516     tasklet_init(&host->dma_issue,
0517              renesas_sdhi_internal_dmac_issue_tasklet_fn,
0518              (unsigned long)host);
0519
0520     /* Add pre_req and post_req */
0521     host->ops.pre_req = renesas_sdhi_internal_dmac_pre_req;
0522     host->ops.post_req = renesas_sdhi_internal_dmac_post_req;
0523 }
0524
0525 static void
0526 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
0527 {
0528     /* Each value is set to zero to assume "disabling" each DMA */
0529     host->chan_rx = host->chan_tx = NULL;
0530 }
0531
0532 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
0533     .start = renesas_sdhi_internal_dmac_start_dma,
0534     .enable = renesas_sdhi_internal_dmac_enable_dma,
0535     .request = renesas_sdhi_internal_dmac_request_dma,
0536     .release = renesas_sdhi_internal_dmac_release_dma,
0537     .abort = renesas_sdhi_internal_dmac_abort_dma,
0538     .dataend = renesas_sdhi_internal_dmac_dataend_dma,
0539     .end = renesas_sdhi_internal_dmac_end_dma,
0540 };
0541
0542 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
0543 {
0544     const struct soc_device_attribute *attr;
0545     const struct renesas_sdhi_of_data_with_quirks *of_data_quirks;
0546     const struct renesas_sdhi_quirks *quirks;
0547     struct device *dev = &pdev->dev;
0548
0549     of_data_quirks = of_device_get_match_data(&pdev->dev);
0550     quirks = of_data_quirks->quirks;
0551
0552     attr = soc_device_match(sdhi_quirks_match);
0553     if (attr)
0554         quirks = attr->data;
0555
0556     /* value is max of SD_SECCNT. Confirmed by HW engineers */
0557     dma_set_max_seg_size(dev, 0xffffffff);
0558
0559     return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops,
0560                   of_data_quirks->of_data, quirks);
0561 }
0562
0563 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
0564     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0565                 pm_runtime_force_resume)
0566     SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
0567                tmio_mmc_host_runtime_resume,
0568                NULL)
0569 };
0570
0571 static struct platform_driver renesas_internal_dmac_sdhi_driver = {
0572     .driver     = {
0573         .name   = "renesas_sdhi_internal_dmac",
0574         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0575         .pm = &renesas_sdhi_internal_dmac_dev_pm_ops,
0576         .of_match_table = renesas_sdhi_internal_dmac_of_match,
0577     },
0578     .probe      = renesas_sdhi_internal_dmac_probe,
0579     .remove     = renesas_sdhi_remove,
0580 };
0581
0582 module_platform_driver(renesas_internal_dmac_sdhi_driver);
0583
0584 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
0585 MODULE_AUTHOR("Yoshihiro Shimoda");
0586 MODULE_LICENSE("GPL v2");