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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas SDHI
0004  *
0005  * Copyright (C) 2015-19 Renesas Electronics Corporation
0006  * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
0007  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
0008  * Copyright (C) 2009 Magnus Damm
0009  *
0010  * Based on "Compaq ASIC3 support":
0011  *
0012  * Copyright 2001 Compaq Computer Corporation.
0013  * Copyright 2004-2005 Phil Blundell
0014  * Copyright 2007-2008 OpenedHand Ltd.
0015  *
0016  * Authors: Phil Blundell <pb@handhelds.org>,
0017  *      Samuel Ortiz <sameo@openedhand.com>
0018  *
0019  */
0020 
0021 #include <linux/clk.h>
0022 #include <linux/delay.h>
0023 #include <linux/iopoll.h>
0024 #include <linux/kernel.h>
0025 #include <linux/mfd/tmio.h>
0026 #include <linux/mmc/host.h>
0027 #include <linux/mmc/mmc.h>
0028 #include <linux/mmc/slot-gpio.h>
0029 #include <linux/module.h>
0030 #include <linux/pinctrl/consumer.h>
0031 #include <linux/pinctrl/pinctrl-state.h>
0032 #include <linux/platform_device.h>
0033 #include <linux/pm_domain.h>
0034 #include <linux/regulator/consumer.h>
0035 #include <linux/reset.h>
0036 #include <linux/sh_dma.h>
0037 #include <linux/slab.h>
0038 
0039 #include "renesas_sdhi.h"
0040 #include "tmio_mmc.h"
0041 
0042 #define CTL_HOST_MODE   0xe4
0043 #define HOST_MODE_GEN2_SDR50_WMODE  BIT(0)
0044 #define HOST_MODE_GEN2_SDR104_WMODE BIT(0)
0045 #define HOST_MODE_GEN3_WMODE        BIT(0)
0046 #define HOST_MODE_GEN3_BUSWIDTH     BIT(8)
0047 
0048 #define HOST_MODE_GEN3_16BIT    HOST_MODE_GEN3_WMODE
0049 #define HOST_MODE_GEN3_32BIT    (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH)
0050 #define HOST_MODE_GEN3_64BIT    0
0051 
0052 #define SDHI_VER_GEN2_SDR50 0x490c
0053 #define SDHI_VER_RZ_A1      0x820b
0054 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
0055 #define SDHI_VER_GEN2_SDR104    0xcb0d
0056 #define SDHI_VER_GEN3_SD    0xcc10
0057 #define SDHI_VER_GEN3_SDMMC 0xcd10
0058 
0059 #define SDHI_GEN3_MMC0_ADDR 0xee140000
0060 
0061 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
0062 {
0063     u32 val;
0064 
0065     /*
0066      * see also
0067      *  renesas_sdhi_of_data :: dma_buswidth
0068      */
0069     switch (sd_ctrl_read16(host, CTL_VERSION)) {
0070     case SDHI_VER_GEN2_SDR50:
0071         val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0;
0072         break;
0073     case SDHI_VER_GEN2_SDR104:
0074         val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE;
0075         break;
0076     case SDHI_VER_GEN3_SD:
0077     case SDHI_VER_GEN3_SDMMC:
0078         if (width == 64)
0079             val = HOST_MODE_GEN3_64BIT;
0080         else if (width == 32)
0081             val = HOST_MODE_GEN3_32BIT;
0082         else
0083             val = HOST_MODE_GEN3_16BIT;
0084         break;
0085     default:
0086         /* nothing to do */
0087         return;
0088     }
0089 
0090     sd_ctrl_write16(host, CTL_HOST_MODE, val);
0091 }
0092 
0093 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
0094 {
0095     struct mmc_host *mmc = host->mmc;
0096     struct renesas_sdhi *priv = host_to_priv(host);
0097     int ret;
0098 
0099     ret = clk_prepare_enable(priv->clk_cd);
0100     if (ret < 0)
0101         return ret;
0102 
0103     /*
0104      * The clock driver may not know what maximum frequency
0105      * actually works, so it should be set with the max-frequency
0106      * property which will already have been read to f_max.  If it
0107      * was missing, assume the current frequency is the maximum.
0108      */
0109     if (!mmc->f_max)
0110         mmc->f_max = clk_get_rate(priv->clk);
0111 
0112     /*
0113      * Minimum frequency is the minimum input clock frequency
0114      * divided by our maximum divider.
0115      */
0116     mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
0117 
0118     /* enable 16bit data access on SDBUF as default */
0119     renesas_sdhi_sdbuf_width(host, 16);
0120 
0121     return 0;
0122 }
0123 
0124 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
0125                         unsigned int wanted_clock)
0126 {
0127     struct renesas_sdhi *priv = host_to_priv(host);
0128     struct clk *ref_clk = priv->clk;
0129     unsigned int freq, diff, best_freq = 0, diff_min = ~0;
0130     unsigned int new_clock, clkh_shift = 0;
0131     int i;
0132 
0133     /*
0134      * We simply return the current rate if a) we are not on a R-Car Gen2+
0135      * SoC (may work for others, but untested) or b) if the SCC needs its
0136      * clock during tuning, so we don't change the external clock setup.
0137      */
0138     if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc))
0139         return clk_get_rate(priv->clk);
0140 
0141     if (priv->clkh) {
0142         /* HS400 with 4TAP needs different clock settings */
0143         bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
0144         bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400;
0145         clkh_shift = use_4tap && need_slow_clkh ? 1 : 2;
0146         ref_clk = priv->clkh;
0147     }
0148 
0149     new_clock = wanted_clock << clkh_shift;
0150 
0151     /*
0152      * We want the bus clock to be as close as possible to, but no
0153      * greater than, new_clock.  As we can divide by 1 << i for
0154      * any i in [0, 9] we want the input clock to be as close as
0155      * possible, but no greater than, new_clock << i.
0156      */
0157     for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
0158         freq = clk_round_rate(ref_clk, new_clock << i);
0159         if (freq > (new_clock << i)) {
0160             /* Too fast; look for a slightly slower option */
0161             freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3);
0162             if (freq > (new_clock << i))
0163                 continue;
0164         }
0165 
0166         diff = new_clock - (freq >> i);
0167         if (diff <= diff_min) {
0168             best_freq = freq;
0169             diff_min = diff;
0170         }
0171     }
0172 
0173     clk_set_rate(ref_clk, best_freq);
0174 
0175     if (priv->clkh)
0176         clk_set_rate(priv->clk, best_freq >> clkh_shift);
0177 
0178     return clk_get_rate(priv->clk);
0179 }
0180 
0181 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
0182                    unsigned int new_clock)
0183 {
0184     u32 clk = 0, clock;
0185 
0186     sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
0187         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
0188 
0189     if (new_clock == 0) {
0190         host->mmc->actual_clock = 0;
0191         goto out;
0192     }
0193 
0194     host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
0195     clock = host->mmc->actual_clock / 512;
0196 
0197     for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
0198         clock <<= 1;
0199 
0200     /* 1/1 clock is option */
0201     if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
0202         if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
0203             clk |= 0xff;
0204         else
0205             clk &= ~0xff;
0206     }
0207 
0208     sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
0209     if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
0210         usleep_range(10000, 11000);
0211 
0212     sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
0213         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
0214 
0215 out:
0216     /* HW engineers overrode docs: no sleep needed on R-Car2+ */
0217     if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
0218         usleep_range(10000, 11000);
0219 }
0220 
0221 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
0222 {
0223     struct renesas_sdhi *priv = host_to_priv(host);
0224 
0225     clk_disable_unprepare(priv->clk_cd);
0226 }
0227 
0228 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
0229 {
0230     struct tmio_mmc_host *host = mmc_priv(mmc);
0231 
0232     return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
0233          TMIO_STAT_DAT0);
0234 }
0235 
0236 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
0237                             struct mmc_ios *ios)
0238 {
0239     struct tmio_mmc_host *host = mmc_priv(mmc);
0240     struct renesas_sdhi *priv = host_to_priv(host);
0241     struct pinctrl_state *pin_state;
0242     int ret;
0243 
0244     switch (ios->signal_voltage) {
0245     case MMC_SIGNAL_VOLTAGE_330:
0246         pin_state = priv->pins_default;
0247         break;
0248     case MMC_SIGNAL_VOLTAGE_180:
0249         pin_state = priv->pins_uhs;
0250         break;
0251     default:
0252         return -EINVAL;
0253     }
0254 
0255     /*
0256      * If anything is missing, assume signal voltage is fixed at
0257      * 3.3V and succeed/fail accordingly.
0258      */
0259     if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
0260         return ios->signal_voltage ==
0261             MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
0262 
0263     ret = mmc_regulator_set_vqmmc(host->mmc, ios);
0264     if (ret < 0)
0265         return ret;
0266 
0267     return pinctrl_select_state(priv->pinctrl, pin_state);
0268 }
0269 
0270 /* SCC registers */
0271 #define SH_MOBILE_SDHI_SCC_DTCNTL   0x000
0272 #define SH_MOBILE_SDHI_SCC_TAPSET   0x002
0273 #define SH_MOBILE_SDHI_SCC_DT2FF    0x004
0274 #define SH_MOBILE_SDHI_SCC_CKSEL    0x006
0275 #define SH_MOBILE_SDHI_SCC_RVSCNTL  0x008
0276 #define SH_MOBILE_SDHI_SCC_RVSREQ   0x00A
0277 #define SH_MOBILE_SDHI_SCC_SMPCMP       0x00C
0278 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E
0279 #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014
0280 #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016
0281 #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018
0282 #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A
0283 #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C
0284 
0285 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN     BIT(0)
0286 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT  16
0287 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK   0xff
0288 
0289 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL      BIT(0)
0290 
0291 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN    BIT(0)
0292 
0293 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN    BIT(0)
0294 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP  BIT(1)
0295 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR    BIT(2)
0296 
0297 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN   BIT(8)
0298 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
0299 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR   (BIT(8) | BIT(24))
0300 
0301 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL   BIT(4)
0302 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
0303 
0304 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */
0305 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START   BIT(0)
0306 
0307 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */
0308 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R    BIT(8)
0309 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W    (0 << 8)
0310 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK    0x3F
0311 
0312 /* Definitions for values the SH_MOBILE_SDHI_SCC register */
0313 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE  0xa5000000
0314 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK  0x1f
0315 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE      BIT(7)
0316 
0317 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
0318                 struct renesas_sdhi *priv, int addr)
0319 {
0320     return readl(priv->scc_ctl + (addr << host->bus_shift));
0321 }
0322 
0323 static inline void sd_scc_write32(struct tmio_mmc_host *host,
0324                   struct renesas_sdhi *priv,
0325                   int addr, u32 val)
0326 {
0327     writel(val, priv->scc_ctl + (addr << host->bus_shift));
0328 }
0329 
0330 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
0331 {
0332     struct renesas_sdhi *priv;
0333 
0334     priv = host_to_priv(host);
0335 
0336     /* Initialize SCC */
0337     sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
0338 
0339     sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
0340             sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
0341 
0342     /* set sampling clock selection range */
0343     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
0344                SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
0345                0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
0346 
0347     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
0348                SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
0349                sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
0350 
0351     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
0352                ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
0353                sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
0354 
0355     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
0356 
0357     sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
0358             sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
0359 
0360     /* Read TAPNUM */
0361     return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
0362         SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
0363         SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
0364 }
0365 
0366 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc)
0367 {
0368     struct tmio_mmc_host *host = mmc_priv(mmc);
0369     struct renesas_sdhi *priv = host_to_priv(host);
0370     u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
0371     bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
0372 
0373     sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
0374         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
0375 
0376     /* Set HS400 mode */
0377     sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 |
0378             sd_ctrl_read16(host, CTL_SDIF_MODE));
0379 
0380     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
0381                priv->scc_tappos_hs400);
0382 
0383     if (priv->quirks && priv->quirks->manual_tap_correction)
0384         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
0385                    ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
0386                    sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
0387 
0388     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
0389                (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
0390             SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
0391             sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
0392 
0393     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
0394                SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
0395                sd_scc_read32(host, priv,
0396                      SH_MOBILE_SDHI_SCC_DTCNTL));
0397 
0398     /* Avoid bad TAP */
0399     if (bad_taps & BIT(priv->tap_set)) {
0400         u32 new_tap = (priv->tap_set + 1) % priv->tap_num;
0401 
0402         if (bad_taps & BIT(new_tap))
0403             new_tap = (priv->tap_set - 1) % priv->tap_num;
0404 
0405         if (bad_taps & BIT(new_tap)) {
0406             new_tap = priv->tap_set;
0407             dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n");
0408         }
0409 
0410         priv->tap_set = new_tap;
0411     }
0412 
0413     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
0414                priv->tap_set / (use_4tap ? 2 : 1));
0415 
0416     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
0417                SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
0418                sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
0419 
0420     sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
0421             sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
0422 
0423     if (priv->adjust_hs400_calib_table)
0424         priv->needs_adjust_hs400 = true;
0425 }
0426 
0427 static void renesas_sdhi_disable_scc(struct mmc_host *mmc)
0428 {
0429     struct tmio_mmc_host *host = mmc_priv(mmc);
0430     struct renesas_sdhi *priv = host_to_priv(host);
0431 
0432     sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
0433             sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
0434 
0435     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
0436                ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
0437                sd_scc_read32(host, priv,
0438                      SH_MOBILE_SDHI_SCC_CKSEL));
0439 
0440     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
0441                ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
0442                sd_scc_read32(host, priv,
0443                      SH_MOBILE_SDHI_SCC_DTCNTL));
0444 
0445     sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
0446             sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
0447 }
0448 
0449 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host,
0450                  struct renesas_sdhi *priv, u32 addr)
0451 {
0452     /* read mode */
0453     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
0454                SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
0455                (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
0456 
0457     /* access start and stop */
0458     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
0459                SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
0460     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
0461 
0462     return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7);
0463 }
0464 
0465 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host,
0466                    struct renesas_sdhi *priv, u32 addr, u32 val)
0467 {
0468     /* write mode */
0469     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
0470                SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
0471                (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
0472 
0473     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val);
0474 
0475     /* access start and stop */
0476     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
0477                SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
0478     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
0479 }
0480 
0481 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host)
0482 {
0483     struct renesas_sdhi *priv = host_to_priv(host);
0484     u32 calib_code;
0485 
0486     /* disable write protect */
0487     sd_scc_tmpport_write32(host, priv, 0x00,
0488                    SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
0489     /* read calibration code and adjust */
0490     calib_code = sd_scc_tmpport_read32(host, priv, 0x26);
0491     calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
0492 
0493     sd_scc_tmpport_write32(host, priv, 0x22,
0494                    SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE |
0495                    priv->adjust_hs400_calib_table[calib_code]);
0496 
0497     /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */
0498     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3);
0499 
0500     /* adjustment done, clear flag */
0501     priv->needs_adjust_hs400 = false;
0502 }
0503 
0504 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host)
0505 {
0506     struct renesas_sdhi *priv = host_to_priv(host);
0507 
0508     /* disable write protect */
0509     sd_scc_tmpport_write32(host, priv, 0x00,
0510                    SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
0511     /* disable manual calibration */
0512     sd_scc_tmpport_write32(host, priv, 0x22, 0);
0513     /* clear offset value of TMPPORT3 */
0514     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0);
0515 }
0516 
0517 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
0518                       struct renesas_sdhi *priv)
0519 {
0520     sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
0521             sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
0522 
0523     /* Reset HS400 mode */
0524     sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 &
0525             sd_ctrl_read16(host, CTL_SDIF_MODE));
0526 
0527     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
0528 
0529     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
0530                ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
0531              SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
0532             sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
0533 
0534     if (priv->adjust_hs400_calib_table)
0535         renesas_sdhi_adjust_hs400_mode_disable(host);
0536 
0537     sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
0538             sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
0539 }
0540 
0541 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
0542 {
0543     struct tmio_mmc_host *host = mmc_priv(mmc);
0544 
0545     renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
0546     return 0;
0547 }
0548 
0549 static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv)
0550 {
0551     renesas_sdhi_disable_scc(host->mmc);
0552     renesas_sdhi_reset_hs400_mode(host, priv);
0553     priv->needs_adjust_hs400 = false;
0554 
0555     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
0556                ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
0557                sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
0558 }
0559 
0560 /* only populated for TMIO_MMC_MIN_RCAR2 */
0561 static void renesas_sdhi_reset(struct tmio_mmc_host *host, bool preserve)
0562 {
0563     struct renesas_sdhi *priv = host_to_priv(host);
0564     int ret;
0565     u16 val;
0566 
0567     if (!preserve) {
0568         if (priv->rstc) {
0569             reset_control_reset(priv->rstc);
0570             /* Unknown why but without polling reset status, it will hang */
0571             read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100,
0572                       false, priv->rstc);
0573             /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */
0574             sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
0575             priv->needs_adjust_hs400 = false;
0576             renesas_sdhi_set_clock(host, host->clk_cache);
0577         } else if (priv->scc_ctl) {
0578             renesas_sdhi_scc_reset(host, priv);
0579         }
0580     }
0581 
0582     if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) {
0583         val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
0584         val |= CARD_OPT_EXTOP;
0585         sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val);
0586     }
0587 }
0588 
0589 static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host)
0590 {
0591     u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
0592 
0593     num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT;
0594     return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num);
0595 
0596 }
0597 
0598 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3
0599 
0600 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
0601 {
0602     struct renesas_sdhi *priv = host_to_priv(host);
0603     unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i;
0604     unsigned int taps_size = priv->tap_num * 2, min_tap_row;
0605     unsigned long *bitmap;
0606 
0607     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
0608 
0609     /*
0610      * When tuning CMD19 is issued twice for each tap, merge the
0611      * result requiring the tap to be good in both runs before
0612      * considering it for tuning selection.
0613      */
0614     for (i = 0; i < taps_size; i++) {
0615         int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1);
0616 
0617         if (!test_bit(i, priv->taps))
0618             clear_bit(i + offset, priv->taps);
0619 
0620         if (!test_bit(i, priv->smpcmp))
0621             clear_bit(i + offset, priv->smpcmp);
0622     }
0623 
0624     /*
0625      * If all TAP are OK, the sampling clock position is selected by
0626      * identifying the change point of data.
0627      */
0628     if (bitmap_full(priv->taps, taps_size)) {
0629         bitmap = priv->smpcmp;
0630         min_tap_row = 1;
0631     } else {
0632         bitmap = priv->taps;
0633         min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW;
0634     }
0635 
0636     /*
0637      * Find the longest consecutive run of successful probes. If that
0638      * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the
0639      * center index as the tap, otherwise bail out.
0640      */
0641     for_each_set_bitrange(rs, re, bitmap, taps_size) {
0642         if (re - rs > tap_cnt) {
0643             tap_end = re;
0644             tap_start = rs;
0645             tap_cnt = tap_end - tap_start;
0646         }
0647     }
0648 
0649     if (tap_cnt >= min_tap_row)
0650         priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num;
0651     else
0652         return -EIO;
0653 
0654     /* Set SCC */
0655     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set);
0656 
0657     /* Enable auto re-tuning */
0658     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
0659                SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
0660                sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
0661 
0662     return 0;
0663 }
0664 
0665 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode)
0666 {
0667     struct tmio_mmc_host *host = mmc_priv(mmc);
0668     struct renesas_sdhi *priv = host_to_priv(host);
0669     int i, ret;
0670 
0671     priv->tap_num = renesas_sdhi_init_tuning(host);
0672     if (!priv->tap_num)
0673         return 0; /* Tuning is not supported */
0674 
0675     if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
0676         dev_err(&host->pdev->dev,
0677             "Too many taps, please update 'taps' in tmio_mmc_host!\n");
0678         return -EINVAL;
0679     }
0680 
0681     bitmap_zero(priv->taps, priv->tap_num * 2);
0682     bitmap_zero(priv->smpcmp, priv->tap_num * 2);
0683 
0684     /* Issue CMD19 twice for each tap */
0685     for (i = 0; i < 2 * priv->tap_num; i++) {
0686         int cmd_error = 0;
0687 
0688         /* Set sampling clock position */
0689         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
0690 
0691         if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0)
0692             set_bit(i, priv->taps);
0693 
0694         if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0)
0695             set_bit(i, priv->smpcmp);
0696 
0697         if (cmd_error)
0698             mmc_send_abort_tuning(mmc, opcode);
0699     }
0700 
0701     ret = renesas_sdhi_select_tuning(host);
0702     if (ret < 0)
0703         renesas_sdhi_scc_reset(host, priv);
0704     return ret;
0705 }
0706 
0707 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
0708 {
0709     struct renesas_sdhi *priv = host_to_priv(host);
0710     unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set;
0711     u32 val;
0712 
0713     val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
0714     if (!val)
0715         return false;
0716 
0717     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
0718 
0719     /* Change TAP position according to correction status */
0720     if (priv->quirks && priv->quirks->manual_tap_correction &&
0721         host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
0722         u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
0723         /*
0724          * With HS400, the DAT signal is based on DS, not CLK.
0725          * Therefore, use only CMD status.
0726          */
0727         u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
0728                        SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
0729         if (!smpcmp) {
0730             return false;   /* no error in CMD signal */
0731         } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) {
0732             new_tap++;
0733             error_tap--;
0734         } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) {
0735             new_tap--;
0736             error_tap++;
0737         } else {
0738             return true;    /* need retune */
0739         }
0740 
0741         /*
0742          * When new_tap is a bad tap, we cannot change. Then, we compare
0743          * with the HS200 tuning result. When smpcmp[error_tap] is OK,
0744          * we can at least retune.
0745          */
0746         if (bad_taps & BIT(new_tap % priv->tap_num))
0747             return test_bit(error_tap % priv->tap_num, priv->smpcmp);
0748     } else {
0749         if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
0750             return true;    /* need retune */
0751         else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
0752             new_tap++;
0753         else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
0754             new_tap--;
0755         else
0756             return false;
0757     }
0758 
0759     priv->tap_set = (new_tap % priv->tap_num);
0760     sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
0761                priv->tap_set / (use_4tap ? 2 : 1));
0762 
0763     return false;
0764 }
0765 
0766 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host)
0767 {
0768     struct renesas_sdhi *priv = host_to_priv(host);
0769 
0770     /* Check SCC error */
0771     if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
0772         SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
0773         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
0774         return true;
0775     }
0776 
0777     return false;
0778 }
0779 
0780 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host,
0781                      struct mmc_request *mrq)
0782 {
0783     struct renesas_sdhi *priv = host_to_priv(host);
0784     bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
0785     bool ret = false;
0786 
0787     /*
0788      * Skip checking SCC errors when running on 4 taps in HS400 mode as
0789      * any retuning would still result in the same 4 taps being used.
0790      */
0791     if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
0792         !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
0793         !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
0794         return false;
0795 
0796     if (mmc_doing_tune(host->mmc))
0797         return false;
0798 
0799     if (((mrq->cmd->error == -ETIMEDOUT) ||
0800          (mrq->data && mrq->data->error == -ETIMEDOUT)) &&
0801         ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
0802          (host->ops.get_cd && host->ops.get_cd(host->mmc))))
0803         ret |= true;
0804 
0805     if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
0806         SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN)
0807         ret |= renesas_sdhi_auto_correction(host);
0808     else
0809         ret |= renesas_sdhi_manual_correction(host, use_4tap);
0810 
0811     return ret;
0812 }
0813 
0814 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
0815 {
0816     int timeout = 1000;
0817     /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
0818     u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
0819 
0820     while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
0821                   & bit) == wait_state)
0822         udelay(1);
0823 
0824     if (!timeout) {
0825         dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
0826         return -EBUSY;
0827     }
0828 
0829     return 0;
0830 }
0831 
0832 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
0833 {
0834     u32 bit = TMIO_STAT_SCLKDIVEN;
0835 
0836     switch (addr) {
0837     case CTL_SD_CMD:
0838     case CTL_STOP_INTERNAL_ACTION:
0839     case CTL_XFER_BLK_COUNT:
0840     case CTL_SD_XFER_LEN:
0841     case CTL_SD_MEM_CARD_OPT:
0842     case CTL_TRANSACTION_CTL:
0843     case CTL_DMA_ENABLE:
0844     case CTL_HOST_MODE:
0845         if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
0846             bit = TMIO_STAT_CMD_BUSY;
0847         fallthrough;
0848     case CTL_SD_CARD_CLK_CTL:
0849         return renesas_sdhi_wait_idle(host, bit);
0850     }
0851 
0852     return 0;
0853 }
0854 
0855 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
0856                        unsigned int direction, int blk_size)
0857 {
0858     /*
0859      * In Renesas controllers, when performing a
0860      * multiple block read of one or two blocks,
0861      * depending on the timing with which the
0862      * response register is read, the response
0863      * value may not be read properly.
0864      * Use single block read for this HW bug
0865      */
0866     if ((direction == MMC_DATA_READ) &&
0867         blk_size == 2)
0868         return 1;
0869 
0870     return blk_size;
0871 }
0872 
0873 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq)
0874 {
0875     struct renesas_sdhi *priv = host_to_priv(host);
0876 
0877     if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS)
0878         renesas_sdhi_adjust_hs400_mode_enable(host);
0879 }
0880 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
0881 {
0882     /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
0883     int width = (host->bus_shift == 2) ? 64 : 32;
0884 
0885     sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
0886     renesas_sdhi_sdbuf_width(host, enable ? width : 16);
0887 }
0888 
0889 int renesas_sdhi_probe(struct platform_device *pdev,
0890                const struct tmio_mmc_dma_ops *dma_ops,
0891                const struct renesas_sdhi_of_data *of_data,
0892                const struct renesas_sdhi_quirks *quirks)
0893 {
0894     struct tmio_mmc_data *mmd = pdev->dev.platform_data;
0895     struct tmio_mmc_data *mmc_data;
0896     struct tmio_mmc_dma *dma_priv;
0897     struct tmio_mmc_host *host;
0898     struct renesas_sdhi *priv;
0899     int num_irqs, irq, ret, i;
0900     struct resource *res;
0901     u16 ver;
0902 
0903     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0904     if (!res)
0905         return -EINVAL;
0906 
0907     priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
0908                 GFP_KERNEL);
0909     if (!priv)
0910         return -ENOMEM;
0911 
0912     priv->quirks = quirks;
0913     mmc_data = &priv->mmc_data;
0914     dma_priv = &priv->dma_priv;
0915 
0916     priv->clk = devm_clk_get(&pdev->dev, NULL);
0917     if (IS_ERR(priv->clk))
0918         return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), "cannot get clock");
0919 
0920     priv->clkh = devm_clk_get_optional(&pdev->dev, "clkh");
0921     if (IS_ERR(priv->clkh))
0922         return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkh), "cannot get clkh");
0923 
0924     /*
0925      * Some controllers provide a 2nd clock just to run the internal card
0926      * detection logic. Unfortunately, the existing driver architecture does
0927      * not support a separation of clocks for runtime PM usage. When
0928      * native hotplug is used, the tmio driver assumes that the core
0929      * must continue to run for card detect to stay active, so we cannot
0930      * disable it.
0931      * Additionally, it is prohibited to supply a clock to the core but not
0932      * to the card detect circuit. That leaves us with if separate clocks
0933      * are presented, we must treat them both as virtually 1 clock.
0934      */
0935     priv->clk_cd = devm_clk_get_optional(&pdev->dev, "cd");
0936     if (IS_ERR(priv->clk_cd))
0937         return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk_cd), "cannot get cd clock");
0938 
0939     priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
0940     if (IS_ERR(priv->rstc))
0941         return PTR_ERR(priv->rstc);
0942 
0943     priv->pinctrl = devm_pinctrl_get(&pdev->dev);
0944     if (!IS_ERR(priv->pinctrl)) {
0945         priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
0946                         PINCTRL_STATE_DEFAULT);
0947         priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
0948                         "state_uhs");
0949     }
0950 
0951     host = tmio_mmc_host_alloc(pdev, mmc_data);
0952     if (IS_ERR(host))
0953         return PTR_ERR(host);
0954 
0955     if (of_data) {
0956         mmc_data->flags |= of_data->tmio_flags;
0957         mmc_data->ocr_mask = of_data->tmio_ocr_mask;
0958         mmc_data->capabilities |= of_data->capabilities;
0959         mmc_data->capabilities2 |= of_data->capabilities2;
0960         mmc_data->dma_rx_offset = of_data->dma_rx_offset;
0961         mmc_data->max_blk_count = of_data->max_blk_count;
0962         mmc_data->max_segs = of_data->max_segs;
0963         dma_priv->dma_buswidth = of_data->dma_buswidth;
0964         host->bus_shift = of_data->bus_shift;
0965         /* Fallback for old DTs */
0966         if (!priv->clkh && of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK)
0967             priv->clkh = clk_get_parent(clk_get_parent(priv->clk));
0968 
0969     }
0970 
0971     host->write16_hook  = renesas_sdhi_write16_hook;
0972     host->clk_enable    = renesas_sdhi_clk_enable;
0973     host->clk_disable   = renesas_sdhi_clk_disable;
0974     host->set_clock     = renesas_sdhi_set_clock;
0975     host->multi_io_quirk    = renesas_sdhi_multi_io_quirk;
0976     host->dma_ops       = dma_ops;
0977 
0978     if (quirks && quirks->hs400_disabled)
0979         host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
0980 
0981     /* For some SoC, we disable internal WP. GPIO may override this */
0982     if (mmc_can_gpio_ro(host->mmc))
0983         mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
0984 
0985     /* SDR speeds are only available on Gen2+ */
0986     if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
0987         /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
0988         host->ops.card_busy = renesas_sdhi_card_busy;
0989         host->ops.start_signal_voltage_switch =
0990             renesas_sdhi_start_signal_voltage_switch;
0991         host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
0992         host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2;
0993         host->reset = renesas_sdhi_reset;
0994     }
0995 
0996     /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
0997     if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
0998         host->bus_shift = 1;
0999 
1000     if (mmd)
1001         *mmc_data = *mmd;
1002 
1003     dma_priv->filter = shdma_chan_filter;
1004     dma_priv->enable = renesas_sdhi_enable_dma;
1005 
1006     mmc_data->alignment_shift = 1; /* 2-byte alignment */
1007     mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1008 
1009     /*
1010      * All SDHI blocks support 2-byte and larger block sizes in 4-bit
1011      * bus width mode.
1012      */
1013     mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
1014 
1015     /*
1016      * All SDHI blocks support SDIO IRQ signalling.
1017      */
1018     mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
1019 
1020     /* All SDHI have CMD12 control bit */
1021     mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
1022 
1023     /* All SDHI have SDIO status bits which must be 1 */
1024     mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
1025 
1026     /* All SDHI support HW busy detection */
1027     mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT;
1028 
1029     dev_pm_domain_start(&pdev->dev);
1030 
1031     ret = renesas_sdhi_clk_enable(host);
1032     if (ret)
1033         goto efree;
1034 
1035     ver = sd_ctrl_read16(host, CTL_VERSION);
1036     /* GEN2_SDR104 is first known SDHI to use 32bit block count */
1037     if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
1038         mmc_data->max_blk_count = U16_MAX;
1039 
1040     /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
1041     if (ver == SDHI_VER_GEN2_SDR50)
1042         mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
1043 
1044     if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) {
1045         host->fixup_request = renesas_sdhi_fixup_request;
1046         priv->adjust_hs400_calib_table = *(
1047             res->start == SDHI_GEN3_MMC0_ADDR ?
1048             quirks->hs400_calib_table :
1049             quirks->hs400_calib_table + 1);
1050     }
1051 
1052     /* these have an EXTOP bit */
1053     if (ver >= SDHI_VER_GEN3_SD)
1054         host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles;
1055 
1056     /* Enable tuning iff we have an SCC and a supported mode */
1057     if (of_data && of_data->scc_offset &&
1058         (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
1059          host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
1060                  MMC_CAP2_HS400_1_8V))) {
1061         const struct renesas_sdhi_scc *taps = of_data->taps;
1062         bool use_4tap = quirks && quirks->hs400_4taps;
1063         bool hit = false;
1064 
1065         for (i = 0; i < of_data->taps_num; i++) {
1066             if (taps[i].clk_rate == 0 ||
1067                 taps[i].clk_rate == host->mmc->f_max) {
1068                 priv->scc_tappos = taps->tap;
1069                 priv->scc_tappos_hs400 = use_4tap ?
1070                              taps->tap_hs400_4tap :
1071                              taps->tap;
1072                 hit = true;
1073                 break;
1074             }
1075         }
1076 
1077         if (!hit)
1078             dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
1079 
1080         priv->scc_ctl = host->ctl + of_data->scc_offset;
1081         host->check_retune = renesas_sdhi_check_scc_error;
1082         host->ops.execute_tuning = renesas_sdhi_execute_tuning;
1083         host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
1084         host->ops.hs400_downgrade = renesas_sdhi_disable_scc;
1085         host->ops.hs400_complete = renesas_sdhi_hs400_complete;
1086     }
1087 
1088     ret = tmio_mmc_host_probe(host);
1089     if (ret < 0)
1090         goto edisclk;
1091 
1092     num_irqs = platform_irq_count(pdev);
1093     if (num_irqs < 0) {
1094         ret = num_irqs;
1095         goto eirq;
1096     }
1097 
1098     /* There must be at least one IRQ source */
1099     if (!num_irqs) {
1100         ret = -ENXIO;
1101         goto eirq;
1102     }
1103 
1104     for (i = 0; i < num_irqs; i++) {
1105         irq = platform_get_irq(pdev, i);
1106         if (irq < 0) {
1107             ret = irq;
1108             goto eirq;
1109         }
1110 
1111         ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
1112                        dev_name(&pdev->dev), host);
1113         if (ret)
1114             goto eirq;
1115     }
1116 
1117     dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n",
1118          mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000);
1119 
1120     return ret;
1121 
1122 eirq:
1123     tmio_mmc_host_remove(host);
1124 edisclk:
1125     renesas_sdhi_clk_disable(host);
1126 efree:
1127     tmio_mmc_host_free(host);
1128 
1129     return ret;
1130 }
1131 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
1132 
1133 int renesas_sdhi_remove(struct platform_device *pdev)
1134 {
1135     struct tmio_mmc_host *host = platform_get_drvdata(pdev);
1136 
1137     tmio_mmc_host_remove(host);
1138     renesas_sdhi_clk_disable(host);
1139     tmio_mmc_host_free(host);
1140 
1141     return 0;
1142 }
1143 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
1144 
1145 MODULE_LICENSE("GPL v2");
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