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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/drivers/mmc/host/pxa.c - PXA MMCI driver
0004  *
0005  *  Copyright (C) 2003 Russell King, All Rights Reserved.
0006  *
0007  *  This hardware is really sick:
0008  *   - No way to clear interrupts.
0009  *   - Have to turn off the clock whenever we touch the device.
0010  *   - Doesn't tell you how many data blocks were transferred.
0011  *  Yuck!
0012  *
0013  *  1 and 3 byte data transfers not supported
0014  *  max block length up to 1023
0015  */
0016 #include <linux/module.h>
0017 #include <linux/init.h>
0018 #include <linux/ioport.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/delay.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/dmaengine.h>
0023 #include <linux/dma-mapping.h>
0024 #include <linux/clk.h>
0025 #include <linux/err.h>
0026 #include <linux/mmc/host.h>
0027 #include <linux/mmc/slot-gpio.h>
0028 #include <linux/io.h>
0029 #include <linux/regulator/consumer.h>
0030 #include <linux/gpio/consumer.h>
0031 #include <linux/gfp.h>
0032 #include <linux/of.h>
0033 #include <linux/of_device.h>
0034 #include <linux/soc/pxa/cpu.h>
0035 
0036 #include <linux/sizes.h>
0037 
0038 #include <linux/platform_data/mmc-pxamci.h>
0039 
0040 #include "pxamci.h"
0041 
0042 #define DRIVER_NAME "pxa2xx-mci"
0043 
0044 #define NR_SG   1
0045 #define CLKRT_OFF   (~0)
0046 
0047 #define mmc_has_26MHz()     (cpu_is_pxa300() || cpu_is_pxa310() \
0048                 || cpu_is_pxa935())
0049 
0050 struct pxamci_host {
0051     struct mmc_host     *mmc;
0052     spinlock_t      lock;
0053     struct resource     *res;
0054     void __iomem        *base;
0055     struct clk      *clk;
0056     unsigned long       clkrate;
0057     unsigned int        clkrt;
0058     unsigned int        cmdat;
0059     unsigned int        imask;
0060     unsigned int        power_mode;
0061     unsigned long       detect_delay_ms;
0062     bool            use_ro_gpio;
0063     struct gpio_desc    *power;
0064     struct pxamci_platform_data *pdata;
0065 
0066     struct mmc_request  *mrq;
0067     struct mmc_command  *cmd;
0068     struct mmc_data     *data;
0069 
0070     struct dma_chan     *dma_chan_rx;
0071     struct dma_chan     *dma_chan_tx;
0072     dma_cookie_t        dma_cookie;
0073     unsigned int        dma_len;
0074     unsigned int        dma_dir;
0075 };
0076 
0077 static int pxamci_init_ocr(struct pxamci_host *host)
0078 {
0079     struct mmc_host *mmc = host->mmc;
0080     int ret;
0081 
0082     ret = mmc_regulator_get_supply(mmc);
0083     if (ret < 0)
0084         return ret;
0085 
0086     if (IS_ERR(mmc->supply.vmmc)) {
0087         /* fall-back to platform data */
0088         mmc->ocr_avail = host->pdata ?
0089             host->pdata->ocr_mask :
0090             MMC_VDD_32_33 | MMC_VDD_33_34;
0091     }
0092 
0093     return 0;
0094 }
0095 
0096 static inline int pxamci_set_power(struct pxamci_host *host,
0097                     unsigned char power_mode,
0098                     unsigned int vdd)
0099 {
0100     struct mmc_host *mmc = host->mmc;
0101     struct regulator *supply = mmc->supply.vmmc;
0102 
0103     if (!IS_ERR(supply))
0104         return mmc_regulator_set_ocr(mmc, supply, vdd);
0105 
0106     if (host->power) {
0107         bool on = !!((1 << vdd) & host->pdata->ocr_mask);
0108         gpiod_set_value(host->power, on);
0109     }
0110 
0111     if (host->pdata && host->pdata->setpower)
0112         return host->pdata->setpower(mmc_dev(host->mmc), vdd);
0113 
0114     return 0;
0115 }
0116 
0117 static void pxamci_stop_clock(struct pxamci_host *host)
0118 {
0119     if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
0120         unsigned long timeout = 10000;
0121         unsigned int v;
0122 
0123         writel(STOP_CLOCK, host->base + MMC_STRPCL);
0124 
0125         do {
0126             v = readl(host->base + MMC_STAT);
0127             if (!(v & STAT_CLK_EN))
0128                 break;
0129             udelay(1);
0130         } while (timeout--);
0131 
0132         if (v & STAT_CLK_EN)
0133             dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
0134     }
0135 }
0136 
0137 static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
0138 {
0139     unsigned long flags;
0140 
0141     spin_lock_irqsave(&host->lock, flags);
0142     host->imask &= ~mask;
0143     writel(host->imask, host->base + MMC_I_MASK);
0144     spin_unlock_irqrestore(&host->lock, flags);
0145 }
0146 
0147 static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
0148 {
0149     unsigned long flags;
0150 
0151     spin_lock_irqsave(&host->lock, flags);
0152     host->imask |= mask;
0153     writel(host->imask, host->base + MMC_I_MASK);
0154     spin_unlock_irqrestore(&host->lock, flags);
0155 }
0156 
0157 static void pxamci_dma_irq(void *param);
0158 
0159 static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
0160 {
0161     struct dma_async_tx_descriptor *tx;
0162     enum dma_transfer_direction direction;
0163     struct dma_slave_config config;
0164     struct dma_chan *chan;
0165     unsigned int nob = data->blocks;
0166     unsigned long long clks;
0167     unsigned int timeout;
0168     int ret;
0169 
0170     host->data = data;
0171 
0172     writel(nob, host->base + MMC_NOB);
0173     writel(data->blksz, host->base + MMC_BLKLEN);
0174 
0175     clks = (unsigned long long)data->timeout_ns * host->clkrate;
0176     do_div(clks, 1000000000UL);
0177     timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
0178     writel((timeout + 255) / 256, host->base + MMC_RDTO);
0179 
0180     memset(&config, 0, sizeof(config));
0181     config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
0182     config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
0183     config.src_addr = host->res->start + MMC_RXFIFO;
0184     config.dst_addr = host->res->start + MMC_TXFIFO;
0185     config.src_maxburst = 32;
0186     config.dst_maxburst = 32;
0187 
0188     if (data->flags & MMC_DATA_READ) {
0189         host->dma_dir = DMA_FROM_DEVICE;
0190         direction = DMA_DEV_TO_MEM;
0191         chan = host->dma_chan_rx;
0192     } else {
0193         host->dma_dir = DMA_TO_DEVICE;
0194         direction = DMA_MEM_TO_DEV;
0195         chan = host->dma_chan_tx;
0196     }
0197 
0198     config.direction = direction;
0199 
0200     ret = dmaengine_slave_config(chan, &config);
0201     if (ret < 0) {
0202         dev_err(mmc_dev(host->mmc), "dma slave config failed\n");
0203         return;
0204     }
0205 
0206     host->dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
0207                    host->dma_dir);
0208 
0209     tx = dmaengine_prep_slave_sg(chan, data->sg, host->dma_len, direction,
0210                      DMA_PREP_INTERRUPT);
0211     if (!tx) {
0212         dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
0213         return;
0214     }
0215 
0216     if (!(data->flags & MMC_DATA_READ)) {
0217         tx->callback = pxamci_dma_irq;
0218         tx->callback_param = host;
0219     }
0220 
0221     host->dma_cookie = dmaengine_submit(tx);
0222 
0223     /*
0224      * workaround for erratum #91:
0225      * only start DMA now if we are doing a read,
0226      * otherwise we wait until CMD/RESP has finished
0227      * before starting DMA.
0228      */
0229     if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ)
0230         dma_async_issue_pending(chan);
0231 }
0232 
0233 static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
0234 {
0235     WARN_ON(host->cmd != NULL);
0236     host->cmd = cmd;
0237 
0238     if (cmd->flags & MMC_RSP_BUSY)
0239         cmdat |= CMDAT_BUSY;
0240 
0241 #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
0242     switch (RSP_TYPE(mmc_resp_type(cmd))) {
0243     case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
0244         cmdat |= CMDAT_RESP_SHORT;
0245         break;
0246     case RSP_TYPE(MMC_RSP_R3):
0247         cmdat |= CMDAT_RESP_R3;
0248         break;
0249     case RSP_TYPE(MMC_RSP_R2):
0250         cmdat |= CMDAT_RESP_R2;
0251         break;
0252     default:
0253         break;
0254     }
0255 
0256     writel(cmd->opcode, host->base + MMC_CMD);
0257     writel(cmd->arg >> 16, host->base + MMC_ARGH);
0258     writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
0259     writel(cmdat, host->base + MMC_CMDAT);
0260     writel(host->clkrt, host->base + MMC_CLKRT);
0261 
0262     writel(START_CLOCK, host->base + MMC_STRPCL);
0263 
0264     pxamci_enable_irq(host, END_CMD_RES);
0265 }
0266 
0267 static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
0268 {
0269     host->mrq = NULL;
0270     host->cmd = NULL;
0271     host->data = NULL;
0272     mmc_request_done(host->mmc, mrq);
0273 }
0274 
0275 static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
0276 {
0277     struct mmc_command *cmd = host->cmd;
0278     int i;
0279     u32 v;
0280 
0281     if (!cmd)
0282         return 0;
0283 
0284     host->cmd = NULL;
0285 
0286     /*
0287      * Did I mention this is Sick.  We always need to
0288      * discard the upper 8 bits of the first 16-bit word.
0289      */
0290     v = readl(host->base + MMC_RES) & 0xffff;
0291     for (i = 0; i < 4; i++) {
0292         u32 w1 = readl(host->base + MMC_RES) & 0xffff;
0293         u32 w2 = readl(host->base + MMC_RES) & 0xffff;
0294         cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
0295         v = w2;
0296     }
0297 
0298     if (stat & STAT_TIME_OUT_RESPONSE) {
0299         cmd->error = -ETIMEDOUT;
0300     } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
0301         /*
0302          * workaround for erratum #42:
0303          * Intel PXA27x Family Processor Specification Update Rev 001
0304          * A bogus CRC error can appear if the msb of a 136 bit
0305          * response is a one.
0306          */
0307         if (cpu_is_pxa27x() &&
0308             (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000))
0309             pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode);
0310         else
0311             cmd->error = -EILSEQ;
0312     }
0313 
0314     pxamci_disable_irq(host, END_CMD_RES);
0315     if (host->data && !cmd->error) {
0316         pxamci_enable_irq(host, DATA_TRAN_DONE);
0317         /*
0318          * workaround for erratum #91, if doing write
0319          * enable DMA late
0320          */
0321         if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE)
0322             dma_async_issue_pending(host->dma_chan_tx);
0323     } else {
0324         pxamci_finish_request(host, host->mrq);
0325     }
0326 
0327     return 1;
0328 }
0329 
0330 static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
0331 {
0332     struct mmc_data *data = host->data;
0333     struct dma_chan *chan;
0334 
0335     if (!data)
0336         return 0;
0337 
0338     if (data->flags & MMC_DATA_READ)
0339         chan = host->dma_chan_rx;
0340     else
0341         chan = host->dma_chan_tx;
0342     dma_unmap_sg(chan->device->dev,
0343              data->sg, data->sg_len, host->dma_dir);
0344 
0345     if (stat & STAT_READ_TIME_OUT)
0346         data->error = -ETIMEDOUT;
0347     else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
0348         data->error = -EILSEQ;
0349 
0350     /*
0351      * There appears to be a hardware design bug here.  There seems to
0352      * be no way to find out how much data was transferred to the card.
0353      * This means that if there was an error on any block, we mark all
0354      * data blocks as being in error.
0355      */
0356     if (!data->error)
0357         data->bytes_xfered = data->blocks * data->blksz;
0358     else
0359         data->bytes_xfered = 0;
0360 
0361     pxamci_disable_irq(host, DATA_TRAN_DONE);
0362 
0363     host->data = NULL;
0364     if (host->mrq->stop) {
0365         pxamci_stop_clock(host);
0366         pxamci_start_cmd(host, host->mrq->stop, host->cmdat);
0367     } else {
0368         pxamci_finish_request(host, host->mrq);
0369     }
0370 
0371     return 1;
0372 }
0373 
0374 static irqreturn_t pxamci_irq(int irq, void *devid)
0375 {
0376     struct pxamci_host *host = devid;
0377     unsigned int ireg;
0378     int handled = 0;
0379 
0380     ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK);
0381 
0382     if (ireg) {
0383         unsigned stat = readl(host->base + MMC_STAT);
0384 
0385         pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);
0386 
0387         if (ireg & END_CMD_RES)
0388             handled |= pxamci_cmd_done(host, stat);
0389         if (ireg & DATA_TRAN_DONE)
0390             handled |= pxamci_data_done(host, stat);
0391         if (ireg & SDIO_INT) {
0392             mmc_signal_sdio_irq(host->mmc);
0393             handled = 1;
0394         }
0395     }
0396 
0397     return IRQ_RETVAL(handled);
0398 }
0399 
0400 static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
0401 {
0402     struct pxamci_host *host = mmc_priv(mmc);
0403     unsigned int cmdat;
0404 
0405     WARN_ON(host->mrq != NULL);
0406 
0407     host->mrq = mrq;
0408 
0409     pxamci_stop_clock(host);
0410 
0411     cmdat = host->cmdat;
0412     host->cmdat &= ~CMDAT_INIT;
0413 
0414     if (mrq->data) {
0415         pxamci_setup_data(host, mrq->data);
0416 
0417         cmdat &= ~CMDAT_BUSY;
0418         cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
0419         if (mrq->data->flags & MMC_DATA_WRITE)
0420             cmdat |= CMDAT_WRITE;
0421     }
0422 
0423     pxamci_start_cmd(host, mrq->cmd, cmdat);
0424 }
0425 
0426 static int pxamci_get_ro(struct mmc_host *mmc)
0427 {
0428     struct pxamci_host *host = mmc_priv(mmc);
0429 
0430     if (host->use_ro_gpio)
0431         return mmc_gpio_get_ro(mmc);
0432     if (host->pdata && host->pdata->get_ro)
0433         return !!host->pdata->get_ro(mmc_dev(mmc));
0434     /*
0435      * Board doesn't support read only detection; let the mmc core
0436      * decide what to do.
0437      */
0438     return -ENOSYS;
0439 }
0440 
0441 static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
0442 {
0443     struct pxamci_host *host = mmc_priv(mmc);
0444 
0445     if (ios->clock) {
0446         unsigned long rate = host->clkrate;
0447         unsigned int clk = rate / ios->clock;
0448 
0449         if (host->clkrt == CLKRT_OFF)
0450             clk_prepare_enable(host->clk);
0451 
0452         if (ios->clock == 26000000) {
0453             /* to support 26MHz */
0454             host->clkrt = 7;
0455         } else {
0456             /* to handle (19.5MHz, 26MHz) */
0457             if (!clk)
0458                 clk = 1;
0459 
0460             /*
0461              * clk might result in a lower divisor than we
0462              * desire.  check for that condition and adjust
0463              * as appropriate.
0464              */
0465             if (rate / clk > ios->clock)
0466                 clk <<= 1;
0467             host->clkrt = fls(clk) - 1;
0468         }
0469 
0470         /*
0471          * we write clkrt on the next command
0472          */
0473     } else {
0474         pxamci_stop_clock(host);
0475         if (host->clkrt != CLKRT_OFF) {
0476             host->clkrt = CLKRT_OFF;
0477             clk_disable_unprepare(host->clk);
0478         }
0479     }
0480 
0481     if (host->power_mode != ios->power_mode) {
0482         int ret;
0483 
0484         host->power_mode = ios->power_mode;
0485 
0486         ret = pxamci_set_power(host, ios->power_mode, ios->vdd);
0487         if (ret) {
0488             dev_err(mmc_dev(mmc), "unable to set power\n");
0489             /*
0490              * The .set_ios() function in the mmc_host_ops
0491              * struct return void, and failing to set the
0492              * power should be rare so we print an error and
0493              * return here.
0494              */
0495             return;
0496         }
0497 
0498         if (ios->power_mode == MMC_POWER_ON)
0499             host->cmdat |= CMDAT_INIT;
0500     }
0501 
0502     if (ios->bus_width == MMC_BUS_WIDTH_4)
0503         host->cmdat |= CMDAT_SD_4DAT;
0504     else
0505         host->cmdat &= ~CMDAT_SD_4DAT;
0506 
0507     dev_dbg(mmc_dev(mmc), "PXAMCI: clkrt = %x cmdat = %x\n",
0508         host->clkrt, host->cmdat);
0509 }
0510 
0511 static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable)
0512 {
0513     struct pxamci_host *pxa_host = mmc_priv(host);
0514 
0515     if (enable)
0516         pxamci_enable_irq(pxa_host, SDIO_INT);
0517     else
0518         pxamci_disable_irq(pxa_host, SDIO_INT);
0519 }
0520 
0521 static const struct mmc_host_ops pxamci_ops = {
0522     .request        = pxamci_request,
0523     .get_cd         = mmc_gpio_get_cd,
0524     .get_ro         = pxamci_get_ro,
0525     .set_ios        = pxamci_set_ios,
0526     .enable_sdio_irq    = pxamci_enable_sdio_irq,
0527 };
0528 
0529 static void pxamci_dma_irq(void *param)
0530 {
0531     struct pxamci_host *host = param;
0532     struct dma_tx_state state;
0533     enum dma_status status;
0534     struct dma_chan *chan;
0535     unsigned long flags;
0536 
0537     spin_lock_irqsave(&host->lock, flags);
0538 
0539     if (!host->data)
0540         goto out_unlock;
0541 
0542     if (host->data->flags & MMC_DATA_READ)
0543         chan = host->dma_chan_rx;
0544     else
0545         chan = host->dma_chan_tx;
0546 
0547     status = dmaengine_tx_status(chan, host->dma_cookie, &state);
0548 
0549     if (likely(status == DMA_COMPLETE)) {
0550         writel(BUF_PART_FULL, host->base + MMC_PRTBUF);
0551     } else {
0552         pr_err("%s: DMA error on %s channel\n", mmc_hostname(host->mmc),
0553             host->data->flags & MMC_DATA_READ ? "rx" : "tx");
0554         host->data->error = -EIO;
0555         pxamci_data_done(host, 0);
0556     }
0557 
0558 out_unlock:
0559     spin_unlock_irqrestore(&host->lock, flags);
0560 }
0561 
0562 static irqreturn_t pxamci_detect_irq(int irq, void *devid)
0563 {
0564     struct pxamci_host *host = mmc_priv(devid);
0565 
0566     mmc_detect_change(devid, msecs_to_jiffies(host->detect_delay_ms));
0567     return IRQ_HANDLED;
0568 }
0569 
0570 #ifdef CONFIG_OF
0571 static const struct of_device_id pxa_mmc_dt_ids[] = {
0572         { .compatible = "marvell,pxa-mmc" },
0573         { }
0574 };
0575 
0576 MODULE_DEVICE_TABLE(of, pxa_mmc_dt_ids);
0577 
0578 static int pxamci_of_init(struct platform_device *pdev,
0579               struct mmc_host *mmc)
0580 {
0581     struct device_node *np = pdev->dev.of_node;
0582     struct pxamci_host *host = mmc_priv(mmc);
0583     u32 tmp;
0584     int ret;
0585 
0586     if (!np)
0587         return 0;
0588 
0589     /* pxa-mmc specific */
0590     if (of_property_read_u32(np, "pxa-mmc,detect-delay-ms", &tmp) == 0)
0591         host->detect_delay_ms = tmp;
0592 
0593     ret = mmc_of_parse(mmc);
0594     if (ret < 0)
0595         return ret;
0596 
0597     return 0;
0598 }
0599 #else
0600 static int pxamci_of_init(struct platform_device *pdev,
0601               struct mmc_host *mmc)
0602 {
0603         return 0;
0604 }
0605 #endif
0606 
0607 static int pxamci_probe(struct platform_device *pdev)
0608 {
0609     struct mmc_host *mmc;
0610     struct pxamci_host *host = NULL;
0611     struct device *dev = &pdev->dev;
0612     struct resource *r;
0613     int ret, irq;
0614 
0615     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0616     irq = platform_get_irq(pdev, 0);
0617     if (irq < 0)
0618         return irq;
0619 
0620     mmc = mmc_alloc_host(sizeof(struct pxamci_host), dev);
0621     if (!mmc) {
0622         ret = -ENOMEM;
0623         goto out;
0624     }
0625 
0626     mmc->ops = &pxamci_ops;
0627 
0628     /*
0629      * We can do SG-DMA, but we don't because we never know how much
0630      * data we successfully wrote to the card.
0631      */
0632     mmc->max_segs = NR_SG;
0633 
0634     /*
0635      * Our hardware DMA can handle a maximum of one page per SG entry.
0636      */
0637     mmc->max_seg_size = PAGE_SIZE;
0638 
0639     /*
0640      * Block length register is only 10 bits before PXA27x.
0641      */
0642     mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048;
0643 
0644     /*
0645      * Block count register is 16 bits.
0646      */
0647     mmc->max_blk_count = 65535;
0648 
0649     ret = pxamci_of_init(pdev, mmc);
0650     if (ret)
0651         goto out;
0652 
0653     host = mmc_priv(mmc);
0654     host->mmc = mmc;
0655     host->pdata = pdev->dev.platform_data;
0656     host->clkrt = CLKRT_OFF;
0657 
0658     host->clk = devm_clk_get(dev, NULL);
0659     if (IS_ERR(host->clk)) {
0660         ret = PTR_ERR(host->clk);
0661         host->clk = NULL;
0662         goto out;
0663     }
0664 
0665     host->clkrate = clk_get_rate(host->clk);
0666 
0667     /*
0668      * Calculate minimum clock rate, rounding up.
0669      */
0670     mmc->f_min = (host->clkrate + 63) / 64;
0671     mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate;
0672 
0673     ret = pxamci_init_ocr(host);
0674     if (ret < 0)
0675         goto out;
0676 
0677     mmc->caps = 0;
0678     host->cmdat = 0;
0679     if (!cpu_is_pxa25x()) {
0680         mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
0681         host->cmdat |= CMDAT_SDIO_INT_EN;
0682         if (mmc_has_26MHz())
0683             mmc->caps |= MMC_CAP_MMC_HIGHSPEED |
0684                      MMC_CAP_SD_HIGHSPEED;
0685     }
0686 
0687     spin_lock_init(&host->lock);
0688     host->res = r;
0689     host->imask = MMC_I_MASK_ALL;
0690 
0691     host->base = devm_ioremap_resource(dev, r);
0692     if (IS_ERR(host->base)) {
0693         ret = PTR_ERR(host->base);
0694         goto out;
0695     }
0696 
0697     /*
0698      * Ensure that the host controller is shut down, and setup
0699      * with our defaults.
0700      */
0701     pxamci_stop_clock(host);
0702     writel(0, host->base + MMC_SPI);
0703     writel(64, host->base + MMC_RESTO);
0704     writel(host->imask, host->base + MMC_I_MASK);
0705 
0706     ret = devm_request_irq(dev, irq, pxamci_irq, 0,
0707                    DRIVER_NAME, host);
0708     if (ret)
0709         goto out;
0710 
0711     platform_set_drvdata(pdev, mmc);
0712 
0713     host->dma_chan_rx = dma_request_chan(dev, "rx");
0714     if (IS_ERR(host->dma_chan_rx)) {
0715         dev_err(dev, "unable to request rx dma channel\n");
0716         ret = PTR_ERR(host->dma_chan_rx);
0717         host->dma_chan_rx = NULL;
0718         goto out;
0719     }
0720 
0721     host->dma_chan_tx = dma_request_chan(dev, "tx");
0722     if (IS_ERR(host->dma_chan_tx)) {
0723         dev_err(dev, "unable to request tx dma channel\n");
0724         ret = PTR_ERR(host->dma_chan_tx);
0725         host->dma_chan_tx = NULL;
0726         goto out;
0727     }
0728 
0729     if (host->pdata) {
0730         host->detect_delay_ms = host->pdata->detect_delay_ms;
0731 
0732         host->power = devm_gpiod_get_optional(dev, "power", GPIOD_OUT_LOW);
0733         if (IS_ERR(host->power)) {
0734             ret = PTR_ERR(host->power);
0735             dev_err(dev, "Failed requesting gpio_power\n");
0736             goto out;
0737         }
0738 
0739         /* FIXME: should we pass detection delay to debounce? */
0740         ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0);
0741         if (ret && ret != -ENOENT) {
0742             dev_err(dev, "Failed requesting gpio_cd\n");
0743             goto out;
0744         }
0745 
0746         if (!host->pdata->gpio_card_ro_invert)
0747             mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
0748 
0749         ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0);
0750         if (ret && ret != -ENOENT) {
0751             dev_err(dev, "Failed requesting gpio_ro\n");
0752             goto out;
0753         }
0754         if (!ret)
0755             host->use_ro_gpio = true;
0756 
0757         if (host->pdata->init)
0758             host->pdata->init(dev, pxamci_detect_irq, mmc);
0759 
0760         if (host->power && host->pdata->setpower)
0761             dev_warn(dev, "gpio_power and setpower() both defined\n");
0762         if (host->use_ro_gpio && host->pdata->get_ro)
0763             dev_warn(dev, "gpio_ro and get_ro() both defined\n");
0764     }
0765 
0766     mmc_add_host(mmc);
0767 
0768     return 0;
0769 
0770 out:
0771     if (host) {
0772         if (host->dma_chan_rx)
0773             dma_release_channel(host->dma_chan_rx);
0774         if (host->dma_chan_tx)
0775             dma_release_channel(host->dma_chan_tx);
0776     }
0777     if (mmc)
0778         mmc_free_host(mmc);
0779     return ret;
0780 }
0781 
0782 static int pxamci_remove(struct platform_device *pdev)
0783 {
0784     struct mmc_host *mmc = platform_get_drvdata(pdev);
0785 
0786     if (mmc) {
0787         struct pxamci_host *host = mmc_priv(mmc);
0788 
0789         mmc_remove_host(mmc);
0790 
0791         if (host->pdata && host->pdata->exit)
0792             host->pdata->exit(&pdev->dev, mmc);
0793 
0794         pxamci_stop_clock(host);
0795         writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
0796                END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
0797                host->base + MMC_I_MASK);
0798 
0799         dmaengine_terminate_all(host->dma_chan_rx);
0800         dmaengine_terminate_all(host->dma_chan_tx);
0801         dma_release_channel(host->dma_chan_rx);
0802         dma_release_channel(host->dma_chan_tx);
0803 
0804         mmc_free_host(mmc);
0805     }
0806 
0807     return 0;
0808 }
0809 
0810 static struct platform_driver pxamci_driver = {
0811     .probe      = pxamci_probe,
0812     .remove     = pxamci_remove,
0813     .driver     = {
0814         .name   = DRIVER_NAME,
0815         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0816         .of_match_table = of_match_ptr(pxa_mmc_dt_ids),
0817     },
0818 };
0819 
0820 module_platform_driver(pxamci_driver);
0821 
0822 MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
0823 MODULE_LICENSE("GPL");
0824 MODULE_ALIAS("platform:pxa2xx-mci");
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