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0001 /*
0002  * drivers/mmc/host/omap_hsmmc.c
0003  *
0004  * Driver for OMAP2430/3430 MMC controller.
0005  *
0006  * Copyright (C) 2007 Texas Instruments.
0007  *
0008  * Authors:
0009  *  Syed Mohammed Khasim    <x0khasim@ti.com>
0010  *  Madhusudhan     <madhu.cr@ti.com>
0011  *  Mohit Jalori        <mjalori@ti.com>
0012  *
0013  * This file is licensed under the terms of the GNU General Public License
0014  * version 2. This program is licensed "as is" without any warranty of any
0015  * kind, whether express or implied.
0016  */
0017 
0018 #include <linux/module.h>
0019 #include <linux/init.h>
0020 #include <linux/kernel.h>
0021 #include <linux/debugfs.h>
0022 #include <linux/dmaengine.h>
0023 #include <linux/seq_file.h>
0024 #include <linux/sizes.h>
0025 #include <linux/interrupt.h>
0026 #include <linux/delay.h>
0027 #include <linux/dma-mapping.h>
0028 #include <linux/platform_device.h>
0029 #include <linux/timer.h>
0030 #include <linux/clk.h>
0031 #include <linux/of.h>
0032 #include <linux/of_irq.h>
0033 #include <linux/of_device.h>
0034 #include <linux/mmc/host.h>
0035 #include <linux/mmc/core.h>
0036 #include <linux/mmc/mmc.h>
0037 #include <linux/mmc/slot-gpio.h>
0038 #include <linux/io.h>
0039 #include <linux/irq.h>
0040 #include <linux/regulator/consumer.h>
0041 #include <linux/pinctrl/consumer.h>
0042 #include <linux/pm_runtime.h>
0043 #include <linux/pm_wakeirq.h>
0044 #include <linux/platform_data/hsmmc-omap.h>
0045 
0046 /* OMAP HSMMC Host Controller Registers */
0047 #define OMAP_HSMMC_SYSSTATUS    0x0014
0048 #define OMAP_HSMMC_CON      0x002C
0049 #define OMAP_HSMMC_SDMASA   0x0100
0050 #define OMAP_HSMMC_BLK      0x0104
0051 #define OMAP_HSMMC_ARG      0x0108
0052 #define OMAP_HSMMC_CMD      0x010C
0053 #define OMAP_HSMMC_RSP10    0x0110
0054 #define OMAP_HSMMC_RSP32    0x0114
0055 #define OMAP_HSMMC_RSP54    0x0118
0056 #define OMAP_HSMMC_RSP76    0x011C
0057 #define OMAP_HSMMC_DATA     0x0120
0058 #define OMAP_HSMMC_PSTATE   0x0124
0059 #define OMAP_HSMMC_HCTL     0x0128
0060 #define OMAP_HSMMC_SYSCTL   0x012C
0061 #define OMAP_HSMMC_STAT     0x0130
0062 #define OMAP_HSMMC_IE       0x0134
0063 #define OMAP_HSMMC_ISE      0x0138
0064 #define OMAP_HSMMC_AC12     0x013C
0065 #define OMAP_HSMMC_CAPA     0x0140
0066 
0067 #define VS18            (1 << 26)
0068 #define VS30            (1 << 25)
0069 #define HSS         (1 << 21)
0070 #define SDVS18          (0x5 << 9)
0071 #define SDVS30          (0x6 << 9)
0072 #define SDVS33          (0x7 << 9)
0073 #define SDVS_MASK       0x00000E00
0074 #define SDVSCLR         0xFFFFF1FF
0075 #define SDVSDET         0x00000400
0076 #define AUTOIDLE        0x1
0077 #define SDBP            (1 << 8)
0078 #define DTO         0xe
0079 #define ICE         0x1
0080 #define ICS         0x2
0081 #define CEN         (1 << 2)
0082 #define CLKD_MAX        0x3FF       /* max clock divisor: 1023 */
0083 #define CLKD_MASK       0x0000FFC0
0084 #define CLKD_SHIFT      6
0085 #define DTO_MASK        0x000F0000
0086 #define DTO_SHIFT       16
0087 #define INIT_STREAM     (1 << 1)
0088 #define ACEN_ACMD23     (2 << 2)
0089 #define DP_SELECT       (1 << 21)
0090 #define DDIR            (1 << 4)
0091 #define DMAE            0x1
0092 #define MSBS            (1 << 5)
0093 #define BCE         (1 << 1)
0094 #define FOUR_BIT        (1 << 1)
0095 #define HSPE            (1 << 2)
0096 #define IWE         (1 << 24)
0097 #define DDR         (1 << 19)
0098 #define CLKEXTFREE      (1 << 16)
0099 #define CTPL            (1 << 11)
0100 #define DW8         (1 << 5)
0101 #define OD          0x1
0102 #define STAT_CLEAR      0xFFFFFFFF
0103 #define INIT_STREAM_CMD     0x00000000
0104 #define DUAL_VOLT_OCR_BIT   7
0105 #define SRC         (1 << 25)
0106 #define SRD         (1 << 26)
0107 #define SOFTRESET       (1 << 1)
0108 
0109 /* PSTATE */
0110 #define DLEV_DAT(x)     (1 << (20 + (x)))
0111 
0112 /* Interrupt masks for IE and ISE register */
0113 #define CC_EN           (1 << 0)
0114 #define TC_EN           (1 << 1)
0115 #define BWR_EN          (1 << 4)
0116 #define BRR_EN          (1 << 5)
0117 #define CIRQ_EN         (1 << 8)
0118 #define ERR_EN          (1 << 15)
0119 #define CTO_EN          (1 << 16)
0120 #define CCRC_EN         (1 << 17)
0121 #define CEB_EN          (1 << 18)
0122 #define CIE_EN          (1 << 19)
0123 #define DTO_EN          (1 << 20)
0124 #define DCRC_EN         (1 << 21)
0125 #define DEB_EN          (1 << 22)
0126 #define ACE_EN          (1 << 24)
0127 #define CERR_EN         (1 << 28)
0128 #define BADA_EN         (1 << 29)
0129 
0130 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
0131         DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
0132         BRR_EN | BWR_EN | TC_EN | CC_EN)
0133 
0134 #define CNI (1 << 7)
0135 #define ACIE    (1 << 4)
0136 #define ACEB    (1 << 3)
0137 #define ACCE    (1 << 2)
0138 #define ACTO    (1 << 1)
0139 #define ACNE    (1 << 0)
0140 
0141 #define MMC_AUTOSUSPEND_DELAY   100
0142 #define MMC_TIMEOUT_MS      20      /* 20 mSec */
0143 #define MMC_TIMEOUT_US      20000       /* 20000 micro Sec */
0144 #define OMAP_MMC_MIN_CLOCK  400000
0145 #define OMAP_MMC_MAX_CLOCK  52000000
0146 #define DRIVER_NAME     "omap_hsmmc"
0147 
0148 /*
0149  * One controller can have multiple slots, like on some omap boards using
0150  * omap.c controller driver. Luckily this is not currently done on any known
0151  * omap_hsmmc.c device.
0152  */
0153 #define mmc_pdata(host)     host->pdata
0154 
0155 /*
0156  * MMC Host controller read/write API's
0157  */
0158 #define OMAP_HSMMC_READ(base, reg)  \
0159     __raw_readl((base) + OMAP_HSMMC_##reg)
0160 
0161 #define OMAP_HSMMC_WRITE(base, reg, val) \
0162     __raw_writel((val), (base) + OMAP_HSMMC_##reg)
0163 
0164 struct omap_hsmmc_next {
0165     unsigned int    dma_len;
0166     s32     cookie;
0167 };
0168 
0169 struct omap_hsmmc_host {
0170     struct  device      *dev;
0171     struct  mmc_host    *mmc;
0172     struct  mmc_request *mrq;
0173     struct  mmc_command *cmd;
0174     struct  mmc_data    *data;
0175     struct  clk     *fclk;
0176     struct  clk     *dbclk;
0177     struct  regulator   *pbias;
0178     bool            pbias_enabled;
0179     void    __iomem     *base;
0180     bool            vqmmc_enabled;
0181     resource_size_t     mapbase;
0182     spinlock_t      irq_lock; /* Prevent races with irq handler */
0183     unsigned int        dma_len;
0184     unsigned int        dma_sg_idx;
0185     unsigned char       bus_mode;
0186     unsigned char       power_mode;
0187     int         suspended;
0188     u32         con;
0189     u32         hctl;
0190     u32         sysctl;
0191     u32         capa;
0192     int         irq;
0193     int         wake_irq;
0194     int         use_dma, dma_ch;
0195     struct dma_chan     *tx_chan;
0196     struct dma_chan     *rx_chan;
0197     int         response_busy;
0198     int         context_loss;
0199     int         reqs_blocked;
0200     int         req_in_progress;
0201     unsigned long       clk_rate;
0202     unsigned int        flags;
0203 #define AUTO_CMD23      (1 << 0)        /* Auto CMD23 support */
0204 #define HSMMC_SDIO_IRQ_ENABLED  (1 << 1)        /* SDIO irq enabled */
0205     struct omap_hsmmc_next  next_data;
0206     struct  omap_hsmmc_platform_data    *pdata;
0207 };
0208 
0209 struct omap_mmc_of_data {
0210     u32 reg_offset;
0211     u8 controller_flags;
0212 };
0213 
0214 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
0215 
0216 static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
0217 {
0218     int ret;
0219     struct omap_hsmmc_host *host = mmc_priv(mmc);
0220     struct mmc_ios *ios = &mmc->ios;
0221 
0222     if (!IS_ERR(mmc->supply.vmmc)) {
0223         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
0224         if (ret)
0225             return ret;
0226     }
0227 
0228     /* Enable interface voltage rail, if needed */
0229     if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
0230         ret = regulator_enable(mmc->supply.vqmmc);
0231         if (ret) {
0232             dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
0233             goto err_vqmmc;
0234         }
0235         host->vqmmc_enabled = true;
0236     }
0237 
0238     return 0;
0239 
0240 err_vqmmc:
0241     if (!IS_ERR(mmc->supply.vmmc))
0242         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
0243 
0244     return ret;
0245 }
0246 
0247 static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
0248 {
0249     int ret;
0250     int status;
0251     struct omap_hsmmc_host *host = mmc_priv(mmc);
0252 
0253     if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
0254         ret = regulator_disable(mmc->supply.vqmmc);
0255         if (ret) {
0256             dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
0257             return ret;
0258         }
0259         host->vqmmc_enabled = false;
0260     }
0261 
0262     if (!IS_ERR(mmc->supply.vmmc)) {
0263         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
0264         if (ret)
0265             goto err_set_ocr;
0266     }
0267 
0268     return 0;
0269 
0270 err_set_ocr:
0271     if (!IS_ERR(mmc->supply.vqmmc)) {
0272         status = regulator_enable(mmc->supply.vqmmc);
0273         if (status)
0274             dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
0275     }
0276 
0277     return ret;
0278 }
0279 
0280 static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on)
0281 {
0282     int ret;
0283 
0284     if (IS_ERR(host->pbias))
0285         return 0;
0286 
0287     if (power_on) {
0288         if (!host->pbias_enabled) {
0289             ret = regulator_enable(host->pbias);
0290             if (ret) {
0291                 dev_err(host->dev, "pbias reg enable fail\n");
0292                 return ret;
0293             }
0294             host->pbias_enabled = true;
0295         }
0296     } else {
0297         if (host->pbias_enabled) {
0298             ret = regulator_disable(host->pbias);
0299             if (ret) {
0300                 dev_err(host->dev, "pbias reg disable fail\n");
0301                 return ret;
0302             }
0303             host->pbias_enabled = false;
0304         }
0305     }
0306 
0307     return 0;
0308 }
0309 
0310 static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on)
0311 {
0312     struct mmc_host *mmc = host->mmc;
0313     int ret = 0;
0314 
0315     /*
0316      * If we don't see a Vcc regulator, assume it's a fixed
0317      * voltage always-on regulator.
0318      */
0319     if (IS_ERR(mmc->supply.vmmc))
0320         return 0;
0321 
0322     ret = omap_hsmmc_set_pbias(host, false);
0323     if (ret)
0324         return ret;
0325 
0326     /*
0327      * Assume Vcc regulator is used only to power the card ... OMAP
0328      * VDDS is used to power the pins, optionally with a transceiver to
0329      * support cards using voltages other than VDDS (1.8V nominal).  When a
0330      * transceiver is used, DAT3..7 are muxed as transceiver control pins.
0331      *
0332      * In some cases this regulator won't support enable/disable;
0333      * e.g. it's a fixed rail for a WLAN chip.
0334      *
0335      * In other cases vcc_aux switches interface power.  Example, for
0336      * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
0337      * chips/cards need an interface voltage rail too.
0338      */
0339     if (power_on) {
0340         ret = omap_hsmmc_enable_supply(mmc);
0341         if (ret)
0342             return ret;
0343 
0344         ret = omap_hsmmc_set_pbias(host, true);
0345         if (ret)
0346             goto err_set_voltage;
0347     } else {
0348         ret = omap_hsmmc_disable_supply(mmc);
0349         if (ret)
0350             return ret;
0351     }
0352 
0353     return 0;
0354 
0355 err_set_voltage:
0356     omap_hsmmc_disable_supply(mmc);
0357 
0358     return ret;
0359 }
0360 
0361 static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
0362 {
0363     int ret;
0364 
0365     if (IS_ERR(reg))
0366         return 0;
0367 
0368     if (regulator_is_enabled(reg)) {
0369         ret = regulator_enable(reg);
0370         if (ret)
0371             return ret;
0372 
0373         ret = regulator_disable(reg);
0374         if (ret)
0375             return ret;
0376     }
0377 
0378     return 0;
0379 }
0380 
0381 static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
0382 {
0383     struct mmc_host *mmc = host->mmc;
0384     int ret;
0385 
0386     /*
0387      * disable regulators enabled during boot and get the usecount
0388      * right so that regulators can be enabled/disabled by checking
0389      * the return value of regulator_is_enabled
0390      */
0391     ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
0392     if (ret) {
0393         dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
0394         return ret;
0395     }
0396 
0397     ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
0398     if (ret) {
0399         dev_err(host->dev,
0400             "fail to disable boot enabled vmmc_aux reg\n");
0401         return ret;
0402     }
0403 
0404     ret = omap_hsmmc_disable_boot_regulator(host->pbias);
0405     if (ret) {
0406         dev_err(host->dev,
0407             "failed to disable boot enabled pbias reg\n");
0408         return ret;
0409     }
0410 
0411     return 0;
0412 }
0413 
0414 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
0415 {
0416     int ret;
0417     struct mmc_host *mmc = host->mmc;
0418 
0419 
0420     ret = mmc_regulator_get_supply(mmc);
0421     if (ret)
0422         return ret;
0423 
0424     /* Allow an aux regulator */
0425     if (IS_ERR(mmc->supply.vqmmc)) {
0426         mmc->supply.vqmmc = devm_regulator_get_optional(host->dev,
0427                                 "vmmc_aux");
0428         if (IS_ERR(mmc->supply.vqmmc)) {
0429             ret = PTR_ERR(mmc->supply.vqmmc);
0430             if ((ret != -ENODEV) && host->dev->of_node)
0431                 return ret;
0432             dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
0433                 PTR_ERR(mmc->supply.vqmmc));
0434         }
0435     }
0436 
0437     host->pbias = devm_regulator_get_optional(host->dev, "pbias");
0438     if (IS_ERR(host->pbias)) {
0439         ret = PTR_ERR(host->pbias);
0440         if ((ret != -ENODEV) && host->dev->of_node) {
0441             dev_err(host->dev,
0442             "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n");
0443             return ret;
0444         }
0445         dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
0446             PTR_ERR(host->pbias));
0447     }
0448 
0449     /* For eMMC do not power off when not in sleep state */
0450     if (mmc_pdata(host)->no_regulator_off_init)
0451         return 0;
0452 
0453     ret = omap_hsmmc_disable_boot_regulators(host);
0454     if (ret)
0455         return ret;
0456 
0457     return 0;
0458 }
0459 
0460 /*
0461  * Start clock to the card
0462  */
0463 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
0464 {
0465     OMAP_HSMMC_WRITE(host->base, SYSCTL,
0466         OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
0467 }
0468 
0469 /*
0470  * Stop clock to the card
0471  */
0472 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
0473 {
0474     OMAP_HSMMC_WRITE(host->base, SYSCTL,
0475         OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
0476     if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
0477         dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
0478 }
0479 
0480 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
0481                   struct mmc_command *cmd)
0482 {
0483     u32 irq_mask = INT_EN_MASK;
0484     unsigned long flags;
0485 
0486     if (host->use_dma)
0487         irq_mask &= ~(BRR_EN | BWR_EN);
0488 
0489     /* Disable timeout for erases */
0490     if (cmd->opcode == MMC_ERASE)
0491         irq_mask &= ~DTO_EN;
0492 
0493     spin_lock_irqsave(&host->irq_lock, flags);
0494     OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
0495     OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
0496 
0497     /* latch pending CIRQ, but don't signal MMC core */
0498     if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
0499         irq_mask |= CIRQ_EN;
0500     OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
0501     spin_unlock_irqrestore(&host->irq_lock, flags);
0502 }
0503 
0504 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
0505 {
0506     u32 irq_mask = 0;
0507     unsigned long flags;
0508 
0509     spin_lock_irqsave(&host->irq_lock, flags);
0510     /* no transfer running but need to keep cirq if enabled */
0511     if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
0512         irq_mask |= CIRQ_EN;
0513     OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
0514     OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
0515     OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
0516     spin_unlock_irqrestore(&host->irq_lock, flags);
0517 }
0518 
0519 /* Calculate divisor for the given clock frequency */
0520 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
0521 {
0522     u16 dsor = 0;
0523 
0524     if (ios->clock) {
0525         dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
0526         if (dsor > CLKD_MAX)
0527             dsor = CLKD_MAX;
0528     }
0529 
0530     return dsor;
0531 }
0532 
0533 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
0534 {
0535     struct mmc_ios *ios = &host->mmc->ios;
0536     unsigned long regval;
0537     unsigned long timeout;
0538     unsigned long clkdiv;
0539 
0540     dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
0541 
0542     omap_hsmmc_stop_clock(host);
0543 
0544     regval = OMAP_HSMMC_READ(host->base, SYSCTL);
0545     regval = regval & ~(CLKD_MASK | DTO_MASK);
0546     clkdiv = calc_divisor(host, ios);
0547     regval = regval | (clkdiv << 6) | (DTO << 16);
0548     OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
0549     OMAP_HSMMC_WRITE(host->base, SYSCTL,
0550         OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
0551 
0552     /* Wait till the ICS bit is set */
0553     timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
0554     while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
0555         && time_before(jiffies, timeout))
0556         cpu_relax();
0557 
0558     /*
0559      * Enable High-Speed Support
0560      * Pre-Requisites
0561      *  - Controller should support High-Speed-Enable Bit
0562      *  - Controller should not be using DDR Mode
0563      *  - Controller should advertise that it supports High Speed
0564      *    in capabilities register
0565      *  - MMC/SD clock coming out of controller > 25MHz
0566      */
0567     if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
0568         (ios->timing != MMC_TIMING_MMC_DDR52) &&
0569         (ios->timing != MMC_TIMING_UHS_DDR50) &&
0570         ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
0571         regval = OMAP_HSMMC_READ(host->base, HCTL);
0572         if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
0573             regval |= HSPE;
0574         else
0575             regval &= ~HSPE;
0576 
0577         OMAP_HSMMC_WRITE(host->base, HCTL, regval);
0578     }
0579 
0580     omap_hsmmc_start_clock(host);
0581 }
0582 
0583 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
0584 {
0585     struct mmc_ios *ios = &host->mmc->ios;
0586     u32 con;
0587 
0588     con = OMAP_HSMMC_READ(host->base, CON);
0589     if (ios->timing == MMC_TIMING_MMC_DDR52 ||
0590         ios->timing == MMC_TIMING_UHS_DDR50)
0591         con |= DDR; /* configure in DDR mode */
0592     else
0593         con &= ~DDR;
0594     switch (ios->bus_width) {
0595     case MMC_BUS_WIDTH_8:
0596         OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
0597         break;
0598     case MMC_BUS_WIDTH_4:
0599         OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
0600         OMAP_HSMMC_WRITE(host->base, HCTL,
0601             OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
0602         break;
0603     case MMC_BUS_WIDTH_1:
0604         OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
0605         OMAP_HSMMC_WRITE(host->base, HCTL,
0606             OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
0607         break;
0608     }
0609 }
0610 
0611 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
0612 {
0613     struct mmc_ios *ios = &host->mmc->ios;
0614     u32 con;
0615 
0616     con = OMAP_HSMMC_READ(host->base, CON);
0617     if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
0618         OMAP_HSMMC_WRITE(host->base, CON, con | OD);
0619     else
0620         OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
0621 }
0622 
0623 #ifdef CONFIG_PM
0624 
0625 /*
0626  * Restore the MMC host context, if it was lost as result of a
0627  * power state change.
0628  */
0629 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
0630 {
0631     struct mmc_ios *ios = &host->mmc->ios;
0632     u32 hctl, capa;
0633     unsigned long timeout;
0634 
0635     if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
0636         host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
0637         host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
0638         host->capa == OMAP_HSMMC_READ(host->base, CAPA))
0639         return 0;
0640 
0641     host->context_loss++;
0642 
0643     if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
0644         if (host->power_mode != MMC_POWER_OFF &&
0645             (1 << ios->vdd) <= MMC_VDD_23_24)
0646             hctl = SDVS18;
0647         else
0648             hctl = SDVS30;
0649         capa = VS30 | VS18;
0650     } else {
0651         hctl = SDVS18;
0652         capa = VS18;
0653     }
0654 
0655     if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
0656         hctl |= IWE;
0657 
0658     OMAP_HSMMC_WRITE(host->base, HCTL,
0659             OMAP_HSMMC_READ(host->base, HCTL) | hctl);
0660 
0661     OMAP_HSMMC_WRITE(host->base, CAPA,
0662             OMAP_HSMMC_READ(host->base, CAPA) | capa);
0663 
0664     OMAP_HSMMC_WRITE(host->base, HCTL,
0665             OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
0666 
0667     timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
0668     while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
0669         && time_before(jiffies, timeout))
0670         ;
0671 
0672     OMAP_HSMMC_WRITE(host->base, ISE, 0);
0673     OMAP_HSMMC_WRITE(host->base, IE, 0);
0674     OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
0675 
0676     /* Do not initialize card-specific things if the power is off */
0677     if (host->power_mode == MMC_POWER_OFF)
0678         goto out;
0679 
0680     omap_hsmmc_set_bus_width(host);
0681 
0682     omap_hsmmc_set_clock(host);
0683 
0684     omap_hsmmc_set_bus_mode(host);
0685 
0686 out:
0687     dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
0688         host->context_loss);
0689     return 0;
0690 }
0691 
0692 /*
0693  * Save the MMC host context (store the number of power state changes so far).
0694  */
0695 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
0696 {
0697     host->con =  OMAP_HSMMC_READ(host->base, CON);
0698     host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
0699     host->sysctl =  OMAP_HSMMC_READ(host->base, SYSCTL);
0700     host->capa = OMAP_HSMMC_READ(host->base, CAPA);
0701 }
0702 
0703 #else
0704 
0705 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
0706 {
0707 }
0708 
0709 #endif
0710 
0711 /*
0712  * Send init stream sequence to card
0713  * before sending IDLE command
0714  */
0715 static void send_init_stream(struct omap_hsmmc_host *host)
0716 {
0717     int reg = 0;
0718     unsigned long timeout;
0719 
0720     disable_irq(host->irq);
0721 
0722     OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
0723     OMAP_HSMMC_WRITE(host->base, CON,
0724         OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
0725     OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
0726 
0727     timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
0728     while ((reg != CC_EN) && time_before(jiffies, timeout))
0729         reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
0730 
0731     OMAP_HSMMC_WRITE(host->base, CON,
0732         OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
0733 
0734     OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
0735     OMAP_HSMMC_READ(host->base, STAT);
0736 
0737     enable_irq(host->irq);
0738 }
0739 
0740 static ssize_t
0741 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
0742             char *buf)
0743 {
0744     struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
0745     struct omap_hsmmc_host *host = mmc_priv(mmc);
0746 
0747     return sprintf(buf, "%s\n", mmc_pdata(host)->name);
0748 }
0749 
0750 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
0751 
0752 /*
0753  * Configure the response type and send the cmd.
0754  */
0755 static void
0756 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
0757     struct mmc_data *data)
0758 {
0759     int cmdreg = 0, resptype = 0, cmdtype = 0;
0760 
0761     dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
0762         mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
0763     host->cmd = cmd;
0764 
0765     omap_hsmmc_enable_irq(host, cmd);
0766 
0767     host->response_busy = 0;
0768     if (cmd->flags & MMC_RSP_PRESENT) {
0769         if (cmd->flags & MMC_RSP_136)
0770             resptype = 1;
0771         else if (cmd->flags & MMC_RSP_BUSY) {
0772             resptype = 3;
0773             host->response_busy = 1;
0774         } else
0775             resptype = 2;
0776     }
0777 
0778     /*
0779      * Unlike OMAP1 controller, the cmdtype does not seem to be based on
0780      * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
0781      * a val of 0x3, rest 0x0.
0782      */
0783     if (cmd == host->mrq->stop)
0784         cmdtype = 0x3;
0785 
0786     cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
0787 
0788     if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
0789         host->mrq->sbc) {
0790         cmdreg |= ACEN_ACMD23;
0791         OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
0792     }
0793     if (data) {
0794         cmdreg |= DP_SELECT | MSBS | BCE;
0795         if (data->flags & MMC_DATA_READ)
0796             cmdreg |= DDIR;
0797         else
0798             cmdreg &= ~(DDIR);
0799     }
0800 
0801     if (host->use_dma)
0802         cmdreg |= DMAE;
0803 
0804     host->req_in_progress = 1;
0805 
0806     OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
0807     OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
0808 }
0809 
0810 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
0811     struct mmc_data *data)
0812 {
0813     return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
0814 }
0815 
0816 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
0817 {
0818     int dma_ch;
0819     unsigned long flags;
0820 
0821     spin_lock_irqsave(&host->irq_lock, flags);
0822     host->req_in_progress = 0;
0823     dma_ch = host->dma_ch;
0824     spin_unlock_irqrestore(&host->irq_lock, flags);
0825 
0826     omap_hsmmc_disable_irq(host);
0827     /* Do not complete the request if DMA is still in progress */
0828     if (mrq->data && host->use_dma && dma_ch != -1)
0829         return;
0830     host->mrq = NULL;
0831     mmc_request_done(host->mmc, mrq);
0832 }
0833 
0834 /*
0835  * Notify the transfer complete to MMC core
0836  */
0837 static void
0838 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
0839 {
0840     if (!data) {
0841         struct mmc_request *mrq = host->mrq;
0842 
0843         /* TC before CC from CMD6 - don't know why, but it happens */
0844         if (host->cmd && host->cmd->opcode == 6 &&
0845             host->response_busy) {
0846             host->response_busy = 0;
0847             return;
0848         }
0849 
0850         omap_hsmmc_request_done(host, mrq);
0851         return;
0852     }
0853 
0854     host->data = NULL;
0855 
0856     if (!data->error)
0857         data->bytes_xfered += data->blocks * (data->blksz);
0858     else
0859         data->bytes_xfered = 0;
0860 
0861     if (data->stop && (data->error || !host->mrq->sbc))
0862         omap_hsmmc_start_command(host, data->stop, NULL);
0863     else
0864         omap_hsmmc_request_done(host, data->mrq);
0865 }
0866 
0867 /*
0868  * Notify the core about command completion
0869  */
0870 static void
0871 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
0872 {
0873     if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
0874         !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
0875         host->cmd = NULL;
0876         omap_hsmmc_start_dma_transfer(host);
0877         omap_hsmmc_start_command(host, host->mrq->cmd,
0878                         host->mrq->data);
0879         return;
0880     }
0881 
0882     host->cmd = NULL;
0883 
0884     if (cmd->flags & MMC_RSP_PRESENT) {
0885         if (cmd->flags & MMC_RSP_136) {
0886             /* response type 2 */
0887             cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
0888             cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
0889             cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
0890             cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
0891         } else {
0892             /* response types 1, 1b, 3, 4, 5, 6 */
0893             cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
0894         }
0895     }
0896     if ((host->data == NULL && !host->response_busy) || cmd->error)
0897         omap_hsmmc_request_done(host, host->mrq);
0898 }
0899 
0900 /*
0901  * DMA clean up for command errors
0902  */
0903 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
0904 {
0905     int dma_ch;
0906     unsigned long flags;
0907 
0908     host->data->error = errno;
0909 
0910     spin_lock_irqsave(&host->irq_lock, flags);
0911     dma_ch = host->dma_ch;
0912     host->dma_ch = -1;
0913     spin_unlock_irqrestore(&host->irq_lock, flags);
0914 
0915     if (host->use_dma && dma_ch != -1) {
0916         struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
0917 
0918         dmaengine_terminate_all(chan);
0919         dma_unmap_sg(chan->device->dev,
0920             host->data->sg, host->data->sg_len,
0921             mmc_get_dma_dir(host->data));
0922 
0923         host->data->host_cookie = 0;
0924     }
0925     host->data = NULL;
0926 }
0927 
0928 /*
0929  * Readable error output
0930  */
0931 #ifdef CONFIG_MMC_DEBUG
0932 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
0933 {
0934     /* --- means reserved bit without definition at documentation */
0935     static const char *omap_hsmmc_status_bits[] = {
0936         "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
0937         "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
0938         "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
0939         "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
0940     };
0941     char res[256];
0942     char *buf = res;
0943     int len, i;
0944 
0945     len = sprintf(buf, "MMC IRQ 0x%x :", status);
0946     buf += len;
0947 
0948     for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
0949         if (status & (1 << i)) {
0950             len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
0951             buf += len;
0952         }
0953 
0954     dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
0955 }
0956 #else
0957 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
0958                          u32 status)
0959 {
0960 }
0961 #endif  /* CONFIG_MMC_DEBUG */
0962 
0963 /*
0964  * MMC controller internal state machines reset
0965  *
0966  * Used to reset command or data internal state machines, using respectively
0967  *  SRC or SRD bit of SYSCTL register
0968  * Can be called from interrupt context
0969  */
0970 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
0971                            unsigned long bit)
0972 {
0973     unsigned long i = 0;
0974     unsigned long limit = MMC_TIMEOUT_US;
0975 
0976     OMAP_HSMMC_WRITE(host->base, SYSCTL,
0977              OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
0978 
0979     /*
0980      * OMAP4 ES2 and greater has an updated reset logic.
0981      * Monitor a 0->1 transition first
0982      */
0983     if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
0984         while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
0985                     && (i++ < limit))
0986             udelay(1);
0987     }
0988     i = 0;
0989 
0990     while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
0991         (i++ < limit))
0992         udelay(1);
0993 
0994     if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
0995         dev_err(mmc_dev(host->mmc),
0996             "Timeout waiting on controller reset in %s\n",
0997             __func__);
0998 }
0999 
1000 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1001                     int err, int end_cmd)
1002 {
1003     if (end_cmd) {
1004         omap_hsmmc_reset_controller_fsm(host, SRC);
1005         if (host->cmd)
1006             host->cmd->error = err;
1007     }
1008 
1009     if (host->data) {
1010         omap_hsmmc_reset_controller_fsm(host, SRD);
1011         omap_hsmmc_dma_cleanup(host, err);
1012     } else if (host->mrq && host->mrq->cmd)
1013         host->mrq->cmd->error = err;
1014 }
1015 
1016 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1017 {
1018     struct mmc_data *data;
1019     int end_cmd = 0, end_trans = 0;
1020     int error = 0;
1021 
1022     data = host->data;
1023     dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1024 
1025     if (status & ERR_EN) {
1026         omap_hsmmc_dbg_report_irq(host, status);
1027 
1028         if (status & (CTO_EN | CCRC_EN | CEB_EN))
1029             end_cmd = 1;
1030         if (host->data || host->response_busy) {
1031             end_trans = !end_cmd;
1032             host->response_busy = 0;
1033         }
1034         if (status & (CTO_EN | DTO_EN))
1035             hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1036         else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
1037                    BADA_EN))
1038             hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1039 
1040         if (status & ACE_EN) {
1041             u32 ac12;
1042             ac12 = OMAP_HSMMC_READ(host->base, AC12);
1043             if (!(ac12 & ACNE) && host->mrq->sbc) {
1044                 end_cmd = 1;
1045                 if (ac12 & ACTO)
1046                     error =  -ETIMEDOUT;
1047                 else if (ac12 & (ACCE | ACEB | ACIE))
1048                     error = -EILSEQ;
1049                 host->mrq->sbc->error = error;
1050                 hsmmc_command_incomplete(host, error, end_cmd);
1051             }
1052             dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1053         }
1054     }
1055 
1056     OMAP_HSMMC_WRITE(host->base, STAT, status);
1057     if (end_cmd || ((status & CC_EN) && host->cmd))
1058         omap_hsmmc_cmd_done(host, host->cmd);
1059     if ((end_trans || (status & TC_EN)) && host->mrq)
1060         omap_hsmmc_xfer_done(host, data);
1061 }
1062 
1063 /*
1064  * MMC controller IRQ handler
1065  */
1066 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1067 {
1068     struct omap_hsmmc_host *host = dev_id;
1069     int status;
1070 
1071     status = OMAP_HSMMC_READ(host->base, STAT);
1072     while (status & (INT_EN_MASK | CIRQ_EN)) {
1073         if (host->req_in_progress)
1074             omap_hsmmc_do_irq(host, status);
1075 
1076         if (status & CIRQ_EN)
1077             mmc_signal_sdio_irq(host->mmc);
1078 
1079         /* Flush posted write */
1080         status = OMAP_HSMMC_READ(host->base, STAT);
1081     }
1082 
1083     return IRQ_HANDLED;
1084 }
1085 
1086 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1087 {
1088     unsigned long i;
1089 
1090     OMAP_HSMMC_WRITE(host->base, HCTL,
1091              OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1092     for (i = 0; i < loops_per_jiffy; i++) {
1093         if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1094             break;
1095         cpu_relax();
1096     }
1097 }
1098 
1099 /*
1100  * Switch MMC interface voltage ... only relevant for MMC1.
1101  *
1102  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1103  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1104  * Some chips, like eMMC ones, use internal transceivers.
1105  */
1106 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1107 {
1108     u32 reg_val = 0;
1109     int ret;
1110 
1111     /* Disable the clocks */
1112     clk_disable_unprepare(host->dbclk);
1113 
1114     /* Turn the power off */
1115     ret = omap_hsmmc_set_power(host, 0);
1116 
1117     /* Turn the power ON with given VDD 1.8 or 3.0v */
1118     if (!ret)
1119         ret = omap_hsmmc_set_power(host, 1);
1120     clk_prepare_enable(host->dbclk);
1121 
1122     if (ret != 0)
1123         goto err;
1124 
1125     OMAP_HSMMC_WRITE(host->base, HCTL,
1126         OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1127     reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1128 
1129     /*
1130      * If a MMC dual voltage card is detected, the set_ios fn calls
1131      * this fn with VDD bit set for 1.8V. Upon card removal from the
1132      * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1133      *
1134      * Cope with a bit of slop in the range ... per data sheets:
1135      *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1136      *    but recommended values are 1.71V to 1.89V
1137      *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1138      *    but recommended values are 2.7V to 3.3V
1139      *
1140      * Board setup code shouldn't permit anything very out-of-range.
1141      * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1142      * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1143      */
1144     if ((1 << vdd) <= MMC_VDD_23_24)
1145         reg_val |= SDVS18;
1146     else
1147         reg_val |= SDVS30;
1148 
1149     OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1150     set_sd_bus_power(host);
1151 
1152     return 0;
1153 err:
1154     dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1155     return ret;
1156 }
1157 
1158 static void omap_hsmmc_dma_callback(void *param)
1159 {
1160     struct omap_hsmmc_host *host = param;
1161     struct dma_chan *chan;
1162     struct mmc_data *data;
1163     int req_in_progress;
1164 
1165     spin_lock_irq(&host->irq_lock);
1166     if (host->dma_ch < 0) {
1167         spin_unlock_irq(&host->irq_lock);
1168         return;
1169     }
1170 
1171     data = host->mrq->data;
1172     chan = omap_hsmmc_get_dma_chan(host, data);
1173     if (!data->host_cookie)
1174         dma_unmap_sg(chan->device->dev,
1175                  data->sg, data->sg_len,
1176                  mmc_get_dma_dir(data));
1177 
1178     req_in_progress = host->req_in_progress;
1179     host->dma_ch = -1;
1180     spin_unlock_irq(&host->irq_lock);
1181 
1182     /* If DMA has finished after TC, complete the request */
1183     if (!req_in_progress) {
1184         struct mmc_request *mrq = host->mrq;
1185 
1186         host->mrq = NULL;
1187         mmc_request_done(host->mmc, mrq);
1188     }
1189 }
1190 
1191 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1192                        struct mmc_data *data,
1193                        struct omap_hsmmc_next *next,
1194                        struct dma_chan *chan)
1195 {
1196     int dma_len;
1197 
1198     if (!next && data->host_cookie &&
1199         data->host_cookie != host->next_data.cookie) {
1200         dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1201                " host->next_data.cookie %d\n",
1202                __func__, data->host_cookie, host->next_data.cookie);
1203         data->host_cookie = 0;
1204     }
1205 
1206     /* Check if next job is already prepared */
1207     if (next || data->host_cookie != host->next_data.cookie) {
1208         dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1209                      mmc_get_dma_dir(data));
1210 
1211     } else {
1212         dma_len = host->next_data.dma_len;
1213         host->next_data.dma_len = 0;
1214     }
1215 
1216 
1217     if (dma_len == 0)
1218         return -EINVAL;
1219 
1220     if (next) {
1221         next->dma_len = dma_len;
1222         data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1223     } else
1224         host->dma_len = dma_len;
1225 
1226     return 0;
1227 }
1228 
1229 /*
1230  * Routine to configure and start DMA for the MMC card
1231  */
1232 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1233                     struct mmc_request *req)
1234 {
1235     struct dma_async_tx_descriptor *tx;
1236     int ret = 0, i;
1237     struct mmc_data *data = req->data;
1238     struct dma_chan *chan;
1239     struct dma_slave_config cfg = {
1240         .src_addr = host->mapbase + OMAP_HSMMC_DATA,
1241         .dst_addr = host->mapbase + OMAP_HSMMC_DATA,
1242         .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1243         .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1244         .src_maxburst = data->blksz / 4,
1245         .dst_maxburst = data->blksz / 4,
1246     };
1247 
1248     /* Sanity check: all the SG entries must be aligned by block size. */
1249     for (i = 0; i < data->sg_len; i++) {
1250         struct scatterlist *sgl;
1251 
1252         sgl = data->sg + i;
1253         if (sgl->length % data->blksz)
1254             return -EINVAL;
1255     }
1256     if ((data->blksz % 4) != 0)
1257         /* REVISIT: The MMC buffer increments only when MSB is written.
1258          * Return error for blksz which is non multiple of four.
1259          */
1260         return -EINVAL;
1261 
1262     BUG_ON(host->dma_ch != -1);
1263 
1264     chan = omap_hsmmc_get_dma_chan(host, data);
1265 
1266     ret = dmaengine_slave_config(chan, &cfg);
1267     if (ret)
1268         return ret;
1269 
1270     ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1271     if (ret)
1272         return ret;
1273 
1274     tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1275         data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1276         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1277     if (!tx) {
1278         dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1279         /* FIXME: cleanup */
1280         return -1;
1281     }
1282 
1283     tx->callback = omap_hsmmc_dma_callback;
1284     tx->callback_param = host;
1285 
1286     /* Does not fail */
1287     dmaengine_submit(tx);
1288 
1289     host->dma_ch = 1;
1290 
1291     return 0;
1292 }
1293 
1294 static void set_data_timeout(struct omap_hsmmc_host *host,
1295                  unsigned long long timeout_ns,
1296                  unsigned int timeout_clks)
1297 {
1298     unsigned long long timeout = timeout_ns;
1299     unsigned int cycle_ns;
1300     uint32_t reg, clkd, dto = 0;
1301 
1302     reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1303     clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1304     if (clkd == 0)
1305         clkd = 1;
1306 
1307     cycle_ns = 1000000000 / (host->clk_rate / clkd);
1308     do_div(timeout, cycle_ns);
1309     timeout += timeout_clks;
1310     if (timeout) {
1311         while ((timeout & 0x80000000) == 0) {
1312             dto += 1;
1313             timeout <<= 1;
1314         }
1315         dto = 31 - dto;
1316         timeout <<= 1;
1317         if (timeout && dto)
1318             dto += 1;
1319         if (dto >= 13)
1320             dto -= 13;
1321         else
1322             dto = 0;
1323         if (dto > 14)
1324             dto = 14;
1325     }
1326 
1327     reg &= ~DTO_MASK;
1328     reg |= dto << DTO_SHIFT;
1329     OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1330 }
1331 
1332 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1333 {
1334     struct mmc_request *req = host->mrq;
1335     struct dma_chan *chan;
1336 
1337     if (!req->data)
1338         return;
1339     OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1340                 | (req->data->blocks << 16));
1341     set_data_timeout(host, req->data->timeout_ns,
1342                 req->data->timeout_clks);
1343     chan = omap_hsmmc_get_dma_chan(host, req->data);
1344     dma_async_issue_pending(chan);
1345 }
1346 
1347 /*
1348  * Configure block length for MMC/SD cards and initiate the transfer.
1349  */
1350 static int
1351 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1352 {
1353     int ret;
1354     unsigned long long timeout;
1355 
1356     host->data = req->data;
1357 
1358     if (req->data == NULL) {
1359         OMAP_HSMMC_WRITE(host->base, BLK, 0);
1360         if (req->cmd->flags & MMC_RSP_BUSY) {
1361             timeout = req->cmd->busy_timeout * NSEC_PER_MSEC;
1362 
1363             /*
1364              * Set an arbitrary 100ms data timeout for commands with
1365              * busy signal and no indication of busy_timeout.
1366              */
1367             if (!timeout)
1368                 timeout = 100000000U;
1369 
1370             set_data_timeout(host, timeout, 0);
1371         }
1372         return 0;
1373     }
1374 
1375     if (host->use_dma) {
1376         ret = omap_hsmmc_setup_dma_transfer(host, req);
1377         if (ret != 0) {
1378             dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1379             return ret;
1380         }
1381     }
1382     return 0;
1383 }
1384 
1385 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1386                 int err)
1387 {
1388     struct omap_hsmmc_host *host = mmc_priv(mmc);
1389     struct mmc_data *data = mrq->data;
1390 
1391     if (host->use_dma && data->host_cookie) {
1392         struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1393 
1394         dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1395                  mmc_get_dma_dir(data));
1396         data->host_cookie = 0;
1397     }
1398 }
1399 
1400 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1401 {
1402     struct omap_hsmmc_host *host = mmc_priv(mmc);
1403 
1404     if (mrq->data->host_cookie) {
1405         mrq->data->host_cookie = 0;
1406         return ;
1407     }
1408 
1409     if (host->use_dma) {
1410         struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1411 
1412         if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1413                         &host->next_data, c))
1414             mrq->data->host_cookie = 0;
1415     }
1416 }
1417 
1418 /*
1419  * Request function. for read/write operation
1420  */
1421 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1422 {
1423     struct omap_hsmmc_host *host = mmc_priv(mmc);
1424     int err;
1425 
1426     BUG_ON(host->req_in_progress);
1427     BUG_ON(host->dma_ch != -1);
1428     if (host->reqs_blocked)
1429         host->reqs_blocked = 0;
1430     WARN_ON(host->mrq != NULL);
1431     host->mrq = req;
1432     host->clk_rate = clk_get_rate(host->fclk);
1433     err = omap_hsmmc_prepare_data(host, req);
1434     if (err) {
1435         req->cmd->error = err;
1436         if (req->data)
1437             req->data->error = err;
1438         host->mrq = NULL;
1439         mmc_request_done(mmc, req);
1440         return;
1441     }
1442     if (req->sbc && !(host->flags & AUTO_CMD23)) {
1443         omap_hsmmc_start_command(host, req->sbc, NULL);
1444         return;
1445     }
1446 
1447     omap_hsmmc_start_dma_transfer(host);
1448     omap_hsmmc_start_command(host, req->cmd, req->data);
1449 }
1450 
1451 /* Routine to configure clock values. Exposed API to core */
1452 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1453 {
1454     struct omap_hsmmc_host *host = mmc_priv(mmc);
1455     int do_send_init_stream = 0;
1456 
1457     if (ios->power_mode != host->power_mode) {
1458         switch (ios->power_mode) {
1459         case MMC_POWER_OFF:
1460             omap_hsmmc_set_power(host, 0);
1461             break;
1462         case MMC_POWER_UP:
1463             omap_hsmmc_set_power(host, 1);
1464             break;
1465         case MMC_POWER_ON:
1466             do_send_init_stream = 1;
1467             break;
1468         }
1469         host->power_mode = ios->power_mode;
1470     }
1471 
1472     /* FIXME: set registers based only on changes to ios */
1473 
1474     omap_hsmmc_set_bus_width(host);
1475 
1476     if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1477         /* Only MMC1 can interface at 3V without some flavor
1478          * of external transceiver; but they all handle 1.8V.
1479          */
1480         if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1481             (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1482                 /*
1483                  * The mmc_select_voltage fn of the core does
1484                  * not seem to set the power_mode to
1485                  * MMC_POWER_UP upon recalculating the voltage.
1486                  * vdd 1.8v.
1487                  */
1488             if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1489                 dev_dbg(mmc_dev(host->mmc),
1490                         "Switch operation failed\n");
1491         }
1492     }
1493 
1494     omap_hsmmc_set_clock(host);
1495 
1496     if (do_send_init_stream)
1497         send_init_stream(host);
1498 
1499     omap_hsmmc_set_bus_mode(host);
1500 }
1501 
1502 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1503 {
1504     struct omap_hsmmc_host *host = mmc_priv(mmc);
1505     u32 irq_mask, con;
1506     unsigned long flags;
1507 
1508     spin_lock_irqsave(&host->irq_lock, flags);
1509 
1510     con = OMAP_HSMMC_READ(host->base, CON);
1511     irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1512     if (enable) {
1513         host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1514         irq_mask |= CIRQ_EN;
1515         con |= CTPL | CLKEXTFREE;
1516     } else {
1517         host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1518         irq_mask &= ~CIRQ_EN;
1519         con &= ~(CTPL | CLKEXTFREE);
1520     }
1521     OMAP_HSMMC_WRITE(host->base, CON, con);
1522     OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1523 
1524     /*
1525      * if enable, piggy back detection on current request
1526      * but always disable immediately
1527      */
1528     if (!host->req_in_progress || !enable)
1529         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1530 
1531     /* flush posted write */
1532     OMAP_HSMMC_READ(host->base, IE);
1533 
1534     spin_unlock_irqrestore(&host->irq_lock, flags);
1535 }
1536 
1537 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1538 {
1539     int ret;
1540 
1541     /*
1542      * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1543      * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1544      * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1545      * with functional clock disabled.
1546      */
1547     if (!host->dev->of_node || !host->wake_irq)
1548         return -ENODEV;
1549 
1550     ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
1551     if (ret) {
1552         dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1553         goto err;
1554     }
1555 
1556     /*
1557      * Some omaps don't have wake-up path from deeper idle states
1558      * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1559      */
1560     if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1561         struct pinctrl *p = devm_pinctrl_get(host->dev);
1562         if (IS_ERR(p)) {
1563             ret = PTR_ERR(p);
1564             goto err_free_irq;
1565         }
1566 
1567         if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1568             dev_info(host->dev, "missing idle pinctrl state\n");
1569             devm_pinctrl_put(p);
1570             ret = -EINVAL;
1571             goto err_free_irq;
1572         }
1573         devm_pinctrl_put(p);
1574     }
1575 
1576     OMAP_HSMMC_WRITE(host->base, HCTL,
1577              OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1578     return 0;
1579 
1580 err_free_irq:
1581     dev_pm_clear_wake_irq(host->dev);
1582 err:
1583     dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1584     host->wake_irq = 0;
1585     return ret;
1586 }
1587 
1588 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1589 {
1590     u32 hctl, capa, value;
1591 
1592     /* Only MMC1 supports 3.0V */
1593     if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1594         hctl = SDVS30;
1595         capa = VS30 | VS18;
1596     } else {
1597         hctl = SDVS18;
1598         capa = VS18;
1599     }
1600 
1601     value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1602     OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1603 
1604     value = OMAP_HSMMC_READ(host->base, CAPA);
1605     OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1606 
1607     /* Set SD bus power bit */
1608     set_sd_bus_power(host);
1609 }
1610 
1611 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1612                      unsigned int direction, int blk_size)
1613 {
1614     /* This controller can't do multiblock reads due to hw bugs */
1615     if (direction == MMC_DATA_READ)
1616         return 1;
1617 
1618     return blk_size;
1619 }
1620 
1621 static struct mmc_host_ops omap_hsmmc_ops = {
1622     .post_req = omap_hsmmc_post_req,
1623     .pre_req = omap_hsmmc_pre_req,
1624     .request = omap_hsmmc_request,
1625     .set_ios = omap_hsmmc_set_ios,
1626     .get_cd = mmc_gpio_get_cd,
1627     .get_ro = mmc_gpio_get_ro,
1628     .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1629 };
1630 
1631 #ifdef CONFIG_DEBUG_FS
1632 
1633 static int mmc_regs_show(struct seq_file *s, void *data)
1634 {
1635     struct mmc_host *mmc = s->private;
1636     struct omap_hsmmc_host *host = mmc_priv(mmc);
1637 
1638     seq_printf(s, "mmc%d:\n", mmc->index);
1639     seq_printf(s, "sdio irq mode\t%s\n",
1640            (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1641 
1642     if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1643         seq_printf(s, "sdio irq \t%s\n",
1644                (host->flags & HSMMC_SDIO_IRQ_ENABLED) ?  "enabled"
1645                : "disabled");
1646     }
1647     seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1648 
1649     pm_runtime_get_sync(host->dev);
1650     seq_puts(s, "\nregs:\n");
1651     seq_printf(s, "CON:\t\t0x%08x\n",
1652             OMAP_HSMMC_READ(host->base, CON));
1653     seq_printf(s, "PSTATE:\t\t0x%08x\n",
1654            OMAP_HSMMC_READ(host->base, PSTATE));
1655     seq_printf(s, "HCTL:\t\t0x%08x\n",
1656             OMAP_HSMMC_READ(host->base, HCTL));
1657     seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1658             OMAP_HSMMC_READ(host->base, SYSCTL));
1659     seq_printf(s, "IE:\t\t0x%08x\n",
1660             OMAP_HSMMC_READ(host->base, IE));
1661     seq_printf(s, "ISE:\t\t0x%08x\n",
1662             OMAP_HSMMC_READ(host->base, ISE));
1663     seq_printf(s, "CAPA:\t\t0x%08x\n",
1664             OMAP_HSMMC_READ(host->base, CAPA));
1665 
1666     pm_runtime_mark_last_busy(host->dev);
1667     pm_runtime_put_autosuspend(host->dev);
1668 
1669     return 0;
1670 }
1671 
1672 DEFINE_SHOW_ATTRIBUTE(mmc_regs);
1673 
1674 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1675 {
1676     if (mmc->debugfs_root)
1677         debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1678             mmc, &mmc_regs_fops);
1679 }
1680 
1681 #else
1682 
1683 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1684 {
1685 }
1686 
1687 #endif
1688 
1689 #ifdef CONFIG_OF
1690 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1691     /* See 35xx errata 2.1.1.128 in SPRZ278F */
1692     .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1693 };
1694 
1695 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1696     .reg_offset = 0x100,
1697 };
1698 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1699     .reg_offset = 0x100,
1700     .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1701 };
1702 
1703 static const struct of_device_id omap_mmc_of_match[] = {
1704     {
1705         .compatible = "ti,omap2-hsmmc",
1706     },
1707     {
1708         .compatible = "ti,omap3-pre-es3-hsmmc",
1709         .data = &omap3_pre_es3_mmc_of_data,
1710     },
1711     {
1712         .compatible = "ti,omap3-hsmmc",
1713     },
1714     {
1715         .compatible = "ti,omap4-hsmmc",
1716         .data = &omap4_mmc_of_data,
1717     },
1718     {
1719         .compatible = "ti,am33xx-hsmmc",
1720         .data = &am33xx_mmc_of_data,
1721     },
1722     {},
1723 };
1724 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1725 
1726 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1727 {
1728     struct omap_hsmmc_platform_data *pdata, *legacy;
1729     struct device_node *np = dev->of_node;
1730 
1731     pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1732     if (!pdata)
1733         return ERR_PTR(-ENOMEM); /* out of memory */
1734 
1735     legacy = dev_get_platdata(dev);
1736     if (legacy && legacy->name)
1737         pdata->name = legacy->name;
1738 
1739     if (of_find_property(np, "ti,dual-volt", NULL))
1740         pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1741 
1742     if (of_find_property(np, "ti,non-removable", NULL)) {
1743         pdata->nonremovable = true;
1744         pdata->no_regulator_off_init = true;
1745     }
1746 
1747     if (of_find_property(np, "ti,needs-special-reset", NULL))
1748         pdata->features |= HSMMC_HAS_UPDATED_RESET;
1749 
1750     if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1751         pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1752 
1753     return pdata;
1754 }
1755 #else
1756 static inline struct omap_hsmmc_platform_data
1757             *of_get_hsmmc_pdata(struct device *dev)
1758 {
1759     return ERR_PTR(-EINVAL);
1760 }
1761 #endif
1762 
1763 static int omap_hsmmc_probe(struct platform_device *pdev)
1764 {
1765     struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
1766     struct mmc_host *mmc;
1767     struct omap_hsmmc_host *host = NULL;
1768     struct resource *res;
1769     int ret, irq;
1770     const struct of_device_id *match;
1771     const struct omap_mmc_of_data *data;
1772     void __iomem *base;
1773 
1774     match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1775     if (match) {
1776         pdata = of_get_hsmmc_pdata(&pdev->dev);
1777 
1778         if (IS_ERR(pdata))
1779             return PTR_ERR(pdata);
1780 
1781         if (match->data) {
1782             data = match->data;
1783             pdata->reg_offset = data->reg_offset;
1784             pdata->controller_flags |= data->controller_flags;
1785         }
1786     }
1787 
1788     if (pdata == NULL) {
1789         dev_err(&pdev->dev, "Platform Data is missing\n");
1790         return -ENXIO;
1791     }
1792 
1793     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1794     irq = platform_get_irq(pdev, 0);
1795     if (res == NULL || irq < 0)
1796         return -ENXIO;
1797 
1798     base = devm_ioremap_resource(&pdev->dev, res);
1799     if (IS_ERR(base))
1800         return PTR_ERR(base);
1801 
1802     mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1803     if (!mmc) {
1804         ret = -ENOMEM;
1805         goto err;
1806     }
1807 
1808     ret = mmc_of_parse(mmc);
1809     if (ret)
1810         goto err1;
1811 
1812     host        = mmc_priv(mmc);
1813     host->mmc   = mmc;
1814     host->pdata = pdata;
1815     host->dev   = &pdev->dev;
1816     host->use_dma   = 1;
1817     host->dma_ch    = -1;
1818     host->irq   = irq;
1819     host->mapbase   = res->start + pdata->reg_offset;
1820     host->base  = base + pdata->reg_offset;
1821     host->power_mode = MMC_POWER_OFF;
1822     host->next_data.cookie = 1;
1823     host->pbias_enabled = false;
1824     host->vqmmc_enabled = false;
1825 
1826     platform_set_drvdata(pdev, host);
1827 
1828     if (pdev->dev.of_node)
1829         host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1830 
1831     mmc->ops    = &omap_hsmmc_ops;
1832 
1833     mmc->f_min = OMAP_MMC_MIN_CLOCK;
1834 
1835     if (pdata->max_freq > 0)
1836         mmc->f_max = pdata->max_freq;
1837     else if (mmc->f_max == 0)
1838         mmc->f_max = OMAP_MMC_MAX_CLOCK;
1839 
1840     spin_lock_init(&host->irq_lock);
1841 
1842     host->fclk = devm_clk_get(&pdev->dev, "fck");
1843     if (IS_ERR(host->fclk)) {
1844         ret = PTR_ERR(host->fclk);
1845         host->fclk = NULL;
1846         goto err1;
1847     }
1848 
1849     if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1850         dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1851         omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
1852     }
1853 
1854     device_init_wakeup(&pdev->dev, true);
1855     pm_runtime_enable(host->dev);
1856     pm_runtime_get_sync(host->dev);
1857     pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1858     pm_runtime_use_autosuspend(host->dev);
1859 
1860     omap_hsmmc_context_save(host);
1861 
1862     host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
1863     /*
1864      * MMC can still work without debounce clock.
1865      */
1866     if (IS_ERR(host->dbclk)) {
1867         host->dbclk = NULL;
1868     } else if (clk_prepare_enable(host->dbclk) != 0) {
1869         dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1870         host->dbclk = NULL;
1871     }
1872 
1873     /* Set this to a value that allows allocating an entire descriptor
1874      * list within a page (zero order allocation). */
1875     mmc->max_segs = 64;
1876 
1877     mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1878     mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1879     mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1880 
1881     mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1882              MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_CMD23;
1883 
1884     mmc->caps |= mmc_pdata(host)->caps;
1885     if (mmc->caps & MMC_CAP_8_BIT_DATA)
1886         mmc->caps |= MMC_CAP_4_BIT_DATA;
1887 
1888     if (mmc_pdata(host)->nonremovable)
1889         mmc->caps |= MMC_CAP_NONREMOVABLE;
1890 
1891     mmc->pm_caps |= mmc_pdata(host)->pm_caps;
1892 
1893     omap_hsmmc_conf_bus_power(host);
1894 
1895     host->rx_chan = dma_request_chan(&pdev->dev, "rx");
1896     if (IS_ERR(host->rx_chan)) {
1897         dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n");
1898         ret = PTR_ERR(host->rx_chan);
1899         goto err_irq;
1900     }
1901 
1902     host->tx_chan = dma_request_chan(&pdev->dev, "tx");
1903     if (IS_ERR(host->tx_chan)) {
1904         dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n");
1905         ret = PTR_ERR(host->tx_chan);
1906         goto err_irq;
1907     }
1908 
1909     /*
1910      * Limit the maximum segment size to the lower of the request size
1911      * and the DMA engine device segment size limits.  In reality, with
1912      * 32-bit transfers, the DMA engine can do longer segments than this
1913      * but there is no way to represent that in the DMA model - if we
1914      * increase this figure here, we get warnings from the DMA API debug.
1915      */
1916     mmc->max_seg_size = min3(mmc->max_req_size,
1917             dma_get_max_seg_size(host->rx_chan->device->dev),
1918             dma_get_max_seg_size(host->tx_chan->device->dev));
1919 
1920     /* Request IRQ for MMC operations */
1921     ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
1922             mmc_hostname(mmc), host);
1923     if (ret) {
1924         dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1925         goto err_irq;
1926     }
1927 
1928     ret = omap_hsmmc_reg_get(host);
1929     if (ret)
1930         goto err_irq;
1931 
1932     if (!mmc->ocr_avail)
1933         mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
1934 
1935     omap_hsmmc_disable_irq(host);
1936 
1937     /*
1938      * For now, only support SDIO interrupt if we have a separate
1939      * wake-up interrupt configured from device tree. This is because
1940      * the wake-up interrupt is needed for idle state and some
1941      * platforms need special quirks. And we don't want to add new
1942      * legacy mux platform init code callbacks any longer as we
1943      * are moving to DT based booting anyways.
1944      */
1945     ret = omap_hsmmc_configure_wake_irq(host);
1946     if (!ret)
1947         mmc->caps |= MMC_CAP_SDIO_IRQ;
1948 
1949     mmc_add_host(mmc);
1950 
1951     if (mmc_pdata(host)->name != NULL) {
1952         ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1953         if (ret < 0)
1954             goto err_slot_name;
1955     }
1956 
1957     omap_hsmmc_debugfs(mmc);
1958     pm_runtime_mark_last_busy(host->dev);
1959     pm_runtime_put_autosuspend(host->dev);
1960 
1961     return 0;
1962 
1963 err_slot_name:
1964     mmc_remove_host(mmc);
1965 err_irq:
1966     device_init_wakeup(&pdev->dev, false);
1967     if (!IS_ERR_OR_NULL(host->tx_chan))
1968         dma_release_channel(host->tx_chan);
1969     if (!IS_ERR_OR_NULL(host->rx_chan))
1970         dma_release_channel(host->rx_chan);
1971     pm_runtime_dont_use_autosuspend(host->dev);
1972     pm_runtime_put_sync(host->dev);
1973     pm_runtime_disable(host->dev);
1974     clk_disable_unprepare(host->dbclk);
1975 err1:
1976     mmc_free_host(mmc);
1977 err:
1978     return ret;
1979 }
1980 
1981 static int omap_hsmmc_remove(struct platform_device *pdev)
1982 {
1983     struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1984 
1985     pm_runtime_get_sync(host->dev);
1986     mmc_remove_host(host->mmc);
1987 
1988     dma_release_channel(host->tx_chan);
1989     dma_release_channel(host->rx_chan);
1990 
1991     dev_pm_clear_wake_irq(host->dev);
1992     pm_runtime_dont_use_autosuspend(host->dev);
1993     pm_runtime_put_sync(host->dev);
1994     pm_runtime_disable(host->dev);
1995     device_init_wakeup(&pdev->dev, false);
1996     clk_disable_unprepare(host->dbclk);
1997 
1998     mmc_free_host(host->mmc);
1999 
2000     return 0;
2001 }
2002 
2003 #ifdef CONFIG_PM_SLEEP
2004 static int omap_hsmmc_suspend(struct device *dev)
2005 {
2006     struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2007 
2008     if (!host)
2009         return 0;
2010 
2011     pm_runtime_get_sync(host->dev);
2012 
2013     if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2014         OMAP_HSMMC_WRITE(host->base, ISE, 0);
2015         OMAP_HSMMC_WRITE(host->base, IE, 0);
2016         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2017         OMAP_HSMMC_WRITE(host->base, HCTL,
2018                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2019     }
2020 
2021     clk_disable_unprepare(host->dbclk);
2022 
2023     pm_runtime_put_sync(host->dev);
2024     return 0;
2025 }
2026 
2027 /* Routine to resume the MMC device */
2028 static int omap_hsmmc_resume(struct device *dev)
2029 {
2030     struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2031 
2032     if (!host)
2033         return 0;
2034 
2035     pm_runtime_get_sync(host->dev);
2036 
2037     clk_prepare_enable(host->dbclk);
2038 
2039     if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2040         omap_hsmmc_conf_bus_power(host);
2041 
2042     pm_runtime_mark_last_busy(host->dev);
2043     pm_runtime_put_autosuspend(host->dev);
2044     return 0;
2045 }
2046 #endif
2047 
2048 #ifdef CONFIG_PM
2049 static int omap_hsmmc_runtime_suspend(struct device *dev)
2050 {
2051     struct omap_hsmmc_host *host;
2052     unsigned long flags;
2053     int ret = 0;
2054 
2055     host = dev_get_drvdata(dev);
2056     omap_hsmmc_context_save(host);
2057     dev_dbg(dev, "disabled\n");
2058 
2059     spin_lock_irqsave(&host->irq_lock, flags);
2060     if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2061         (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2062         /* disable sdio irq handling to prevent race */
2063         OMAP_HSMMC_WRITE(host->base, ISE, 0);
2064         OMAP_HSMMC_WRITE(host->base, IE, 0);
2065 
2066         if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2067             /*
2068              * dat1 line low, pending sdio irq
2069              * race condition: possible irq handler running on
2070              * multi-core, abort
2071              */
2072             dev_dbg(dev, "pending sdio irq, abort suspend\n");
2073             OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2074             OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2075             OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2076             pm_runtime_mark_last_busy(dev);
2077             ret = -EBUSY;
2078             goto abort;
2079         }
2080 
2081         pinctrl_pm_select_idle_state(dev);
2082     } else {
2083         pinctrl_pm_select_idle_state(dev);
2084     }
2085 
2086 abort:
2087     spin_unlock_irqrestore(&host->irq_lock, flags);
2088     return ret;
2089 }
2090 
2091 static int omap_hsmmc_runtime_resume(struct device *dev)
2092 {
2093     struct omap_hsmmc_host *host;
2094     unsigned long flags;
2095 
2096     host = dev_get_drvdata(dev);
2097     omap_hsmmc_context_restore(host);
2098     dev_dbg(dev, "enabled\n");
2099 
2100     spin_lock_irqsave(&host->irq_lock, flags);
2101     if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2102         (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2103 
2104         pinctrl_select_default_state(host->dev);
2105 
2106         /* irq lost, if pinmux incorrect */
2107         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2108         OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2109         OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2110     } else {
2111         pinctrl_select_default_state(host->dev);
2112     }
2113     spin_unlock_irqrestore(&host->irq_lock, flags);
2114     return 0;
2115 }
2116 #endif
2117 
2118 static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2119     SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
2120     SET_RUNTIME_PM_OPS(omap_hsmmc_runtime_suspend, omap_hsmmc_runtime_resume, NULL)
2121 };
2122 
2123 static struct platform_driver omap_hsmmc_driver = {
2124     .probe      = omap_hsmmc_probe,
2125     .remove     = omap_hsmmc_remove,
2126     .driver     = {
2127         .name = DRIVER_NAME,
2128         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2129         .pm = &omap_hsmmc_dev_pm_ops,
2130         .of_match_table = of_match_ptr(omap_mmc_of_match),
2131     },
2132 };
2133 
2134 module_platform_driver(omap_hsmmc_driver);
2135 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2136 MODULE_LICENSE("GPL");
2137 MODULE_ALIAS("platform:" DRIVER_NAME);
2138 MODULE_AUTHOR("Texas Instruments Inc");
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