Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/drivers/mmc/host/omap.c
0004  *
0005  *  Copyright (C) 2004 Nokia Corporation
0006  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
0007  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
0008  *  Other hacks (DMA, SD, etc) by David Brownell
0009  */
0010 
0011 #include <linux/module.h>
0012 #include <linux/moduleparam.h>
0013 #include <linux/init.h>
0014 #include <linux/ioport.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/dmaengine.h>
0018 #include <linux/dma-mapping.h>
0019 #include <linux/delay.h>
0020 #include <linux/spinlock.h>
0021 #include <linux/timer.h>
0022 #include <linux/of.h>
0023 #include <linux/mmc/host.h>
0024 #include <linux/mmc/card.h>
0025 #include <linux/mmc/mmc.h>
0026 #include <linux/clk.h>
0027 #include <linux/scatterlist.h>
0028 #include <linux/slab.h>
0029 #include <linux/platform_data/mmc-omap.h>
0030 
0031 
0032 #define OMAP_MMC_REG_CMD    0x00
0033 #define OMAP_MMC_REG_ARGL   0x01
0034 #define OMAP_MMC_REG_ARGH   0x02
0035 #define OMAP_MMC_REG_CON    0x03
0036 #define OMAP_MMC_REG_STAT   0x04
0037 #define OMAP_MMC_REG_IE     0x05
0038 #define OMAP_MMC_REG_CTO    0x06
0039 #define OMAP_MMC_REG_DTO    0x07
0040 #define OMAP_MMC_REG_DATA   0x08
0041 #define OMAP_MMC_REG_BLEN   0x09
0042 #define OMAP_MMC_REG_NBLK   0x0a
0043 #define OMAP_MMC_REG_BUF    0x0b
0044 #define OMAP_MMC_REG_SDIO   0x0d
0045 #define OMAP_MMC_REG_REV    0x0f
0046 #define OMAP_MMC_REG_RSP0   0x10
0047 #define OMAP_MMC_REG_RSP1   0x11
0048 #define OMAP_MMC_REG_RSP2   0x12
0049 #define OMAP_MMC_REG_RSP3   0x13
0050 #define OMAP_MMC_REG_RSP4   0x14
0051 #define OMAP_MMC_REG_RSP5   0x15
0052 #define OMAP_MMC_REG_RSP6   0x16
0053 #define OMAP_MMC_REG_RSP7   0x17
0054 #define OMAP_MMC_REG_IOSR   0x18
0055 #define OMAP_MMC_REG_SYSC   0x19
0056 #define OMAP_MMC_REG_SYSS   0x1a
0057 
0058 #define OMAP_MMC_STAT_CARD_ERR      (1 << 14)
0059 #define OMAP_MMC_STAT_CARD_IRQ      (1 << 13)
0060 #define OMAP_MMC_STAT_OCR_BUSY      (1 << 12)
0061 #define OMAP_MMC_STAT_A_EMPTY       (1 << 11)
0062 #define OMAP_MMC_STAT_A_FULL        (1 << 10)
0063 #define OMAP_MMC_STAT_CMD_CRC       (1 <<  8)
0064 #define OMAP_MMC_STAT_CMD_TOUT      (1 <<  7)
0065 #define OMAP_MMC_STAT_DATA_CRC      (1 <<  6)
0066 #define OMAP_MMC_STAT_DATA_TOUT     (1 <<  5)
0067 #define OMAP_MMC_STAT_END_BUSY      (1 <<  4)
0068 #define OMAP_MMC_STAT_END_OF_DATA   (1 <<  3)
0069 #define OMAP_MMC_STAT_CARD_BUSY     (1 <<  2)
0070 #define OMAP_MMC_STAT_END_OF_CMD    (1 <<  0)
0071 
0072 #define mmc_omap7xx()   (host->features & MMC_OMAP7XX)
0073 #define mmc_omap15xx()  (host->features & MMC_OMAP15XX)
0074 #define mmc_omap16xx()  (host->features & MMC_OMAP16XX)
0075 #define MMC_OMAP1_MASK  (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
0076 #define mmc_omap1() (host->features & MMC_OMAP1_MASK)
0077 #define mmc_omap2() (!mmc_omap1())
0078 
0079 #define OMAP_MMC_REG(host, reg)     (OMAP_MMC_REG_##reg << (host)->reg_shift)
0080 #define OMAP_MMC_READ(host, reg)    __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
0081 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
0082 
0083 /*
0084  * Command types
0085  */
0086 #define OMAP_MMC_CMDTYPE_BC 0
0087 #define OMAP_MMC_CMDTYPE_BCR    1
0088 #define OMAP_MMC_CMDTYPE_AC 2
0089 #define OMAP_MMC_CMDTYPE_ADTC   3
0090 
0091 #define DRIVER_NAME "mmci-omap"
0092 
0093 /* Specifies how often in millisecs to poll for card status changes
0094  * when the cover switch is open */
0095 #define OMAP_MMC_COVER_POLL_DELAY   500
0096 
0097 struct mmc_omap_host;
0098 
0099 struct mmc_omap_slot {
0100     int         id;
0101     unsigned int        vdd;
0102     u16         saved_con;
0103     u16         bus_mode;
0104     u16         power_mode;
0105     unsigned int        fclk_freq;
0106 
0107     struct tasklet_struct   cover_tasklet;
0108     struct timer_list       cover_timer;
0109     unsigned        cover_open;
0110 
0111     struct mmc_request      *mrq;
0112     struct mmc_omap_host    *host;
0113     struct mmc_host     *mmc;
0114     struct omap_mmc_slot_data *pdata;
0115 };
0116 
0117 struct mmc_omap_host {
0118     int         initialized;
0119     struct mmc_request *    mrq;
0120     struct mmc_command *    cmd;
0121     struct mmc_data *   data;
0122     struct mmc_host *   mmc;
0123     struct device *     dev;
0124     unsigned char       id; /* 16xx chips have 2 MMC blocks */
0125     struct clk *        iclk;
0126     struct clk *        fclk;
0127     struct dma_chan     *dma_rx;
0128     u32         dma_rx_burst;
0129     struct dma_chan     *dma_tx;
0130     u32         dma_tx_burst;
0131     void __iomem        *virt_base;
0132     unsigned int        phys_base;
0133     int         irq;
0134     unsigned char       bus_mode;
0135     unsigned int        reg_shift;
0136 
0137     struct work_struct  cmd_abort_work;
0138     unsigned        abort:1;
0139     struct timer_list   cmd_abort_timer;
0140 
0141     struct work_struct      slot_release_work;
0142     struct mmc_omap_slot    *next_slot;
0143     struct work_struct      send_stop_work;
0144     struct mmc_data     *stop_data;
0145 
0146     unsigned int        sg_len;
0147     int         sg_idx;
0148     u16 *           buffer;
0149     u32         buffer_bytes_left;
0150     u32         total_bytes_left;
0151 
0152     unsigned        features;
0153     unsigned        brs_received:1, dma_done:1;
0154     unsigned        dma_in_use:1;
0155     spinlock_t      dma_lock;
0156 
0157     struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
0158     struct mmc_omap_slot    *current_slot;
0159     spinlock_t              slot_lock;
0160     wait_queue_head_t       slot_wq;
0161     int                     nr_slots;
0162 
0163     struct timer_list       clk_timer;
0164     spinlock_t      clk_lock;     /* for changing enabled state */
0165     unsigned int            fclk_enabled:1;
0166     struct workqueue_struct *mmc_omap_wq;
0167 
0168     struct omap_mmc_platform_data *pdata;
0169 };
0170 
0171 
0172 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
0173 {
0174     unsigned long tick_ns;
0175 
0176     if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
0177         tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
0178         ndelay(8 * tick_ns);
0179     }
0180 }
0181 
0182 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
0183 {
0184     unsigned long flags;
0185 
0186     spin_lock_irqsave(&host->clk_lock, flags);
0187     if (host->fclk_enabled != enable) {
0188         host->fclk_enabled = enable;
0189         if (enable)
0190             clk_enable(host->fclk);
0191         else
0192             clk_disable(host->fclk);
0193     }
0194     spin_unlock_irqrestore(&host->clk_lock, flags);
0195 }
0196 
0197 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
0198 {
0199     struct mmc_omap_host *host = slot->host;
0200     unsigned long flags;
0201 
0202     if (claimed)
0203         goto no_claim;
0204     spin_lock_irqsave(&host->slot_lock, flags);
0205     while (host->mmc != NULL) {
0206         spin_unlock_irqrestore(&host->slot_lock, flags);
0207         wait_event(host->slot_wq, host->mmc == NULL);
0208         spin_lock_irqsave(&host->slot_lock, flags);
0209     }
0210     host->mmc = slot->mmc;
0211     spin_unlock_irqrestore(&host->slot_lock, flags);
0212 no_claim:
0213     del_timer(&host->clk_timer);
0214     if (host->current_slot != slot || !claimed)
0215         mmc_omap_fclk_offdelay(host->current_slot);
0216 
0217     if (host->current_slot != slot) {
0218         OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
0219         if (host->pdata->switch_slot != NULL)
0220             host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
0221         host->current_slot = slot;
0222     }
0223 
0224     if (claimed) {
0225         mmc_omap_fclk_enable(host, 1);
0226 
0227         /* Doing the dummy read here seems to work around some bug
0228          * at least in OMAP24xx silicon where the command would not
0229          * start after writing the CMD register. Sigh. */
0230         OMAP_MMC_READ(host, CON);
0231 
0232         OMAP_MMC_WRITE(host, CON, slot->saved_con);
0233     } else
0234         mmc_omap_fclk_enable(host, 0);
0235 }
0236 
0237 static void mmc_omap_start_request(struct mmc_omap_host *host,
0238                    struct mmc_request *req);
0239 
0240 static void mmc_omap_slot_release_work(struct work_struct *work)
0241 {
0242     struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
0243                           slot_release_work);
0244     struct mmc_omap_slot *next_slot = host->next_slot;
0245     struct mmc_request *rq;
0246 
0247     host->next_slot = NULL;
0248     mmc_omap_select_slot(next_slot, 1);
0249 
0250     rq = next_slot->mrq;
0251     next_slot->mrq = NULL;
0252     mmc_omap_start_request(host, rq);
0253 }
0254 
0255 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
0256 {
0257     struct mmc_omap_host *host = slot->host;
0258     unsigned long flags;
0259     int i;
0260 
0261     BUG_ON(slot == NULL || host->mmc == NULL);
0262 
0263     if (clk_enabled)
0264         /* Keeps clock running for at least 8 cycles on valid freq */
0265         mod_timer(&host->clk_timer, jiffies  + HZ/10);
0266     else {
0267         del_timer(&host->clk_timer);
0268         mmc_omap_fclk_offdelay(slot);
0269         mmc_omap_fclk_enable(host, 0);
0270     }
0271 
0272     spin_lock_irqsave(&host->slot_lock, flags);
0273     /* Check for any pending requests */
0274     for (i = 0; i < host->nr_slots; i++) {
0275         struct mmc_omap_slot *new_slot;
0276 
0277         if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
0278             continue;
0279 
0280         BUG_ON(host->next_slot != NULL);
0281         new_slot = host->slots[i];
0282         /* The current slot should not have a request in queue */
0283         BUG_ON(new_slot == host->current_slot);
0284 
0285         host->next_slot = new_slot;
0286         host->mmc = new_slot->mmc;
0287         spin_unlock_irqrestore(&host->slot_lock, flags);
0288         queue_work(host->mmc_omap_wq, &host->slot_release_work);
0289         return;
0290     }
0291 
0292     host->mmc = NULL;
0293     wake_up(&host->slot_wq);
0294     spin_unlock_irqrestore(&host->slot_lock, flags);
0295 }
0296 
0297 static inline
0298 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
0299 {
0300     if (slot->pdata->get_cover_state)
0301         return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
0302                             slot->id);
0303     return 0;
0304 }
0305 
0306 static ssize_t
0307 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
0308                char *buf)
0309 {
0310     struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
0311     struct mmc_omap_slot *slot = mmc_priv(mmc);
0312 
0313     return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
0314                "closed");
0315 }
0316 
0317 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
0318 
0319 static ssize_t
0320 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
0321             char *buf)
0322 {
0323     struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
0324     struct mmc_omap_slot *slot = mmc_priv(mmc);
0325 
0326     return sprintf(buf, "%s\n", slot->pdata->name);
0327 }
0328 
0329 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
0330 
0331 static void
0332 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
0333 {
0334     u32 cmdreg;
0335     u32 resptype;
0336     u32 cmdtype;
0337     u16 irq_mask;
0338 
0339     host->cmd = cmd;
0340 
0341     resptype = 0;
0342     cmdtype = 0;
0343 
0344     /* Our hardware needs to know exact type */
0345     switch (mmc_resp_type(cmd)) {
0346     case MMC_RSP_NONE:
0347         break;
0348     case MMC_RSP_R1:
0349     case MMC_RSP_R1B:
0350         /* resp 1, 1b, 6, 7 */
0351         resptype = 1;
0352         break;
0353     case MMC_RSP_R2:
0354         resptype = 2;
0355         break;
0356     case MMC_RSP_R3:
0357         resptype = 3;
0358         break;
0359     default:
0360         dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
0361         break;
0362     }
0363 
0364     if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
0365         cmdtype = OMAP_MMC_CMDTYPE_ADTC;
0366     } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
0367         cmdtype = OMAP_MMC_CMDTYPE_BC;
0368     } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
0369         cmdtype = OMAP_MMC_CMDTYPE_BCR;
0370     } else {
0371         cmdtype = OMAP_MMC_CMDTYPE_AC;
0372     }
0373 
0374     cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
0375 
0376     if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
0377         cmdreg |= 1 << 6;
0378 
0379     if (cmd->flags & MMC_RSP_BUSY)
0380         cmdreg |= 1 << 11;
0381 
0382     if (host->data && !(host->data->flags & MMC_DATA_WRITE))
0383         cmdreg |= 1 << 15;
0384 
0385     mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
0386 
0387     OMAP_MMC_WRITE(host, CTO, 200);
0388     OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
0389     OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
0390     irq_mask = OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
0391            OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
0392            OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
0393            OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
0394            OMAP_MMC_STAT_END_OF_DATA;
0395     if (cmd->opcode == MMC_ERASE)
0396         irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT;
0397     OMAP_MMC_WRITE(host, IE, irq_mask);
0398     OMAP_MMC_WRITE(host, CMD, cmdreg);
0399 }
0400 
0401 static void
0402 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
0403              int abort)
0404 {
0405     enum dma_data_direction dma_data_dir;
0406     struct device *dev = mmc_dev(host->mmc);
0407     struct dma_chan *c;
0408 
0409     if (data->flags & MMC_DATA_WRITE) {
0410         dma_data_dir = DMA_TO_DEVICE;
0411         c = host->dma_tx;
0412     } else {
0413         dma_data_dir = DMA_FROM_DEVICE;
0414         c = host->dma_rx;
0415     }
0416     if (c) {
0417         if (data->error) {
0418             dmaengine_terminate_all(c);
0419             /* Claim nothing transferred on error... */
0420             data->bytes_xfered = 0;
0421         }
0422         dev = c->device->dev;
0423     }
0424     dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
0425 }
0426 
0427 static void mmc_omap_send_stop_work(struct work_struct *work)
0428 {
0429     struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
0430                           send_stop_work);
0431     struct mmc_omap_slot *slot = host->current_slot;
0432     struct mmc_data *data = host->stop_data;
0433     unsigned long tick_ns;
0434 
0435     tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
0436     ndelay(8*tick_ns);
0437 
0438     mmc_omap_start_command(host, data->stop);
0439 }
0440 
0441 static void
0442 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
0443 {
0444     if (host->dma_in_use)
0445         mmc_omap_release_dma(host, data, data->error);
0446 
0447     host->data = NULL;
0448     host->sg_len = 0;
0449 
0450     /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
0451      * dozens of requests until the card finishes writing data.
0452      * It'd be cheaper to just wait till an EOFB interrupt arrives...
0453      */
0454 
0455     if (!data->stop) {
0456         struct mmc_host *mmc;
0457 
0458         host->mrq = NULL;
0459         mmc = host->mmc;
0460         mmc_omap_release_slot(host->current_slot, 1);
0461         mmc_request_done(mmc, data->mrq);
0462         return;
0463     }
0464 
0465     host->stop_data = data;
0466     queue_work(host->mmc_omap_wq, &host->send_stop_work);
0467 }
0468 
0469 static void
0470 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
0471 {
0472     struct mmc_omap_slot *slot = host->current_slot;
0473     unsigned int restarts, passes, timeout;
0474     u16 stat = 0;
0475 
0476     /* Sending abort takes 80 clocks. Have some extra and round up */
0477     timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq);
0478     restarts = 0;
0479     while (restarts < maxloops) {
0480         OMAP_MMC_WRITE(host, STAT, 0xFFFF);
0481         OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
0482 
0483         passes = 0;
0484         while (passes < timeout) {
0485             stat = OMAP_MMC_READ(host, STAT);
0486             if (stat & OMAP_MMC_STAT_END_OF_CMD)
0487                 goto out;
0488             udelay(1);
0489             passes++;
0490         }
0491 
0492         restarts++;
0493     }
0494 out:
0495     OMAP_MMC_WRITE(host, STAT, stat);
0496 }
0497 
0498 static void
0499 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
0500 {
0501     if (host->dma_in_use)
0502         mmc_omap_release_dma(host, data, 1);
0503 
0504     host->data = NULL;
0505     host->sg_len = 0;
0506 
0507     mmc_omap_send_abort(host, 10000);
0508 }
0509 
0510 static void
0511 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
0512 {
0513     unsigned long flags;
0514     int done;
0515 
0516     if (!host->dma_in_use) {
0517         mmc_omap_xfer_done(host, data);
0518         return;
0519     }
0520     done = 0;
0521     spin_lock_irqsave(&host->dma_lock, flags);
0522     if (host->dma_done)
0523         done = 1;
0524     else
0525         host->brs_received = 1;
0526     spin_unlock_irqrestore(&host->dma_lock, flags);
0527     if (done)
0528         mmc_omap_xfer_done(host, data);
0529 }
0530 
0531 static void
0532 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
0533 {
0534     unsigned long flags;
0535     int done;
0536 
0537     done = 0;
0538     spin_lock_irqsave(&host->dma_lock, flags);
0539     if (host->brs_received)
0540         done = 1;
0541     else
0542         host->dma_done = 1;
0543     spin_unlock_irqrestore(&host->dma_lock, flags);
0544     if (done)
0545         mmc_omap_xfer_done(host, data);
0546 }
0547 
0548 static void
0549 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
0550 {
0551     host->cmd = NULL;
0552 
0553     del_timer(&host->cmd_abort_timer);
0554 
0555     if (cmd->flags & MMC_RSP_PRESENT) {
0556         if (cmd->flags & MMC_RSP_136) {
0557             /* response type 2 */
0558             cmd->resp[3] =
0559                 OMAP_MMC_READ(host, RSP0) |
0560                 (OMAP_MMC_READ(host, RSP1) << 16);
0561             cmd->resp[2] =
0562                 OMAP_MMC_READ(host, RSP2) |
0563                 (OMAP_MMC_READ(host, RSP3) << 16);
0564             cmd->resp[1] =
0565                 OMAP_MMC_READ(host, RSP4) |
0566                 (OMAP_MMC_READ(host, RSP5) << 16);
0567             cmd->resp[0] =
0568                 OMAP_MMC_READ(host, RSP6) |
0569                 (OMAP_MMC_READ(host, RSP7) << 16);
0570         } else {
0571             /* response types 1, 1b, 3, 4, 5, 6 */
0572             cmd->resp[0] =
0573                 OMAP_MMC_READ(host, RSP6) |
0574                 (OMAP_MMC_READ(host, RSP7) << 16);
0575         }
0576     }
0577 
0578     if (host->data == NULL || cmd->error) {
0579         struct mmc_host *mmc;
0580 
0581         if (host->data != NULL)
0582             mmc_omap_abort_xfer(host, host->data);
0583         host->mrq = NULL;
0584         mmc = host->mmc;
0585         mmc_omap_release_slot(host->current_slot, 1);
0586         mmc_request_done(mmc, cmd->mrq);
0587     }
0588 }
0589 
0590 /*
0591  * Abort stuck command. Can occur when card is removed while it is being
0592  * read.
0593  */
0594 static void mmc_omap_abort_command(struct work_struct *work)
0595 {
0596     struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
0597                           cmd_abort_work);
0598     BUG_ON(!host->cmd);
0599 
0600     dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
0601         host->cmd->opcode);
0602 
0603     if (host->cmd->error == 0)
0604         host->cmd->error = -ETIMEDOUT;
0605 
0606     if (host->data == NULL) {
0607         struct mmc_command *cmd;
0608         struct mmc_host    *mmc;
0609 
0610         cmd = host->cmd;
0611         host->cmd = NULL;
0612         mmc_omap_send_abort(host, 10000);
0613 
0614         host->mrq = NULL;
0615         mmc = host->mmc;
0616         mmc_omap_release_slot(host->current_slot, 1);
0617         mmc_request_done(mmc, cmd->mrq);
0618     } else
0619         mmc_omap_cmd_done(host, host->cmd);
0620 
0621     host->abort = 0;
0622     enable_irq(host->irq);
0623 }
0624 
0625 static void
0626 mmc_omap_cmd_timer(struct timer_list *t)
0627 {
0628     struct mmc_omap_host *host = from_timer(host, t, cmd_abort_timer);
0629     unsigned long flags;
0630 
0631     spin_lock_irqsave(&host->slot_lock, flags);
0632     if (host->cmd != NULL && !host->abort) {
0633         OMAP_MMC_WRITE(host, IE, 0);
0634         disable_irq(host->irq);
0635         host->abort = 1;
0636         queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
0637     }
0638     spin_unlock_irqrestore(&host->slot_lock, flags);
0639 }
0640 
0641 /* PIO only */
0642 static void
0643 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
0644 {
0645     struct scatterlist *sg;
0646 
0647     sg = host->data->sg + host->sg_idx;
0648     host->buffer_bytes_left = sg->length;
0649     host->buffer = sg_virt(sg);
0650     if (host->buffer_bytes_left > host->total_bytes_left)
0651         host->buffer_bytes_left = host->total_bytes_left;
0652 }
0653 
0654 static void
0655 mmc_omap_clk_timer(struct timer_list *t)
0656 {
0657     struct mmc_omap_host *host = from_timer(host, t, clk_timer);
0658 
0659     mmc_omap_fclk_enable(host, 0);
0660 }
0661 
0662 /* PIO only */
0663 static void
0664 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
0665 {
0666     int n, nwords;
0667 
0668     if (host->buffer_bytes_left == 0) {
0669         host->sg_idx++;
0670         BUG_ON(host->sg_idx == host->sg_len);
0671         mmc_omap_sg_to_buf(host);
0672     }
0673     n = 64;
0674     if (n > host->buffer_bytes_left)
0675         n = host->buffer_bytes_left;
0676 
0677     /* Round up to handle odd number of bytes to transfer */
0678     nwords = DIV_ROUND_UP(n, 2);
0679 
0680     host->buffer_bytes_left -= n;
0681     host->total_bytes_left -= n;
0682     host->data->bytes_xfered += n;
0683 
0684     if (write) {
0685         __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
0686                   host->buffer, nwords);
0687     } else {
0688         __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
0689                  host->buffer, nwords);
0690     }
0691 
0692     host->buffer += nwords;
0693 }
0694 
0695 #ifdef CONFIG_MMC_DEBUG
0696 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
0697 {
0698     static const char *mmc_omap_status_bits[] = {
0699         "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
0700         "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
0701     };
0702     int i;
0703     char res[64], *buf = res;
0704 
0705     buf += sprintf(buf, "MMC IRQ 0x%x:", status);
0706 
0707     for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
0708         if (status & (1 << i))
0709             buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
0710     dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
0711 }
0712 #else
0713 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
0714 {
0715 }
0716 #endif
0717 
0718 
0719 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
0720 {
0721     struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
0722     u16 status;
0723     int end_command;
0724     int end_transfer;
0725     int transfer_error, cmd_error;
0726 
0727     if (host->cmd == NULL && host->data == NULL) {
0728         status = OMAP_MMC_READ(host, STAT);
0729         dev_info(mmc_dev(host->slots[0]->mmc),
0730              "Spurious IRQ 0x%04x\n", status);
0731         if (status != 0) {
0732             OMAP_MMC_WRITE(host, STAT, status);
0733             OMAP_MMC_WRITE(host, IE, 0);
0734         }
0735         return IRQ_HANDLED;
0736     }
0737 
0738     end_command = 0;
0739     end_transfer = 0;
0740     transfer_error = 0;
0741     cmd_error = 0;
0742 
0743     while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
0744         int cmd;
0745 
0746         OMAP_MMC_WRITE(host, STAT, status);
0747         if (host->cmd != NULL)
0748             cmd = host->cmd->opcode;
0749         else
0750             cmd = -1;
0751         dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
0752             status, cmd);
0753         mmc_omap_report_irq(host, status);
0754 
0755         if (host->total_bytes_left) {
0756             if ((status & OMAP_MMC_STAT_A_FULL) ||
0757                 (status & OMAP_MMC_STAT_END_OF_DATA))
0758                 mmc_omap_xfer_data(host, 0);
0759             if (status & OMAP_MMC_STAT_A_EMPTY)
0760                 mmc_omap_xfer_data(host, 1);
0761         }
0762 
0763         if (status & OMAP_MMC_STAT_END_OF_DATA)
0764             end_transfer = 1;
0765 
0766         if (status & OMAP_MMC_STAT_DATA_TOUT) {
0767             dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
0768                 cmd);
0769             if (host->data) {
0770                 host->data->error = -ETIMEDOUT;
0771                 transfer_error = 1;
0772             }
0773         }
0774 
0775         if (status & OMAP_MMC_STAT_DATA_CRC) {
0776             if (host->data) {
0777                 host->data->error = -EILSEQ;
0778                 dev_dbg(mmc_dev(host->mmc),
0779                      "data CRC error, bytes left %d\n",
0780                     host->total_bytes_left);
0781                 transfer_error = 1;
0782             } else {
0783                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
0784             }
0785         }
0786 
0787         if (status & OMAP_MMC_STAT_CMD_TOUT) {
0788             /* Timeouts are routine with some commands */
0789             if (host->cmd) {
0790                 struct mmc_omap_slot *slot =
0791                     host->current_slot;
0792                 if (slot == NULL ||
0793                     !mmc_omap_cover_is_open(slot))
0794                     dev_err(mmc_dev(host->mmc),
0795                         "command timeout (CMD%d)\n",
0796                         cmd);
0797                 host->cmd->error = -ETIMEDOUT;
0798                 end_command = 1;
0799                 cmd_error = 1;
0800             }
0801         }
0802 
0803         if (status & OMAP_MMC_STAT_CMD_CRC) {
0804             if (host->cmd) {
0805                 dev_err(mmc_dev(host->mmc),
0806                     "command CRC error (CMD%d, arg 0x%08x)\n",
0807                     cmd, host->cmd->arg);
0808                 host->cmd->error = -EILSEQ;
0809                 end_command = 1;
0810                 cmd_error = 1;
0811             } else
0812                 dev_err(mmc_dev(host->mmc),
0813                     "command CRC error without cmd?\n");
0814         }
0815 
0816         if (status & OMAP_MMC_STAT_CARD_ERR) {
0817             dev_dbg(mmc_dev(host->mmc),
0818                 "ignoring card status error (CMD%d)\n",
0819                 cmd);
0820             end_command = 1;
0821         }
0822 
0823         /*
0824          * NOTE: On 1610 the END_OF_CMD may come too early when
0825          * starting a write
0826          */
0827         if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
0828             (!(status & OMAP_MMC_STAT_A_EMPTY))) {
0829             end_command = 1;
0830         }
0831     }
0832 
0833     if (cmd_error && host->data) {
0834         del_timer(&host->cmd_abort_timer);
0835         host->abort = 1;
0836         OMAP_MMC_WRITE(host, IE, 0);
0837         disable_irq_nosync(host->irq);
0838         queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
0839         return IRQ_HANDLED;
0840     }
0841 
0842     if (end_command && host->cmd)
0843         mmc_omap_cmd_done(host, host->cmd);
0844     if (host->data != NULL) {
0845         if (transfer_error)
0846             mmc_omap_xfer_done(host, host->data);
0847         else if (end_transfer)
0848             mmc_omap_end_of_data(host, host->data);
0849     }
0850 
0851     return IRQ_HANDLED;
0852 }
0853 
0854 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
0855 {
0856     int cover_open;
0857     struct mmc_omap_host *host = dev_get_drvdata(dev);
0858     struct mmc_omap_slot *slot = host->slots[num];
0859 
0860     BUG_ON(num >= host->nr_slots);
0861 
0862     /* Other subsystems can call in here before we're initialised. */
0863     if (host->nr_slots == 0 || !host->slots[num])
0864         return;
0865 
0866     cover_open = mmc_omap_cover_is_open(slot);
0867     if (cover_open != slot->cover_open) {
0868         slot->cover_open = cover_open;
0869         sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
0870     }
0871 
0872     tasklet_hi_schedule(&slot->cover_tasklet);
0873 }
0874 
0875 static void mmc_omap_cover_timer(struct timer_list *t)
0876 {
0877     struct mmc_omap_slot *slot = from_timer(slot, t, cover_timer);
0878     tasklet_schedule(&slot->cover_tasklet);
0879 }
0880 
0881 static void mmc_omap_cover_handler(struct tasklet_struct *t)
0882 {
0883     struct mmc_omap_slot *slot = from_tasklet(slot, t, cover_tasklet);
0884     int cover_open = mmc_omap_cover_is_open(slot);
0885 
0886     mmc_detect_change(slot->mmc, 0);
0887     if (!cover_open)
0888         return;
0889 
0890     /*
0891      * If no card is inserted, we postpone polling until
0892      * the cover has been closed.
0893      */
0894     if (slot->mmc->card == NULL)
0895         return;
0896 
0897     mod_timer(&slot->cover_timer,
0898           jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
0899 }
0900 
0901 static void mmc_omap_dma_callback(void *priv)
0902 {
0903     struct mmc_omap_host *host = priv;
0904     struct mmc_data *data = host->data;
0905 
0906     /* If we got to the end of DMA, assume everything went well */
0907     data->bytes_xfered += data->blocks * data->blksz;
0908 
0909     mmc_omap_dma_done(host, data);
0910 }
0911 
0912 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
0913 {
0914     u16 reg;
0915 
0916     reg = OMAP_MMC_READ(host, SDIO);
0917     reg &= ~(1 << 5);
0918     OMAP_MMC_WRITE(host, SDIO, reg);
0919     /* Set maximum timeout */
0920     OMAP_MMC_WRITE(host, CTO, 0xfd);
0921 }
0922 
0923 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
0924 {
0925     unsigned int timeout, cycle_ns;
0926     u16 reg;
0927 
0928     cycle_ns = 1000000000 / host->current_slot->fclk_freq;
0929     timeout = req->data->timeout_ns / cycle_ns;
0930     timeout += req->data->timeout_clks;
0931 
0932     /* Check if we need to use timeout multiplier register */
0933     reg = OMAP_MMC_READ(host, SDIO);
0934     if (timeout > 0xffff) {
0935         reg |= (1 << 5);
0936         timeout /= 1024;
0937     } else
0938         reg &= ~(1 << 5);
0939     OMAP_MMC_WRITE(host, SDIO, reg);
0940     OMAP_MMC_WRITE(host, DTO, timeout);
0941 }
0942 
0943 static void
0944 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
0945 {
0946     struct mmc_data *data = req->data;
0947     int i, use_dma = 1, block_size;
0948     struct scatterlist *sg;
0949     unsigned sg_len;
0950 
0951     host->data = data;
0952     if (data == NULL) {
0953         OMAP_MMC_WRITE(host, BLEN, 0);
0954         OMAP_MMC_WRITE(host, NBLK, 0);
0955         OMAP_MMC_WRITE(host, BUF, 0);
0956         host->dma_in_use = 0;
0957         set_cmd_timeout(host, req);
0958         return;
0959     }
0960 
0961     block_size = data->blksz;
0962 
0963     OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
0964     OMAP_MMC_WRITE(host, BLEN, block_size - 1);
0965     set_data_timeout(host, req);
0966 
0967     /* cope with calling layer confusion; it issues "single
0968      * block" writes using multi-block scatterlists.
0969      */
0970     sg_len = (data->blocks == 1) ? 1 : data->sg_len;
0971 
0972     /* Only do DMA for entire blocks */
0973     for_each_sg(data->sg, sg, sg_len, i) {
0974         if ((sg->length % block_size) != 0) {
0975             use_dma = 0;
0976             break;
0977         }
0978     }
0979 
0980     host->sg_idx = 0;
0981     if (use_dma) {
0982         enum dma_data_direction dma_data_dir;
0983         struct dma_async_tx_descriptor *tx;
0984         struct dma_chan *c;
0985         u32 burst, *bp;
0986         u16 buf;
0987 
0988         /*
0989          * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
0990          * and 24xx. Use 16 or 32 word frames when the
0991          * blocksize is at least that large. Blocksize is
0992          * usually 512 bytes; but not for some SD reads.
0993          */
0994         burst = mmc_omap15xx() ? 32 : 64;
0995         if (burst > data->blksz)
0996             burst = data->blksz;
0997 
0998         burst >>= 1;
0999 
1000         if (data->flags & MMC_DATA_WRITE) {
1001             c = host->dma_tx;
1002             bp = &host->dma_tx_burst;
1003             buf = 0x0f80 | (burst - 1) << 0;
1004             dma_data_dir = DMA_TO_DEVICE;
1005         } else {
1006             c = host->dma_rx;
1007             bp = &host->dma_rx_burst;
1008             buf = 0x800f | (burst - 1) << 8;
1009             dma_data_dir = DMA_FROM_DEVICE;
1010         }
1011 
1012         if (!c)
1013             goto use_pio;
1014 
1015         /* Only reconfigure if we have a different burst size */
1016         if (*bp != burst) {
1017             struct dma_slave_config cfg = {
1018                 .src_addr = host->phys_base +
1019                         OMAP_MMC_REG(host, DATA),
1020                 .dst_addr = host->phys_base +
1021                         OMAP_MMC_REG(host, DATA),
1022                 .src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
1023                 .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
1024                 .src_maxburst = burst,
1025                 .dst_maxburst = burst,
1026             };
1027 
1028             if (dmaengine_slave_config(c, &cfg))
1029                 goto use_pio;
1030 
1031             *bp = burst;
1032         }
1033 
1034         host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1035                       dma_data_dir);
1036         if (host->sg_len == 0)
1037             goto use_pio;
1038 
1039         tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1040             data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1041             DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1042         if (!tx)
1043             goto use_pio;
1044 
1045         OMAP_MMC_WRITE(host, BUF, buf);
1046 
1047         tx->callback = mmc_omap_dma_callback;
1048         tx->callback_param = host;
1049         dmaengine_submit(tx);
1050         host->brs_received = 0;
1051         host->dma_done = 0;
1052         host->dma_in_use = 1;
1053         return;
1054     }
1055  use_pio:
1056 
1057     /* Revert to PIO? */
1058     OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1059     host->total_bytes_left = data->blocks * block_size;
1060     host->sg_len = sg_len;
1061     mmc_omap_sg_to_buf(host);
1062     host->dma_in_use = 0;
1063 }
1064 
1065 static void mmc_omap_start_request(struct mmc_omap_host *host,
1066                    struct mmc_request *req)
1067 {
1068     BUG_ON(host->mrq != NULL);
1069 
1070     host->mrq = req;
1071 
1072     /* only touch fifo AFTER the controller readies it */
1073     mmc_omap_prepare_data(host, req);
1074     mmc_omap_start_command(host, req->cmd);
1075     if (host->dma_in_use) {
1076         struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1077                 host->dma_tx : host->dma_rx;
1078 
1079         dma_async_issue_pending(c);
1080     }
1081 }
1082 
1083 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1084 {
1085     struct mmc_omap_slot *slot = mmc_priv(mmc);
1086     struct mmc_omap_host *host = slot->host;
1087     unsigned long flags;
1088 
1089     spin_lock_irqsave(&host->slot_lock, flags);
1090     if (host->mmc != NULL) {
1091         BUG_ON(slot->mrq != NULL);
1092         slot->mrq = req;
1093         spin_unlock_irqrestore(&host->slot_lock, flags);
1094         return;
1095     } else
1096         host->mmc = mmc;
1097     spin_unlock_irqrestore(&host->slot_lock, flags);
1098     mmc_omap_select_slot(slot, 1);
1099     mmc_omap_start_request(host, req);
1100 }
1101 
1102 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1103                 int vdd)
1104 {
1105     struct mmc_omap_host *host;
1106 
1107     host = slot->host;
1108 
1109     if (slot->pdata->set_power != NULL)
1110         slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1111                     vdd);
1112     if (mmc_omap2()) {
1113         u16 w;
1114 
1115         if (power_on) {
1116             w = OMAP_MMC_READ(host, CON);
1117             OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1118         } else {
1119             w = OMAP_MMC_READ(host, CON);
1120             OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1121         }
1122     }
1123 }
1124 
1125 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1126 {
1127     struct mmc_omap_slot *slot = mmc_priv(mmc);
1128     struct mmc_omap_host *host = slot->host;
1129     int func_clk_rate = clk_get_rate(host->fclk);
1130     int dsor;
1131 
1132     if (ios->clock == 0)
1133         return 0;
1134 
1135     dsor = func_clk_rate / ios->clock;
1136     if (dsor < 1)
1137         dsor = 1;
1138 
1139     if (func_clk_rate / dsor > ios->clock)
1140         dsor++;
1141 
1142     if (dsor > 250)
1143         dsor = 250;
1144 
1145     slot->fclk_freq = func_clk_rate / dsor;
1146 
1147     if (ios->bus_width == MMC_BUS_WIDTH_4)
1148         dsor |= 1 << 15;
1149 
1150     return dsor;
1151 }
1152 
1153 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1154 {
1155     struct mmc_omap_slot *slot = mmc_priv(mmc);
1156     struct mmc_omap_host *host = slot->host;
1157     int i, dsor;
1158     int clk_enabled, init_stream;
1159 
1160     mmc_omap_select_slot(slot, 0);
1161 
1162     dsor = mmc_omap_calc_divisor(mmc, ios);
1163 
1164     if (ios->vdd != slot->vdd)
1165         slot->vdd = ios->vdd;
1166 
1167     clk_enabled = 0;
1168     init_stream = 0;
1169     switch (ios->power_mode) {
1170     case MMC_POWER_OFF:
1171         mmc_omap_set_power(slot, 0, ios->vdd);
1172         break;
1173     case MMC_POWER_UP:
1174         /* Cannot touch dsor yet, just power up MMC */
1175         mmc_omap_set_power(slot, 1, ios->vdd);
1176         slot->power_mode = ios->power_mode;
1177         goto exit;
1178     case MMC_POWER_ON:
1179         mmc_omap_fclk_enable(host, 1);
1180         clk_enabled = 1;
1181         dsor |= 1 << 11;
1182         if (slot->power_mode != MMC_POWER_ON)
1183             init_stream = 1;
1184         break;
1185     }
1186     slot->power_mode = ios->power_mode;
1187 
1188     if (slot->bus_mode != ios->bus_mode) {
1189         if (slot->pdata->set_bus_mode != NULL)
1190             slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1191                           ios->bus_mode);
1192         slot->bus_mode = ios->bus_mode;
1193     }
1194 
1195     /* On insanely high arm_per frequencies something sometimes
1196      * goes somehow out of sync, and the POW bit is not being set,
1197      * which results in the while loop below getting stuck.
1198      * Writing to the CON register twice seems to do the trick. */
1199     for (i = 0; i < 2; i++)
1200         OMAP_MMC_WRITE(host, CON, dsor);
1201     slot->saved_con = dsor;
1202     if (init_stream) {
1203         /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1204         int usecs = 250;
1205 
1206         /* Send clock cycles, poll completion */
1207         OMAP_MMC_WRITE(host, IE, 0);
1208         OMAP_MMC_WRITE(host, STAT, 0xffff);
1209         OMAP_MMC_WRITE(host, CMD, 1 << 7);
1210         while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1211             udelay(1);
1212             usecs--;
1213         }
1214         OMAP_MMC_WRITE(host, STAT, 1);
1215     }
1216 
1217 exit:
1218     mmc_omap_release_slot(slot, clk_enabled);
1219 }
1220 
1221 static const struct mmc_host_ops mmc_omap_ops = {
1222     .request    = mmc_omap_request,
1223     .set_ios    = mmc_omap_set_ios,
1224 };
1225 
1226 static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1227 {
1228     struct mmc_omap_slot *slot = NULL;
1229     struct mmc_host *mmc;
1230     int r;
1231 
1232     mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1233     if (mmc == NULL)
1234         return -ENOMEM;
1235 
1236     slot = mmc_priv(mmc);
1237     slot->host = host;
1238     slot->mmc = mmc;
1239     slot->id = id;
1240     slot->power_mode = MMC_POWER_UNDEFINED;
1241     slot->pdata = &host->pdata->slots[id];
1242 
1243     host->slots[id] = slot;
1244 
1245     mmc->caps = 0;
1246     if (host->pdata->slots[id].wires >= 4)
1247         mmc->caps |= MMC_CAP_4_BIT_DATA;
1248 
1249     mmc->ops = &mmc_omap_ops;
1250     mmc->f_min = 400000;
1251 
1252     if (mmc_omap2())
1253         mmc->f_max = 48000000;
1254     else
1255         mmc->f_max = 24000000;
1256     if (host->pdata->max_freq)
1257         mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1258     mmc->ocr_avail = slot->pdata->ocr_mask;
1259 
1260     /* Use scatterlist DMA to reduce per-transfer costs.
1261      * NOTE max_seg_size assumption that small blocks aren't
1262      * normally used (except e.g. for reading SD registers).
1263      */
1264     mmc->max_segs = 32;
1265     mmc->max_blk_size = 2048;   /* BLEN is 11 bits (+1) */
1266     mmc->max_blk_count = 2048;  /* NBLK is 11 bits (+1) */
1267     mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1268     mmc->max_seg_size = mmc->max_req_size;
1269 
1270     if (slot->pdata->get_cover_state != NULL) {
1271         timer_setup(&slot->cover_timer, mmc_omap_cover_timer, 0);
1272         tasklet_setup(&slot->cover_tasklet, mmc_omap_cover_handler);
1273     }
1274 
1275     r = mmc_add_host(mmc);
1276     if (r < 0)
1277         goto err_remove_host;
1278 
1279     if (slot->pdata->name != NULL) {
1280         r = device_create_file(&mmc->class_dev,
1281                     &dev_attr_slot_name);
1282         if (r < 0)
1283             goto err_remove_host;
1284     }
1285 
1286     if (slot->pdata->get_cover_state != NULL) {
1287         r = device_create_file(&mmc->class_dev,
1288                     &dev_attr_cover_switch);
1289         if (r < 0)
1290             goto err_remove_slot_name;
1291         tasklet_schedule(&slot->cover_tasklet);
1292     }
1293 
1294     return 0;
1295 
1296 err_remove_slot_name:
1297     if (slot->pdata->name != NULL)
1298         device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1299 err_remove_host:
1300     mmc_remove_host(mmc);
1301     mmc_free_host(mmc);
1302     return r;
1303 }
1304 
1305 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1306 {
1307     struct mmc_host *mmc = slot->mmc;
1308 
1309     if (slot->pdata->name != NULL)
1310         device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1311     if (slot->pdata->get_cover_state != NULL)
1312         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1313 
1314     tasklet_kill(&slot->cover_tasklet);
1315     del_timer_sync(&slot->cover_timer);
1316     flush_workqueue(slot->host->mmc_omap_wq);
1317 
1318     mmc_remove_host(mmc);
1319     mmc_free_host(mmc);
1320 }
1321 
1322 static int mmc_omap_probe(struct platform_device *pdev)
1323 {
1324     struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1325     struct mmc_omap_host *host = NULL;
1326     struct resource *res;
1327     int i, ret = 0;
1328     int irq;
1329 
1330     if (pdata == NULL) {
1331         dev_err(&pdev->dev, "platform data missing\n");
1332         return -ENXIO;
1333     }
1334     if (pdata->nr_slots == 0) {
1335         dev_err(&pdev->dev, "no slots\n");
1336         return -EPROBE_DEFER;
1337     }
1338 
1339     host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host),
1340                 GFP_KERNEL);
1341     if (host == NULL)
1342         return -ENOMEM;
1343 
1344     irq = platform_get_irq(pdev, 0);
1345     if (irq < 0)
1346         return -ENXIO;
1347 
1348     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1349     host->virt_base = devm_ioremap_resource(&pdev->dev, res);
1350     if (IS_ERR(host->virt_base))
1351         return PTR_ERR(host->virt_base);
1352 
1353     INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1354     INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1355 
1356     INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1357     timer_setup(&host->cmd_abort_timer, mmc_omap_cmd_timer, 0);
1358 
1359     spin_lock_init(&host->clk_lock);
1360     timer_setup(&host->clk_timer, mmc_omap_clk_timer, 0);
1361 
1362     spin_lock_init(&host->dma_lock);
1363     spin_lock_init(&host->slot_lock);
1364     init_waitqueue_head(&host->slot_wq);
1365 
1366     host->pdata = pdata;
1367     host->features = host->pdata->slots[0].features;
1368     host->dev = &pdev->dev;
1369     platform_set_drvdata(pdev, host);
1370 
1371     host->id = pdev->id;
1372     host->irq = irq;
1373     host->phys_base = res->start;
1374     host->iclk = clk_get(&pdev->dev, "ick");
1375     if (IS_ERR(host->iclk))
1376         return PTR_ERR(host->iclk);
1377     clk_prepare_enable(host->iclk);
1378 
1379     host->fclk = clk_get(&pdev->dev, "fck");
1380     if (IS_ERR(host->fclk)) {
1381         ret = PTR_ERR(host->fclk);
1382         goto err_free_iclk;
1383     }
1384 
1385     ret = clk_prepare(host->fclk);
1386     if (ret)
1387         goto err_put_fclk;
1388 
1389     host->dma_tx_burst = -1;
1390     host->dma_rx_burst = -1;
1391 
1392     host->dma_tx = dma_request_chan(&pdev->dev, "tx");
1393     if (IS_ERR(host->dma_tx)) {
1394         ret = PTR_ERR(host->dma_tx);
1395         if (ret == -EPROBE_DEFER)
1396             goto err_free_fclk;
1397 
1398         host->dma_tx = NULL;
1399         dev_warn(host->dev, "TX DMA channel request failed\n");
1400     }
1401 
1402     host->dma_rx = dma_request_chan(&pdev->dev, "rx");
1403     if (IS_ERR(host->dma_rx)) {
1404         ret = PTR_ERR(host->dma_rx);
1405         if (ret == -EPROBE_DEFER) {
1406             if (host->dma_tx)
1407                 dma_release_channel(host->dma_tx);
1408             goto err_free_fclk;
1409         }
1410 
1411         host->dma_rx = NULL;
1412         dev_warn(host->dev, "RX DMA channel request failed\n");
1413     }
1414 
1415     ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1416     if (ret)
1417         goto err_free_dma;
1418 
1419     if (pdata->init != NULL) {
1420         ret = pdata->init(&pdev->dev);
1421         if (ret < 0)
1422             goto err_free_irq;
1423     }
1424 
1425     host->nr_slots = pdata->nr_slots;
1426     host->reg_shift = (mmc_omap7xx() ? 1 : 2);
1427 
1428     host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1429     if (!host->mmc_omap_wq) {
1430         ret = -ENOMEM;
1431         goto err_plat_cleanup;
1432     }
1433 
1434     for (i = 0; i < pdata->nr_slots; i++) {
1435         ret = mmc_omap_new_slot(host, i);
1436         if (ret < 0) {
1437             while (--i >= 0)
1438                 mmc_omap_remove_slot(host->slots[i]);
1439 
1440             goto err_destroy_wq;
1441         }
1442     }
1443 
1444     return 0;
1445 
1446 err_destroy_wq:
1447     destroy_workqueue(host->mmc_omap_wq);
1448 err_plat_cleanup:
1449     if (pdata->cleanup)
1450         pdata->cleanup(&pdev->dev);
1451 err_free_irq:
1452     free_irq(host->irq, host);
1453 err_free_dma:
1454     if (host->dma_tx)
1455         dma_release_channel(host->dma_tx);
1456     if (host->dma_rx)
1457         dma_release_channel(host->dma_rx);
1458 err_free_fclk:
1459     clk_unprepare(host->fclk);
1460 err_put_fclk:
1461     clk_put(host->fclk);
1462 err_free_iclk:
1463     clk_disable_unprepare(host->iclk);
1464     clk_put(host->iclk);
1465     return ret;
1466 }
1467 
1468 static int mmc_omap_remove(struct platform_device *pdev)
1469 {
1470     struct mmc_omap_host *host = platform_get_drvdata(pdev);
1471     int i;
1472 
1473     BUG_ON(host == NULL);
1474 
1475     for (i = 0; i < host->nr_slots; i++)
1476         mmc_omap_remove_slot(host->slots[i]);
1477 
1478     if (host->pdata->cleanup)
1479         host->pdata->cleanup(&pdev->dev);
1480 
1481     mmc_omap_fclk_enable(host, 0);
1482     free_irq(host->irq, host);
1483     clk_unprepare(host->fclk);
1484     clk_put(host->fclk);
1485     clk_disable_unprepare(host->iclk);
1486     clk_put(host->iclk);
1487 
1488     if (host->dma_tx)
1489         dma_release_channel(host->dma_tx);
1490     if (host->dma_rx)
1491         dma_release_channel(host->dma_rx);
1492 
1493     destroy_workqueue(host->mmc_omap_wq);
1494 
1495     return 0;
1496 }
1497 
1498 #if IS_BUILTIN(CONFIG_OF)
1499 static const struct of_device_id mmc_omap_match[] = {
1500     { .compatible = "ti,omap2420-mmc", },
1501     { },
1502 };
1503 MODULE_DEVICE_TABLE(of, mmc_omap_match);
1504 #endif
1505 
1506 static struct platform_driver mmc_omap_driver = {
1507     .probe      = mmc_omap_probe,
1508     .remove     = mmc_omap_remove,
1509     .driver     = {
1510         .name   = DRIVER_NAME,
1511         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1512         .of_match_table = of_match_ptr(mmc_omap_match),
1513     },
1514 };
1515 
1516 module_platform_driver(mmc_omap_driver);
1517 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1518 MODULE_LICENSE("GPL");
1519 MODULE_ALIAS("platform:" DRIVER_NAME);
1520 MODULE_AUTHOR("Juha Yrjölä");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!