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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
0004  *
0005  *  This is a driver for the SDHC controller found in Freescale MX2/MX3
0006  *  SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
0007  *  Unlike the hardware found on MX1, this hardware just works and does
0008  *  not need all the quirks found in imxmmc.c, hence the separate driver.
0009  *
0010  *  Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
0011  *  Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
0012  *
0013  *  derived from pxamci.c by Russell King
0014  */
0015 
0016 #include <linux/module.h>
0017 #include <linux/init.h>
0018 #include <linux/ioport.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/highmem.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/irq.h>
0023 #include <linux/blkdev.h>
0024 #include <linux/dma-mapping.h>
0025 #include <linux/mmc/host.h>
0026 #include <linux/mmc/card.h>
0027 #include <linux/delay.h>
0028 #include <linux/clk.h>
0029 #include <linux/io.h>
0030 #include <linux/regulator/consumer.h>
0031 #include <linux/dmaengine.h>
0032 #include <linux/types.h>
0033 #include <linux/of.h>
0034 #include <linux/of_device.h>
0035 #include <linux/of_dma.h>
0036 #include <linux/mmc/slot-gpio.h>
0037 
0038 #include <asm/dma.h>
0039 #include <asm/irq.h>
0040 #include <linux/platform_data/mmc-mxcmmc.h>
0041 
0042 #include <linux/dma/imx-dma.h>
0043 
0044 #define DRIVER_NAME "mxc-mmc"
0045 #define MXCMCI_TIMEOUT_MS 10000
0046 
0047 #define MMC_REG_STR_STP_CLK     0x00
0048 #define MMC_REG_STATUS          0x04
0049 #define MMC_REG_CLK_RATE        0x08
0050 #define MMC_REG_CMD_DAT_CONT        0x0C
0051 #define MMC_REG_RES_TO          0x10
0052 #define MMC_REG_READ_TO         0x14
0053 #define MMC_REG_BLK_LEN         0x18
0054 #define MMC_REG_NOB         0x1C
0055 #define MMC_REG_REV_NO          0x20
0056 #define MMC_REG_INT_CNTR        0x24
0057 #define MMC_REG_CMD         0x28
0058 #define MMC_REG_ARG         0x2C
0059 #define MMC_REG_RES_FIFO        0x34
0060 #define MMC_REG_BUFFER_ACCESS       0x38
0061 
0062 #define STR_STP_CLK_RESET               (1 << 3)
0063 #define STR_STP_CLK_START_CLK           (1 << 1)
0064 #define STR_STP_CLK_STOP_CLK            (1 << 0)
0065 
0066 #define STATUS_CARD_INSERTION       (1 << 31)
0067 #define STATUS_CARD_REMOVAL     (1 << 30)
0068 #define STATUS_YBUF_EMPTY       (1 << 29)
0069 #define STATUS_XBUF_EMPTY       (1 << 28)
0070 #define STATUS_YBUF_FULL        (1 << 27)
0071 #define STATUS_XBUF_FULL        (1 << 26)
0072 #define STATUS_BUF_UND_RUN      (1 << 25)
0073 #define STATUS_BUF_OVFL         (1 << 24)
0074 #define STATUS_SDIO_INT_ACTIVE      (1 << 14)
0075 #define STATUS_END_CMD_RESP     (1 << 13)
0076 #define STATUS_WRITE_OP_DONE        (1 << 12)
0077 #define STATUS_DATA_TRANS_DONE      (1 << 11)
0078 #define STATUS_READ_OP_DONE     (1 << 11)
0079 #define STATUS_WR_CRC_ERROR_CODE_MASK   (3 << 10)
0080 #define STATUS_CARD_BUS_CLK_RUN     (1 << 8)
0081 #define STATUS_BUF_READ_RDY     (1 << 7)
0082 #define STATUS_BUF_WRITE_RDY        (1 << 6)
0083 #define STATUS_RESP_CRC_ERR     (1 << 5)
0084 #define STATUS_CRC_READ_ERR     (1 << 3)
0085 #define STATUS_CRC_WRITE_ERR        (1 << 2)
0086 #define STATUS_TIME_OUT_RESP        (1 << 1)
0087 #define STATUS_TIME_OUT_READ        (1 << 0)
0088 #define STATUS_ERR_MASK         0x2f
0089 
0090 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF  (1 << 12)
0091 #define CMD_DAT_CONT_STOP_READWAIT  (1 << 11)
0092 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
0093 #define CMD_DAT_CONT_BUS_WIDTH_4    (2 << 8)
0094 #define CMD_DAT_CONT_INIT       (1 << 7)
0095 #define CMD_DAT_CONT_WRITE      (1 << 4)
0096 #define CMD_DAT_CONT_DATA_ENABLE    (1 << 3)
0097 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
0098 #define CMD_DAT_CONT_RESPONSE_136BIT    (2 << 0)
0099 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
0100 
0101 #define INT_SDIO_INT_WKP_EN     (1 << 18)
0102 #define INT_CARD_INSERTION_WKP_EN   (1 << 17)
0103 #define INT_CARD_REMOVAL_WKP_EN     (1 << 16)
0104 #define INT_CARD_INSERTION_EN       (1 << 15)
0105 #define INT_CARD_REMOVAL_EN     (1 << 14)
0106 #define INT_SDIO_IRQ_EN         (1 << 13)
0107 #define INT_DAT0_EN         (1 << 12)
0108 #define INT_BUF_READ_EN         (1 << 4)
0109 #define INT_BUF_WRITE_EN        (1 << 3)
0110 #define INT_END_CMD_RES_EN      (1 << 2)
0111 #define INT_WRITE_OP_DONE_EN        (1 << 1)
0112 #define INT_READ_OP_EN          (1 << 0)
0113 
0114 enum mxcmci_type {
0115     IMX21_MMC,
0116     IMX31_MMC,
0117     MPC512X_MMC,
0118 };
0119 
0120 struct mxcmci_host {
0121     struct mmc_host     *mmc;
0122     void __iomem        *base;
0123     dma_addr_t      phys_base;
0124     int         detect_irq;
0125     struct dma_chan     *dma;
0126     struct dma_async_tx_descriptor *desc;
0127     int         do_dma;
0128     int         default_irq_mask;
0129     int         use_sdio;
0130     unsigned int        power_mode;
0131     struct imxmmc_platform_data *pdata;
0132 
0133     struct mmc_request  *req;
0134     struct mmc_command  *cmd;
0135     struct mmc_data     *data;
0136 
0137     unsigned int        datasize;
0138     unsigned int        dma_dir;
0139 
0140     u16         rev_no;
0141     unsigned int        cmdat;
0142 
0143     struct clk      *clk_ipg;
0144     struct clk      *clk_per;
0145 
0146     int         clock;
0147 
0148     struct work_struct  datawork;
0149     spinlock_t      lock;
0150 
0151     int         burstlen;
0152     int         dmareq;
0153     struct dma_slave_config dma_slave_config;
0154     struct imx_dma_data dma_data;
0155 
0156     struct timer_list   watchdog;
0157     enum mxcmci_type    devtype;
0158 };
0159 
0160 static const struct of_device_id mxcmci_of_match[] = {
0161     {
0162         .compatible = "fsl,imx21-mmc",
0163         .data = (void *) IMX21_MMC,
0164     }, {
0165         .compatible = "fsl,imx31-mmc",
0166         .data = (void *) IMX31_MMC,
0167     }, {
0168         .compatible = "fsl,mpc5121-sdhc",
0169         .data = (void *) MPC512X_MMC,
0170     }, {
0171         /* sentinel */
0172     }
0173 };
0174 MODULE_DEVICE_TABLE(of, mxcmci_of_match);
0175 
0176 static inline int is_imx31_mmc(struct mxcmci_host *host)
0177 {
0178     return host->devtype == IMX31_MMC;
0179 }
0180 
0181 static inline int is_mpc512x_mmc(struct mxcmci_host *host)
0182 {
0183     return host->devtype == MPC512X_MMC;
0184 }
0185 
0186 static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg)
0187 {
0188     if (IS_ENABLED(CONFIG_PPC_MPC512x))
0189         return ioread32be(host->base + reg);
0190     else
0191         return readl(host->base + reg);
0192 }
0193 
0194 static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg)
0195 {
0196     if (IS_ENABLED(CONFIG_PPC_MPC512x))
0197         iowrite32be(val, host->base + reg);
0198     else
0199         writel(val, host->base + reg);
0200 }
0201 
0202 static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg)
0203 {
0204     if (IS_ENABLED(CONFIG_PPC_MPC512x))
0205         return ioread32be(host->base + reg);
0206     else
0207         return readw(host->base + reg);
0208 }
0209 
0210 static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg)
0211 {
0212     if (IS_ENABLED(CONFIG_PPC_MPC512x))
0213         iowrite32be(val, host->base + reg);
0214     else
0215         writew(val, host->base + reg);
0216 }
0217 
0218 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
0219 
0220 static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd)
0221 {
0222     if (!IS_ERR(host->mmc->supply.vmmc)) {
0223         if (host->power_mode == MMC_POWER_UP)
0224             mmc_regulator_set_ocr(host->mmc,
0225                           host->mmc->supply.vmmc, vdd);
0226         else if (host->power_mode == MMC_POWER_OFF)
0227             mmc_regulator_set_ocr(host->mmc,
0228                           host->mmc->supply.vmmc, 0);
0229     }
0230 
0231     if (host->pdata && host->pdata->setpower)
0232         host->pdata->setpower(mmc_dev(host->mmc), vdd);
0233 }
0234 
0235 static inline int mxcmci_use_dma(struct mxcmci_host *host)
0236 {
0237     return host->do_dma;
0238 }
0239 
0240 static void mxcmci_softreset(struct mxcmci_host *host)
0241 {
0242     int i;
0243 
0244     dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
0245 
0246     /* reset sequence */
0247     mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK);
0248     mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
0249             MMC_REG_STR_STP_CLK);
0250 
0251     for (i = 0; i < 8; i++)
0252         mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
0253 
0254     mxcmci_writew(host, 0xff, MMC_REG_RES_TO);
0255 }
0256 
0257 #if IS_ENABLED(CONFIG_PPC_MPC512x)
0258 static inline void buffer_swap32(u32 *buf, int len)
0259 {
0260     int i;
0261 
0262     for (i = 0; i < ((len + 3) / 4); i++) {
0263         *buf = swab32(*buf);
0264         buf++;
0265     }
0266 }
0267 
0268 static void mxcmci_swap_buffers(struct mmc_data *data)
0269 {
0270     struct scatterlist *sg;
0271     int i;
0272 
0273     for_each_sg(data->sg, sg, data->sg_len, i)
0274         buffer_swap32(sg_virt(sg), sg->length);
0275 }
0276 #else
0277 static inline void mxcmci_swap_buffers(struct mmc_data *data) {}
0278 #endif
0279 
0280 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
0281 {
0282     unsigned int nob = data->blocks;
0283     unsigned int blksz = data->blksz;
0284     unsigned int datasize = nob * blksz;
0285     struct scatterlist *sg;
0286     enum dma_transfer_direction slave_dirn;
0287     int i, nents;
0288 
0289     host->data = data;
0290     data->bytes_xfered = 0;
0291 
0292     mxcmci_writew(host, nob, MMC_REG_NOB);
0293     mxcmci_writew(host, blksz, MMC_REG_BLK_LEN);
0294     host->datasize = datasize;
0295 
0296     if (!mxcmci_use_dma(host))
0297         return 0;
0298 
0299     for_each_sg(data->sg, sg, data->sg_len, i) {
0300         if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
0301             host->do_dma = 0;
0302             return 0;
0303         }
0304     }
0305 
0306     if (data->flags & MMC_DATA_READ) {
0307         host->dma_dir = DMA_FROM_DEVICE;
0308         slave_dirn = DMA_DEV_TO_MEM;
0309     } else {
0310         host->dma_dir = DMA_TO_DEVICE;
0311         slave_dirn = DMA_MEM_TO_DEV;
0312 
0313         mxcmci_swap_buffers(data);
0314     }
0315 
0316     nents = dma_map_sg(host->dma->device->dev, data->sg,
0317                      data->sg_len,  host->dma_dir);
0318     if (nents != data->sg_len)
0319         return -EINVAL;
0320 
0321     host->desc = dmaengine_prep_slave_sg(host->dma,
0322         data->sg, data->sg_len, slave_dirn,
0323         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0324 
0325     if (!host->desc) {
0326         dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
0327                 host->dma_dir);
0328         host->do_dma = 0;
0329         return 0; /* Fall back to PIO */
0330     }
0331     wmb();
0332 
0333     dmaengine_submit(host->desc);
0334     dma_async_issue_pending(host->dma);
0335 
0336     mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
0337 
0338     return 0;
0339 }
0340 
0341 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
0342 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
0343 
0344 static void mxcmci_dma_callback(void *data)
0345 {
0346     struct mxcmci_host *host = data;
0347     u32 stat;
0348 
0349     del_timer(&host->watchdog);
0350 
0351     stat = mxcmci_readl(host, MMC_REG_STATUS);
0352 
0353     dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
0354 
0355     mxcmci_data_done(host, stat);
0356 }
0357 
0358 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
0359         unsigned int cmdat)
0360 {
0361     u32 int_cntr = host->default_irq_mask;
0362     unsigned long flags;
0363 
0364     WARN_ON(host->cmd != NULL);
0365     host->cmd = cmd;
0366 
0367     switch (mmc_resp_type(cmd)) {
0368     case MMC_RSP_R1: /* short CRC, OPCODE */
0369     case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
0370         cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
0371         break;
0372     case MMC_RSP_R2: /* long 136 bit + CRC */
0373         cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
0374         break;
0375     case MMC_RSP_R3: /* short */
0376         cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
0377         break;
0378     case MMC_RSP_NONE:
0379         break;
0380     default:
0381         dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
0382                 mmc_resp_type(cmd));
0383         cmd->error = -EINVAL;
0384         return -EINVAL;
0385     }
0386 
0387     int_cntr = INT_END_CMD_RES_EN;
0388 
0389     if (mxcmci_use_dma(host)) {
0390         if (host->dma_dir == DMA_FROM_DEVICE) {
0391             host->desc->callback = mxcmci_dma_callback;
0392             host->desc->callback_param = host;
0393         } else {
0394             int_cntr |= INT_WRITE_OP_DONE_EN;
0395         }
0396     }
0397 
0398     spin_lock_irqsave(&host->lock, flags);
0399     if (host->use_sdio)
0400         int_cntr |= INT_SDIO_IRQ_EN;
0401     mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
0402     spin_unlock_irqrestore(&host->lock, flags);
0403 
0404     mxcmci_writew(host, cmd->opcode, MMC_REG_CMD);
0405     mxcmci_writel(host, cmd->arg, MMC_REG_ARG);
0406     mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT);
0407 
0408     return 0;
0409 }
0410 
0411 static void mxcmci_finish_request(struct mxcmci_host *host,
0412         struct mmc_request *req)
0413 {
0414     u32 int_cntr = host->default_irq_mask;
0415     unsigned long flags;
0416 
0417     spin_lock_irqsave(&host->lock, flags);
0418     if (host->use_sdio)
0419         int_cntr |= INT_SDIO_IRQ_EN;
0420     mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
0421     spin_unlock_irqrestore(&host->lock, flags);
0422 
0423     host->req = NULL;
0424     host->cmd = NULL;
0425     host->data = NULL;
0426 
0427     mmc_request_done(host->mmc, req);
0428 }
0429 
0430 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
0431 {
0432     struct mmc_data *data = host->data;
0433     int data_error;
0434 
0435     if (mxcmci_use_dma(host)) {
0436         dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
0437                 host->dma_dir);
0438         mxcmci_swap_buffers(data);
0439     }
0440 
0441     if (stat & STATUS_ERR_MASK) {
0442         dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
0443                 stat);
0444         if (stat & STATUS_CRC_READ_ERR) {
0445             dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
0446             data->error = -EILSEQ;
0447         } else if (stat & STATUS_CRC_WRITE_ERR) {
0448             u32 err_code = (stat >> 9) & 0x3;
0449             if (err_code == 2) { /* No CRC response */
0450                 dev_err(mmc_dev(host->mmc),
0451                     "%s: No CRC -ETIMEDOUT\n", __func__);
0452                 data->error = -ETIMEDOUT;
0453             } else {
0454                 dev_err(mmc_dev(host->mmc),
0455                     "%s: -EILSEQ\n", __func__);
0456                 data->error = -EILSEQ;
0457             }
0458         } else if (stat & STATUS_TIME_OUT_READ) {
0459             dev_err(mmc_dev(host->mmc),
0460                 "%s: read -ETIMEDOUT\n", __func__);
0461             data->error = -ETIMEDOUT;
0462         } else {
0463             dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
0464             data->error = -EIO;
0465         }
0466     } else {
0467         data->bytes_xfered = host->datasize;
0468     }
0469 
0470     data_error = data->error;
0471 
0472     host->data = NULL;
0473 
0474     return data_error;
0475 }
0476 
0477 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
0478 {
0479     struct mmc_command *cmd = host->cmd;
0480     int i;
0481     u32 a, b, c;
0482 
0483     if (!cmd)
0484         return;
0485 
0486     if (stat & STATUS_TIME_OUT_RESP) {
0487         dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
0488         cmd->error = -ETIMEDOUT;
0489     } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
0490         dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
0491         cmd->error = -EILSEQ;
0492     }
0493 
0494     if (cmd->flags & MMC_RSP_PRESENT) {
0495         if (cmd->flags & MMC_RSP_136) {
0496             for (i = 0; i < 4; i++) {
0497                 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
0498                 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
0499                 cmd->resp[i] = a << 16 | b;
0500             }
0501         } else {
0502             a = mxcmci_readw(host, MMC_REG_RES_FIFO);
0503             b = mxcmci_readw(host, MMC_REG_RES_FIFO);
0504             c = mxcmci_readw(host, MMC_REG_RES_FIFO);
0505             cmd->resp[0] = a << 24 | b << 8 | c >> 8;
0506         }
0507     }
0508 }
0509 
0510 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
0511 {
0512     u32 stat;
0513     unsigned long timeout = jiffies + HZ;
0514 
0515     do {
0516         stat = mxcmci_readl(host, MMC_REG_STATUS);
0517         if (stat & STATUS_ERR_MASK)
0518             return stat;
0519         if (time_after(jiffies, timeout)) {
0520             mxcmci_softreset(host);
0521             mxcmci_set_clk_rate(host, host->clock);
0522             return STATUS_TIME_OUT_READ;
0523         }
0524         if (stat & mask)
0525             return 0;
0526         cpu_relax();
0527     } while (1);
0528 }
0529 
0530 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
0531 {
0532     unsigned int stat;
0533     u32 *buf = _buf;
0534 
0535     while (bytes > 3) {
0536         stat = mxcmci_poll_status(host,
0537                 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
0538         if (stat)
0539             return stat;
0540         *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
0541         bytes -= 4;
0542     }
0543 
0544     if (bytes) {
0545         u8 *b = (u8 *)buf;
0546         u32 tmp;
0547 
0548         stat = mxcmci_poll_status(host,
0549                 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
0550         if (stat)
0551             return stat;
0552         tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
0553         memcpy(b, &tmp, bytes);
0554     }
0555 
0556     return 0;
0557 }
0558 
0559 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
0560 {
0561     unsigned int stat;
0562     u32 *buf = _buf;
0563 
0564     while (bytes > 3) {
0565         stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
0566         if (stat)
0567             return stat;
0568         mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS);
0569         bytes -= 4;
0570     }
0571 
0572     if (bytes) {
0573         u8 *b = (u8 *)buf;
0574         u32 tmp;
0575 
0576         stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
0577         if (stat)
0578             return stat;
0579 
0580         memcpy(&tmp, b, bytes);
0581         mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS);
0582     }
0583 
0584     return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
0585 }
0586 
0587 static int mxcmci_transfer_data(struct mxcmci_host *host)
0588 {
0589     struct mmc_data *data = host->req->data;
0590     struct scatterlist *sg;
0591     int stat, i;
0592 
0593     host->data = data;
0594     host->datasize = 0;
0595 
0596     if (data->flags & MMC_DATA_READ) {
0597         for_each_sg(data->sg, sg, data->sg_len, i) {
0598             stat = mxcmci_pull(host, sg_virt(sg), sg->length);
0599             if (stat)
0600                 return stat;
0601             host->datasize += sg->length;
0602         }
0603     } else {
0604         for_each_sg(data->sg, sg, data->sg_len, i) {
0605             stat = mxcmci_push(host, sg_virt(sg), sg->length);
0606             if (stat)
0607                 return stat;
0608             host->datasize += sg->length;
0609         }
0610         stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
0611         if (stat)
0612             return stat;
0613     }
0614     return 0;
0615 }
0616 
0617 static void mxcmci_datawork(struct work_struct *work)
0618 {
0619     struct mxcmci_host *host = container_of(work, struct mxcmci_host,
0620                           datawork);
0621     int datastat = mxcmci_transfer_data(host);
0622 
0623     mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
0624         MMC_REG_STATUS);
0625     mxcmci_finish_data(host, datastat);
0626 
0627     if (host->req->stop) {
0628         if (mxcmci_start_cmd(host, host->req->stop, 0)) {
0629             mxcmci_finish_request(host, host->req);
0630             return;
0631         }
0632     } else {
0633         mxcmci_finish_request(host, host->req);
0634     }
0635 }
0636 
0637 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
0638 {
0639     struct mmc_request *req;
0640     int data_error;
0641     unsigned long flags;
0642 
0643     spin_lock_irqsave(&host->lock, flags);
0644 
0645     if (!host->data) {
0646         spin_unlock_irqrestore(&host->lock, flags);
0647         return;
0648     }
0649 
0650     if (!host->req) {
0651         spin_unlock_irqrestore(&host->lock, flags);
0652         return;
0653     }
0654 
0655     req = host->req;
0656     if (!req->stop)
0657         host->req = NULL; /* we will handle finish req below */
0658 
0659     data_error = mxcmci_finish_data(host, stat);
0660 
0661     spin_unlock_irqrestore(&host->lock, flags);
0662 
0663     if (data_error)
0664         return;
0665 
0666     mxcmci_read_response(host, stat);
0667     host->cmd = NULL;
0668 
0669     if (req->stop) {
0670         if (mxcmci_start_cmd(host, req->stop, 0)) {
0671             mxcmci_finish_request(host, req);
0672             return;
0673         }
0674     } else {
0675         mxcmci_finish_request(host, req);
0676     }
0677 }
0678 
0679 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
0680 {
0681     mxcmci_read_response(host, stat);
0682     host->cmd = NULL;
0683 
0684     if (!host->data && host->req) {
0685         mxcmci_finish_request(host, host->req);
0686         return;
0687     }
0688 
0689     /* For the DMA case the DMA engine handles the data transfer
0690      * automatically. For non DMA we have to do it ourselves.
0691      * Don't do it in interrupt context though.
0692      */
0693     if (!mxcmci_use_dma(host) && host->data)
0694         schedule_work(&host->datawork);
0695 
0696 }
0697 
0698 static irqreturn_t mxcmci_irq(int irq, void *devid)
0699 {
0700     struct mxcmci_host *host = devid;
0701     bool sdio_irq;
0702     u32 stat;
0703 
0704     stat = mxcmci_readl(host, MMC_REG_STATUS);
0705     mxcmci_writel(host,
0706         stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
0707              STATUS_WRITE_OP_DONE),
0708         MMC_REG_STATUS);
0709 
0710     dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
0711 
0712     spin_lock(&host->lock);
0713     sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
0714     spin_unlock(&host->lock);
0715 
0716     if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE)))
0717         mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS);
0718 
0719     if (sdio_irq) {
0720         mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS);
0721         mmc_signal_sdio_irq(host->mmc);
0722     }
0723 
0724     if (stat & STATUS_END_CMD_RESP)
0725         mxcmci_cmd_done(host, stat);
0726 
0727     if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) {
0728         del_timer(&host->watchdog);
0729         mxcmci_data_done(host, stat);
0730     }
0731 
0732     if (host->default_irq_mask &&
0733           (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
0734         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
0735 
0736     return IRQ_HANDLED;
0737 }
0738 
0739 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
0740 {
0741     struct mxcmci_host *host = mmc_priv(mmc);
0742     unsigned int cmdat = host->cmdat;
0743     int error;
0744 
0745     WARN_ON(host->req != NULL);
0746 
0747     host->req = req;
0748     host->cmdat &= ~CMD_DAT_CONT_INIT;
0749 
0750     if (host->dma)
0751         host->do_dma = 1;
0752 
0753     if (req->data) {
0754         error = mxcmci_setup_data(host, req->data);
0755         if (error) {
0756             req->cmd->error = error;
0757             goto out;
0758         }
0759 
0760 
0761         cmdat |= CMD_DAT_CONT_DATA_ENABLE;
0762 
0763         if (req->data->flags & MMC_DATA_WRITE)
0764             cmdat |= CMD_DAT_CONT_WRITE;
0765     }
0766 
0767     error = mxcmci_start_cmd(host, req->cmd, cmdat);
0768 
0769 out:
0770     if (error)
0771         mxcmci_finish_request(host, req);
0772 }
0773 
0774 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
0775 {
0776     unsigned int divider;
0777     int prescaler = 0;
0778     unsigned int clk_in = clk_get_rate(host->clk_per);
0779 
0780     while (prescaler <= 0x800) {
0781         for (divider = 1; divider <= 0xF; divider++) {
0782             int x;
0783 
0784             x = (clk_in / (divider + 1));
0785 
0786             if (prescaler)
0787                 x /= (prescaler * 2);
0788 
0789             if (x <= clk_ios)
0790                 break;
0791         }
0792         if (divider < 0x10)
0793             break;
0794 
0795         if (prescaler == 0)
0796             prescaler = 1;
0797         else
0798             prescaler <<= 1;
0799     }
0800 
0801     mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
0802 
0803     dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
0804             prescaler, divider, clk_in, clk_ios);
0805 }
0806 
0807 static int mxcmci_setup_dma(struct mmc_host *mmc)
0808 {
0809     struct mxcmci_host *host = mmc_priv(mmc);
0810     struct dma_slave_config *config = &host->dma_slave_config;
0811 
0812     config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
0813     config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
0814     config->dst_addr_width = 4;
0815     config->src_addr_width = 4;
0816     config->dst_maxburst = host->burstlen;
0817     config->src_maxburst = host->burstlen;
0818     config->device_fc = false;
0819 
0820     return dmaengine_slave_config(host->dma, config);
0821 }
0822 
0823 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
0824 {
0825     struct mxcmci_host *host = mmc_priv(mmc);
0826     int burstlen, ret;
0827 
0828     /*
0829      * use burstlen of 64 (16 words) in 4 bit mode (--> reg value  0)
0830      * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
0831      */
0832     if (ios->bus_width == MMC_BUS_WIDTH_4)
0833         burstlen = 16;
0834     else
0835         burstlen = 4;
0836 
0837     if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
0838         host->burstlen = burstlen;
0839         ret = mxcmci_setup_dma(mmc);
0840         if (ret) {
0841             dev_err(mmc_dev(host->mmc),
0842                 "failed to config DMA channel. Falling back to PIO\n");
0843             dma_release_channel(host->dma);
0844             host->do_dma = 0;
0845             host->dma = NULL;
0846         }
0847     }
0848 
0849     if (ios->bus_width == MMC_BUS_WIDTH_4)
0850         host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
0851     else
0852         host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
0853 
0854     if (host->power_mode != ios->power_mode) {
0855         host->power_mode = ios->power_mode;
0856         mxcmci_set_power(host, ios->vdd);
0857 
0858         if (ios->power_mode == MMC_POWER_ON)
0859             host->cmdat |= CMD_DAT_CONT_INIT;
0860     }
0861 
0862     if (ios->clock) {
0863         mxcmci_set_clk_rate(host, ios->clock);
0864         mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
0865     } else {
0866         mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK);
0867     }
0868 
0869     host->clock = ios->clock;
0870 }
0871 
0872 static irqreturn_t mxcmci_detect_irq(int irq, void *data)
0873 {
0874     struct mmc_host *mmc = data;
0875 
0876     dev_dbg(mmc_dev(mmc), "%s\n", __func__);
0877 
0878     mmc_detect_change(mmc, msecs_to_jiffies(250));
0879     return IRQ_HANDLED;
0880 }
0881 
0882 static int mxcmci_get_ro(struct mmc_host *mmc)
0883 {
0884     struct mxcmci_host *host = mmc_priv(mmc);
0885 
0886     if (host->pdata && host->pdata->get_ro)
0887         return !!host->pdata->get_ro(mmc_dev(mmc));
0888     /*
0889      * If board doesn't support read only detection (no mmc_gpio
0890      * context or gpio is invalid), then let the mmc core decide
0891      * what to do.
0892      */
0893     return mmc_gpio_get_ro(mmc);
0894 }
0895 
0896 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
0897 {
0898     struct mxcmci_host *host = mmc_priv(mmc);
0899     unsigned long flags;
0900     u32 int_cntr;
0901 
0902     spin_lock_irqsave(&host->lock, flags);
0903     host->use_sdio = enable;
0904     int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR);
0905 
0906     if (enable)
0907         int_cntr |= INT_SDIO_IRQ_EN;
0908     else
0909         int_cntr &= ~INT_SDIO_IRQ_EN;
0910 
0911     mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
0912     spin_unlock_irqrestore(&host->lock, flags);
0913 }
0914 
0915 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
0916 {
0917     struct mxcmci_host *mxcmci = mmc_priv(host);
0918 
0919     /*
0920      * MX3 SoCs have a silicon bug which corrupts CRC calculation of
0921      * multi-block transfers when connected SDIO peripheral doesn't
0922      * drive the BUSY line as required by the specs.
0923      * One way to prevent this is to only allow 1-bit transfers.
0924      */
0925 
0926     if (is_imx31_mmc(mxcmci) && mmc_card_sdio(card))
0927         host->caps &= ~MMC_CAP_4_BIT_DATA;
0928     else
0929         host->caps |= MMC_CAP_4_BIT_DATA;
0930 }
0931 
0932 static bool filter(struct dma_chan *chan, void *param)
0933 {
0934     struct mxcmci_host *host = param;
0935 
0936     if (!imx_dma_is_general_purpose(chan))
0937         return false;
0938 
0939     chan->private = &host->dma_data;
0940 
0941     return true;
0942 }
0943 
0944 static void mxcmci_watchdog(struct timer_list *t)
0945 {
0946     struct mxcmci_host *host = from_timer(host, t, watchdog);
0947     struct mmc_request *req = host->req;
0948     unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS);
0949 
0950     if (host->dma_dir == DMA_FROM_DEVICE) {
0951         dmaengine_terminate_all(host->dma);
0952         dev_err(mmc_dev(host->mmc),
0953             "%s: read time out (status = 0x%08x)\n",
0954             __func__, stat);
0955     } else {
0956         dev_err(mmc_dev(host->mmc),
0957             "%s: write time out (status = 0x%08x)\n",
0958             __func__, stat);
0959         mxcmci_softreset(host);
0960     }
0961 
0962     /* Mark transfer as erroneus and inform the upper layers */
0963 
0964     if (host->data)
0965         host->data->error = -ETIMEDOUT;
0966     host->req = NULL;
0967     host->cmd = NULL;
0968     host->data = NULL;
0969     mmc_request_done(host->mmc, req);
0970 }
0971 
0972 static const struct mmc_host_ops mxcmci_ops = {
0973     .request        = mxcmci_request,
0974     .set_ios        = mxcmci_set_ios,
0975     .get_ro         = mxcmci_get_ro,
0976     .enable_sdio_irq    = mxcmci_enable_sdio_irq,
0977     .init_card      = mxcmci_init_card,
0978 };
0979 
0980 static int mxcmci_probe(struct platform_device *pdev)
0981 {
0982     struct mmc_host *mmc;
0983     struct mxcmci_host *host;
0984     struct resource *res;
0985     int ret = 0, irq;
0986     bool dat3_card_detect = false;
0987     dma_cap_mask_t mask;
0988     struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
0989 
0990     pr_info("i.MX/MPC512x SDHC driver\n");
0991 
0992     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0993     irq = platform_get_irq(pdev, 0);
0994     if (irq < 0)
0995         return irq;
0996 
0997     mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
0998     if (!mmc)
0999         return -ENOMEM;
1000 
1001     host = mmc_priv(mmc);
1002 
1003     host->base = devm_ioremap_resource(&pdev->dev, res);
1004     if (IS_ERR(host->base)) {
1005         ret = PTR_ERR(host->base);
1006         goto out_free;
1007     }
1008 
1009     host->phys_base = res->start;
1010 
1011     ret = mmc_of_parse(mmc);
1012     if (ret)
1013         goto out_free;
1014     mmc->ops = &mxcmci_ops;
1015 
1016     /* For devicetree parsing, the bus width is read from devicetree */
1017     if (pdata)
1018         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1019     else
1020         mmc->caps |= MMC_CAP_SDIO_IRQ;
1021 
1022     /* MMC core transfer sizes tunable parameters */
1023     mmc->max_blk_size = 2048;
1024     mmc->max_blk_count = 65535;
1025     mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1026     mmc->max_seg_size = mmc->max_req_size;
1027 
1028     host->devtype = (uintptr_t)of_device_get_match_data(&pdev->dev);
1029 
1030     /* adjust max_segs after devtype detection */
1031     if (!is_mpc512x_mmc(host))
1032         mmc->max_segs = 64;
1033 
1034     host->mmc = mmc;
1035     host->pdata = pdata;
1036     spin_lock_init(&host->lock);
1037 
1038     if (pdata)
1039         dat3_card_detect = pdata->dat3_card_detect;
1040     else if (mmc_card_is_removable(mmc)
1041             && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1042         dat3_card_detect = true;
1043 
1044     ret = mmc_regulator_get_supply(mmc);
1045     if (ret)
1046         goto out_free;
1047 
1048     if (!mmc->ocr_avail) {
1049         if (pdata && pdata->ocr_avail)
1050             mmc->ocr_avail = pdata->ocr_avail;
1051         else
1052             mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1053     }
1054 
1055     if (dat3_card_detect)
1056         host->default_irq_mask =
1057             INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
1058     else
1059         host->default_irq_mask = 0;
1060 
1061     host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1062     if (IS_ERR(host->clk_ipg)) {
1063         ret = PTR_ERR(host->clk_ipg);
1064         goto out_free;
1065     }
1066 
1067     host->clk_per = devm_clk_get(&pdev->dev, "per");
1068     if (IS_ERR(host->clk_per)) {
1069         ret = PTR_ERR(host->clk_per);
1070         goto out_free;
1071     }
1072 
1073     ret = clk_prepare_enable(host->clk_per);
1074     if (ret)
1075         goto out_free;
1076 
1077     ret = clk_prepare_enable(host->clk_ipg);
1078     if (ret)
1079         goto out_clk_per_put;
1080 
1081     mxcmci_softreset(host);
1082 
1083     host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO);
1084     if (host->rev_no != 0x400) {
1085         ret = -ENODEV;
1086         dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1087             host->rev_no);
1088         goto out_clk_put;
1089     }
1090 
1091     mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1092     mmc->f_max = clk_get_rate(host->clk_per) >> 1;
1093 
1094     /* recommended in data sheet */
1095     mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO);
1096 
1097     mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR);
1098 
1099     if (!host->pdata) {
1100         host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1101         if (IS_ERR(host->dma)) {
1102             if (PTR_ERR(host->dma) == -EPROBE_DEFER) {
1103                 ret = -EPROBE_DEFER;
1104                 goto out_clk_put;
1105             }
1106 
1107             /* Ignore errors to fall back to PIO mode */
1108             host->dma = NULL;
1109         }
1110     } else {
1111         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1112         if (res) {
1113             host->dmareq = res->start;
1114             host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1115             host->dma_data.priority = DMA_PRIO_LOW;
1116             host->dma_data.dma_request = host->dmareq;
1117             dma_cap_zero(mask);
1118             dma_cap_set(DMA_SLAVE, mask);
1119             host->dma = dma_request_channel(mask, filter, host);
1120         }
1121     }
1122     if (host->dma)
1123         mmc->max_seg_size = dma_get_max_seg_size(
1124                 host->dma->device->dev);
1125     else
1126         dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
1127 
1128     INIT_WORK(&host->datawork, mxcmci_datawork);
1129 
1130     ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0,
1131                    dev_name(&pdev->dev), host);
1132     if (ret)
1133         goto out_free_dma;
1134 
1135     platform_set_drvdata(pdev, mmc);
1136 
1137     if (host->pdata && host->pdata->init) {
1138         ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1139                 host->mmc);
1140         if (ret)
1141             goto out_free_dma;
1142     }
1143 
1144     timer_setup(&host->watchdog, mxcmci_watchdog, 0);
1145 
1146     mmc_add_host(mmc);
1147 
1148     return 0;
1149 
1150 out_free_dma:
1151     if (host->dma)
1152         dma_release_channel(host->dma);
1153 
1154 out_clk_put:
1155     clk_disable_unprepare(host->clk_ipg);
1156 out_clk_per_put:
1157     clk_disable_unprepare(host->clk_per);
1158 
1159 out_free:
1160     mmc_free_host(mmc);
1161 
1162     return ret;
1163 }
1164 
1165 static int mxcmci_remove(struct platform_device *pdev)
1166 {
1167     struct mmc_host *mmc = platform_get_drvdata(pdev);
1168     struct mxcmci_host *host = mmc_priv(mmc);
1169 
1170     mmc_remove_host(mmc);
1171 
1172     if (host->pdata && host->pdata->exit)
1173         host->pdata->exit(&pdev->dev, mmc);
1174 
1175     if (host->dma)
1176         dma_release_channel(host->dma);
1177 
1178     clk_disable_unprepare(host->clk_per);
1179     clk_disable_unprepare(host->clk_ipg);
1180 
1181     mmc_free_host(mmc);
1182 
1183     return 0;
1184 }
1185 
1186 static int mxcmci_suspend(struct device *dev)
1187 {
1188     struct mmc_host *mmc = dev_get_drvdata(dev);
1189     struct mxcmci_host *host = mmc_priv(mmc);
1190 
1191     clk_disable_unprepare(host->clk_per);
1192     clk_disable_unprepare(host->clk_ipg);
1193     return 0;
1194 }
1195 
1196 static int mxcmci_resume(struct device *dev)
1197 {
1198     struct mmc_host *mmc = dev_get_drvdata(dev);
1199     struct mxcmci_host *host = mmc_priv(mmc);
1200     int ret;
1201 
1202     ret = clk_prepare_enable(host->clk_per);
1203     if (ret)
1204         return ret;
1205 
1206     ret = clk_prepare_enable(host->clk_ipg);
1207     if (ret)
1208         clk_disable_unprepare(host->clk_per);
1209 
1210     return ret;
1211 }
1212 
1213 static DEFINE_SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume);
1214 
1215 static struct platform_driver mxcmci_driver = {
1216     .probe      = mxcmci_probe,
1217     .remove     = mxcmci_remove,
1218     .driver     = {
1219         .name       = DRIVER_NAME,
1220         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1221         .pm = pm_sleep_ptr(&mxcmci_pm_ops),
1222         .of_match_table = mxcmci_of_match,
1223     }
1224 };
1225 
1226 module_platform_driver(mxcmci_driver);
1227 
1228 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1229 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1230 MODULE_LICENSE("GPL");
1231 MODULE_ALIAS("platform:mxc-mmc");
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