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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  Copyright (C) 2008 Marvell Semiconductors, All Rights Reserved.
0004  */
0005 
0006 #ifndef __MVSDIO_H
0007 #define __MVSDIO_H
0008 
0009 /*
0010  * Clock rates
0011  */
0012 
0013 #define MVSD_CLOCKRATE_MAX          50000000
0014 #define MVSD_BASE_DIV_MAX           0x7ff
0015 
0016 
0017 /*
0018  * Register offsets
0019  */
0020 
0021 #define MVSD_SYS_ADDR_LOW           0x000
0022 #define MVSD_SYS_ADDR_HI            0x004
0023 #define MVSD_BLK_SIZE               0x008
0024 #define MVSD_BLK_COUNT              0x00c
0025 #define MVSD_ARG_LOW                0x010
0026 #define MVSD_ARG_HI             0x014
0027 #define MVSD_XFER_MODE              0x018
0028 #define MVSD_CMD                0x01c
0029 #define MVSD_RSP(i)             (0x020 + ((i)<<2))
0030 #define MVSD_RSP0               0x020
0031 #define MVSD_RSP1               0x024
0032 #define MVSD_RSP2               0x028
0033 #define MVSD_RSP3               0x02c
0034 #define MVSD_RSP4               0x030
0035 #define MVSD_RSP5               0x034
0036 #define MVSD_RSP6               0x038
0037 #define MVSD_RSP7               0x03c
0038 #define MVSD_FIFO               0x040
0039 #define MVSD_RSP_CRC7               0x044
0040 #define MVSD_HW_STATE               0x048
0041 #define MVSD_HOST_CTRL              0x050
0042 #define MVSD_BLK_GAP_CTRL           0x054
0043 #define MVSD_CLK_CTRL               0x058
0044 #define MVSD_SW_RESET               0x05c
0045 #define MVSD_NOR_INTR_STATUS            0x060
0046 #define MVSD_ERR_INTR_STATUS            0x064
0047 #define MVSD_NOR_STATUS_EN          0x068
0048 #define MVSD_ERR_STATUS_EN          0x06c
0049 #define MVSD_NOR_INTR_EN            0x070
0050 #define MVSD_ERR_INTR_EN            0x074
0051 #define MVSD_AUTOCMD12_ERR_STATUS       0x078
0052 #define MVSD_CURR_BYTE_LEFT         0x07c
0053 #define MVSD_CURR_BLK_LEFT          0x080
0054 #define MVSD_AUTOCMD12_ARG_LOW          0x084
0055 #define MVSD_AUTOCMD12_ARG_HI           0x088
0056 #define MVSD_AUTOCMD12_CMD          0x08c
0057 #define MVSD_AUTO_RSP(i)            (0x090 + ((i)<<2))
0058 #define MVSD_AUTO_RSP0              0x090
0059 #define MVSD_AUTO_RSP1              0x094
0060 #define MVSD_AUTO_RSP2              0x098
0061 #define MVSD_CLK_DIV                0x128
0062 
0063 #define MVSD_WINDOW_CTRL(i)         (0x108 + ((i) << 3))
0064 #define MVSD_WINDOW_BASE(i)         (0x10c + ((i) << 3))
0065 
0066 
0067 /*
0068  * MVSD_CMD
0069  */
0070 
0071 #define MVSD_CMD_RSP_NONE           (0 << 0)
0072 #define MVSD_CMD_RSP_136            (1 << 0)
0073 #define MVSD_CMD_RSP_48             (2 << 0)
0074 #define MVSD_CMD_RSP_48BUSY         (3 << 0)
0075 
0076 #define MVSD_CMD_CHECK_DATACRC16        (1 << 2)
0077 #define MVSD_CMD_CHECK_CMDCRC           (1 << 3)
0078 #define MVSD_CMD_INDX_CHECK         (1 << 4)
0079 #define MVSD_CMD_DATA_PRESENT           (1 << 5)
0080 #define MVSD_UNEXPECTED_RESP            (1 << 7)
0081 #define MVSD_CMD_INDEX(x)           ((x) << 8)
0082 
0083 
0084 /*
0085  * MVSD_AUTOCMD12_CMD
0086  */
0087 
0088 #define MVSD_AUTOCMD12_BUSY         (1 << 0)
0089 #define MVSD_AUTOCMD12_INDX_CHECK       (1 << 1)
0090 #define MVSD_AUTOCMD12_INDEX(x)         ((x) << 8)
0091 
0092 /*
0093  * MVSD_XFER_MODE
0094  */
0095 
0096 #define MVSD_XFER_MODE_WR_DATA_START        (1 << 0)
0097 #define MVSD_XFER_MODE_HW_WR_DATA_EN        (1 << 1)
0098 #define MVSD_XFER_MODE_AUTO_CMD12       (1 << 2)
0099 #define MVSD_XFER_MODE_INT_CHK_EN       (1 << 3)
0100 #define MVSD_XFER_MODE_TO_HOST          (1 << 4)
0101 #define MVSD_XFER_MODE_STOP_CLK         (1 << 5)
0102 #define MVSD_XFER_MODE_PIO          (1 << 6)
0103 
0104 
0105 /*
0106  * MVSD_HOST_CTRL
0107  */
0108 
0109 #define MVSD_HOST_CTRL_PUSH_PULL_EN         (1 << 0)
0110 
0111 #define MVSD_HOST_CTRL_CARD_TYPE_MEM_ONLY   (0 << 1)
0112 #define MVSD_HOST_CTRL_CARD_TYPE_IO_ONLY    (1 << 1)
0113 #define MVSD_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO   (2 << 1)
0114 #define MVSD_HOST_CTRL_CARD_TYPE_IO_MMC     (3 << 1)
0115 #define MVSD_HOST_CTRL_CARD_TYPE_MASK       (3 << 1)
0116 
0117 #define MVSD_HOST_CTRL_BIG_ENDIAN       (1 << 3)
0118 #define MVSD_HOST_CTRL_LSB_FIRST        (1 << 4)
0119 #define MVSD_HOST_CTRL_DATA_WIDTH_4_BITS    (1 << 9)
0120 #define MVSD_HOST_CTRL_HI_SPEED_EN      (1 << 10)
0121 
0122 #define MVSD_HOST_CTRL_TMOUT_MAX        0xf
0123 #define MVSD_HOST_CTRL_TMOUT_MASK       (0xf << 11)
0124 #define MVSD_HOST_CTRL_TMOUT(x)         ((x) << 11)
0125 #define MVSD_HOST_CTRL_TMOUT_EN         (1 << 15)
0126 
0127 
0128 /*
0129  * MVSD_SW_RESET
0130  */
0131 
0132 #define MVSD_SW_RESET_NOW           (1 << 8)
0133 
0134 
0135 /*
0136  * Normal interrupt status bits
0137  */
0138 
0139 #define MVSD_NOR_CMD_DONE           (1 << 0)
0140 #define MVSD_NOR_XFER_DONE          (1 << 1)
0141 #define MVSD_NOR_BLK_GAP_EVT            (1 << 2)
0142 #define MVSD_NOR_DMA_DONE           (1 << 3)
0143 #define MVSD_NOR_TX_AVAIL           (1 << 4)
0144 #define MVSD_NOR_RX_READY           (1 << 5)
0145 #define MVSD_NOR_CARD_INT           (1 << 8)
0146 #define MVSD_NOR_READ_WAIT_ON           (1 << 9)
0147 #define MVSD_NOR_RX_FIFO_8W         (1 << 10)
0148 #define MVSD_NOR_TX_FIFO_8W         (1 << 11)
0149 #define MVSD_NOR_SUSPEND_ON         (1 << 12)
0150 #define MVSD_NOR_AUTOCMD12_DONE         (1 << 13)
0151 #define MVSD_NOR_UNEXP_RSP          (1 << 14)
0152 #define MVSD_NOR_ERROR              (1 << 15)
0153 
0154 
0155 /*
0156  * Error status bits
0157  */
0158 
0159 #define MVSD_ERR_CMD_TIMEOUT            (1 << 0)
0160 #define MVSD_ERR_CMD_CRC            (1 << 1)
0161 #define MVSD_ERR_CMD_ENDBIT         (1 << 2)
0162 #define MVSD_ERR_CMD_INDEX          (1 << 3)
0163 #define MVSD_ERR_DATA_TIMEOUT           (1 << 4)
0164 #define MVSD_ERR_DATA_CRC           (1 << 5)
0165 #define MVSD_ERR_DATA_ENDBIT            (1 << 6)
0166 #define MVSD_ERR_AUTOCMD12          (1 << 8)
0167 #define MVSD_ERR_CMD_STARTBIT           (1 << 9)
0168 #define MVSD_ERR_XFER_SIZE          (1 << 10)
0169 #define MVSD_ERR_RESP_T_BIT         (1 << 11)
0170 #define MVSD_ERR_CRC_ENDBIT         (1 << 12)
0171 #define MVSD_ERR_CRC_STARTBIT           (1 << 13)
0172 #define MVSD_ERR_CRC_STATUS         (1 << 14)
0173 
0174 
0175 /*
0176  * CMD12 error status bits
0177  */
0178 
0179 #define MVSD_AUTOCMD12_ERR_NOTEXE       (1 << 0)
0180 #define MVSD_AUTOCMD12_ERR_TIMEOUT      (1 << 1)
0181 #define MVSD_AUTOCMD12_ERR_CRC          (1 << 2)
0182 #define MVSD_AUTOCMD12_ERR_ENDBIT       (1 << 3)
0183 #define MVSD_AUTOCMD12_ERR_INDEX        (1 << 4)
0184 #define MVSD_AUTOCMD12_ERR_RESP_T_BIT       (1 << 5)
0185 #define MVSD_AUTOCMD12_ERR_RESP_STARTBIT    (1 << 6)
0186 
0187 #endif